ECE 353 Introduction to Microprocessor Systems

ECE 353Introduction to Microprocessor Systems

Michael G. Morrow, P.E.

Week 11

TopicsSystem Timing Hardware/Software trade-offs Execution time

Bus Timing WAIT states Memory device timing parameters Timing compatibility

Time Measurement Delay loops Hardware Timers

System TimingHardware/Software trade-offs Soft vs. hard real-time systems Task allocation Microprocessor clock frequency

Execution time Affected by numerous variables Difficult to predict Sample Instructions Delay loops

WAIT StatesWAIT states are used to lengthen the bus cycle for slower devices Extra T3 states are run

WAIT state control CSU WS setting READY signal

Normally ready Normally not-ready External circuits

CSU RDY setting

Memory Device TimingRead Cycle TAA / TOH TACS / TCHZ TOE / TOHZ TRC Effect of grounding device’s /CS

Write Cycle /WE vs. /CS controlled Timing Parameters Write cycle

27C512EPROM

HM624100HCSRAM

Timing CompatibilityNeed to determine if devices are compatible with the microprocessor at the selected clock speed.Want to use the cheapest (usually the slowest) parts we can get by with.Two basic timing issues to resolve: Setup and Hold Times

Latching information (inputs) Output Delay and Float Times

Turning drivers on and off (outputs)

Assessing Timing Compatibility

Need to know whether CPU will operate with the TAA for given device. (read cycle) Address valid at start of T1 Data is latched by CPU at start of T4

To get an accurate TAVDV, must include the delays for the address becoming valid, and include the setup time for data. Address valid delay relative to CLKOUT edge Setup time required relative to CLKOUT edge A.C. Specifications 1 & 2

System Timing Compatibility

Need to account for all delays in a system to assess timing compatibility.Consider the system in Fig 13.5-2.Analyze the read timing with regard to: TACC – address access time TCE – chip enable to valid data TOE – output enable to valid data TDF – output hold time

How do wait states impact the timing?Read Cycle A.C. Specs 1 , 2 Relative timings

System Timing Compatibility

Consider the system in Fig 13.5-2.Analyzing write cycle timing. TW, TDW, TDH TASW, TAW, TCW TWR

This is not the entire story – if there is excessive capacitance, long wires, etc., you must account for the delays.Other bus effects

80C188EB Timer/Counter Unit

Three independent timer/countersTimer/counter modules used to Generate signals with specified frequency /

duty cycle Count external events, measure pulses Generate absolute delays, periodic interrupts

Timer 0/1 Modes of operation

Continuous / Non-continuous Single or Dual Maximum Count Input Sources

Flowchart Configured and operated through PCB registers

T0CON, T0CNT, T0CMPA, T0CMPB

80C188EB Timer/Counter Unit

Timers 2 is much more limited. Operated through PCB registers

T2CON, T2CNT, T2CMPA, T2CMPB Useful as a prescaler or as a periodic

interrupt source.

Timer applications Frequency measurement. Waveform generation.

82C54 PIT/CProvides additional timer/counter resources for microprocessor system. Appears as 4 byte-wide registers

Control register (3) Timer registers (0,1,2)

Program by writing 3 bytes in sequence Control byte Timer word

Three independent 16-bit counters BCD or binary DC-10MHz input range Multiple modes of operation

Real-Time ClocksRTCs provide microprocessor systems absolute time information Typically operate from 32.768KHz

crystal Battery back-up Periodic interrupts Often contain small amount of RAM –

historically this was where the PC stored its configuration settings since it is non-volatile.

Dallas Semiconductor DS12887

Watchdog TimersWatchdog timers are used to guard a system against lock-up due to software errors or soft-failures in hardware. Often included in CPU supervisor circuits.

Retriggering usually done in the main program loop.Watchdog output can be used to reset the CPU or as an NMI.Maxim MAX6323/MAX6324

Wrapping UpHomework #6 due Friday, 11/30/2001Exam #2 on Tuesday, 11/20/2001 at 7:15pm in 132 Nolan (same as Exam #1)

WAIT States

WAIT State Generator

Chip-Select Start Reg

Chip-Select Stop Register -Part 2

Memory Device Read Cycle

Memory Device Write Cycle

Instruction Execution Times

Input Setup and Hold

Output Delay and Float

Read Cycle

A.C. Specs (1)

A.C. Specs (2)

Relative Timing

Write Cycle

Fig. 13.5-2

TxCONPart 1

TxCONPart 2

T2CON

Timer/Counter Block Diagram

Timer 0/1

Timer Modes

Timer 0/1Flowchart

Timer 0/1Flowchart

Frequency Measurement

DS12887RTC

MAX6323

82C54 PIT/C