ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #11) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.
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ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #11) The slides included herein were taken from the materials.
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ECE 331 – Digital System Design
Single-bit Adder Circuitsand
Adder Circuits in VHDL
(Lecture #11)
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Fall 2010 ECE 331 - Digital System Design 2
The Half Adder (HA)
Fall 2010 ECE 331 - Digital System Design 3
The Half Adder
0 0 1 1+ 0 + 1 + 0 + 1 0 1 1 10
Sum Carry Sum
Fall 2010 ECE 331 - Digital System Design 4
The Half Adder
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Truth Table
Fall 2010 ECE 331 - Digital System Design 5
The Half Adder
Exercise:
1. Derive the Boolean expressions for the sum and the carry outputs.2. Draw the associated combinational logic
circuit diagrams.
Fall 2010 ECE 331 - Digital System Design 6
The Full Adder (FA)
Fall 2010 ECE 331 - Digital System Design 7
The Full Adder
0 0 0 00 0 1 1
+ 0 + 1 + 0 + 1 0 1 1 10
Carry-out Sum
1 1 1 10 0 1 1
+ 0 + 1 + 0 + 1 1 10 10 11
Carry-in
Fall 2010 ECE 331 - Digital System Design 8
The Full Adder
A B Cin Sum Cout0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Truth Table
Fall 2010 ECE 331 - Digital System Design 9
The Full Adder
Exercise:
1. Derive the Boolean expressions for the sum and the carry outputs.2. Draw the associated combinational logic
circuit diagrams.
Fall 2010 ECE 331 - Digital System Design 10
The Full Adder
Exercise:
Design a Full Adder using
2 Half Adders1 OR gate
Fall 2010 ECE 331 - Digital System Design 11
The Full Adder
Half Adder
Half Adder
A
B
CinSum
Cout
Fall 2010 ECE 331 - Digital System Design 12
More VHDL Fundamentals
Fall 2010 ECE 331 - Digital System Design 13
VHDL: Components Specify the logical sub-circuits (i.e. components) that
will be used in a hierarchical design. Define the interface to the sub-circuit.
Uses the same format as the Entity Statement.
Sub-circuits are interconnected using “wires”. This is known as Structural VHDL.
The architecture statement for the sub-circuit may be included in the same file as the upper level design or in a separate file.
If included in a separate file, it must be compiled prior to compilation of the upper level design.
Fall 2010 ECE 331 - Digital System Design 14
VHDL: Components
COMPONENT <component name> PORT ( <interface signals> : mode
type ) ;END COMPONENT ;
Component Statement
Component Instantiation<instance name> : <component name> PORT MAP ( <component port names> => <signal names> ) ;
ENTITY fulladd ISPORT ( Cin, A, B : IN STD_LOGIC ; Sum, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE Structure OF fulladd IS SIGNAL s1, c1, c2: STD_LOGIC ;BEGIN ha1 : halfadd PORT MAP ( A => A, B => B, Sum => s1, Cout => c1 ) ; ha2 : halfadd PORT MAP ( s1, Cin, Sum, c2 ); Cout <= c1 OR c2 ;END Structure ;