ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Examples

ECE 3110: Introduction to Digital Systems

Chapter 6

Combinational Logic Design Examples

Barrel ShifterSpeical purpose

Encoders/Comparators

1

10

100

Ex. 5.46Ex.

5.19

HW solutions

Design examples using combinational building blocks (decoders, encoders, multiplexers, comparators, three-state devices, adders).

Barrel shifter Dual-priority encoder Cascading comparators, mode-dependent

comparator

Barrel shifter design example n data inputs, n data outputs Control inputs specify number of

positions to rotate or shift data inputs

Example: n = 16 DIN[15:0], DOUT[15:0], S[3:0] (shift

amount) Many possible solutions, all based on

multiplexers

Multiplexers (mux)

Select one of n sources of data to transmit on a bus.

Eg. Put between Processor’s registers and ALUA 16-bit processor where 3-bit field specifies on of 8 registers.The 3-bit field is connected to the select inputs of an 8-input, 16-bit mux.

MSI: 74x1518-input 1-bit multiplexer

16-to-1 barrel shifter

16-to-1 mux = 2 x 74x151 8-to-1 mux + NAND gate

4 16-bit 2-to-1 muxes

16-bit 2-to-1 mux = 4 x 74x157 4-bit 2-to-1 mux

Properties of different approaches

Dual-Priority Encoder A priority encoder identifies not

only the highest but also the second-highest-priority asserted signal among a set of 8 request inputs.

Single-priority encoder

01001001

01001001

Parallel Cascading Comparators

74x85: serial cascading scheme, delay of propagating the cascading signals through a cascade of comparators.

74x682: Parallel approach, used to build very wide comparators. Build 24-bit comparator, using 3 74x682 PEQQ=EQ2.EQ1.EQ0 PGTQ=GT2+EQ2.GT1+EQ2.EQ1.GT0

8 bit Comparator

B0

A1

B1

A2

B2

A3

A0

B3

74x85

A<BIN

A=BIN

A>BIN

A<BOUT

A=B OUT

A>BOUT

B0

A1

B1

A2

B2

A3

A0

B3

74x85

A<BIN

A=BIN

A>BIN

A<BOUT

A=B OUT

A>BOUT

B0

A1

B1

A2

B2

A3

A0

B3

B4

A5

B5

A6

B6

A7

A4

B7

+5V

A<B

A=B A>B

Most Significant bitsLeast Significant bits

Mode-dependent Comparator

Design a c.c. whose inputs are two 8-bit unsigned binary integers(X,Y), and a control signal(MIN/MAX). The output is an 8-bit unsigned binary integer Z, such that Z=min(X,Y) if MIN/MAX=1; Z=max(X,Y) otherwise

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Sequential Logic Introduction