ECE 2300 Digital Logic & Computer Organization...Lecture 12: 4 Example: Hold Time Analysis with Clock Skew combinational logic CLOCK FF1 FF2 Prop Delay (ns) Setup Time (ns) Hold Time

Lecture 12:

Spring 2018

1

ECE 2300Digital Logic & Computer Organization

Two’s Complement RepresentationBinary Arithmetic

Lecture 12: 2

• HW4 due tomorrow

• HW5 will be released tonight

• Lab 3 report due next Monday/Tuesday– Form group before the submission

• A batch of raw quiz scores released on CMS

Announcements

Lecture 12: 3

Example: Setup Time Analysis

• Assumptions: (1) Uniform gate delay = 1ns(2) FF propagation delay = 1ns (3) Setup time = 3ns, hold time = 2ns

• What’s the best achievable cycle time?

CLOCK

X

Y

S F

tclk >= tffpd(max) + tcomb(max) + tsetup = 1 + 3 + 3 = 7ns

Lecture 12: 4

Example: Hold Time Analysis with Clock Skewcombinational

logic

CLOCK

FF1 FF2

Prop Delay (ns) Setup Time (ns)

Hold Time (ns)min max

FF 1 7 3 1

Comb 3 9 - -

Clock may arrive at FF2 up to 3ns later than FF1

• Hold time at FF2 met?tffpd(min) + tcomb(min) >= thold + tskew(max)

1 + 3 >= 1 + 3 The hold time constraint is met

Lecture 12: 5

• To achieve a higher clock frequency, would you prefer – a smaller hold time or a larger one?

– a smaller setup time or a larger one?

– a negative clock skew or a positive one?• a smaller skew or a larger one?

Timing Analysis Discussions

Lecture 12:

Course Content• Binary numbers and logic gates• Boolean algebra and combinational logic• Sequential logic and state machines• Binary arithmetic• Memories

• Instruction set architecture• Processor organization• Caches and virtual memory• Input/output

6

Lecture 12:

Unsigned Binary Integers• An n-bit unsigned number represents 2n integer values

– From 0 to 2n-1

22 21 20 value0 0 0 00 0 1 10 1 0 20 1 1 31 0 0 41 0 1 51 1 0 61 1 1 7

7

Lecture 12:

• For the binary number bn-1bn-2…b1b0.b-1b-2…b-mthe decimal number is

• Examples101.0012 = ?

Sn-1

i=-mD = bi•2i

Unsigned Binary Fractions

8

Lecture 12:

Unsigned Binary Addition• Just like base-10

– Add from right to left, propagating carry

10010 10010 01111+ 01001 + 01011 + 00011

10111+ 111

carry

1001 0

1 1 11 0

(18)

(9)

(27)

(18)

(11)

(29)

(15)

(3)

(18)

(23)

(7)

(30)

9

Lecture 12:

Signed Magnitude Representation• Most significant bit is used as a sign bit

– Sign bit of 0 for positive (0101 = 5)– Sign bit of 1 for negative (1101 = -5)

• Range is from -(2n-1-1) to (2n-1-1) for an n-bit number

• Two representations for zero (+0 and -0)

• Does ordinary binary addition still work?0010 (2)

+ 1010 (-2)

1100 (not 0)

10

Lecture 12: 11

01

2

3

-4

-1

-2

-3

000

001

010

011

100

101

110

111

Another Encoding of Binary Numbers

Wrap-around point

Lecture 12:

• MSB has weight -2n-1

• Range of an n-bit number: -2n-1 through 2n-1-1– Most negative number (-2n-1) has no positive

counterpart -22 21 20

0 0 0 00 0 1 10 1 0 20 1 1 31 0 0 -41 0 1 -31 1 0 -21 1 1 -1

12

Two’s Complement Representation

Lecture 12:

Two’s Complement Addition• Procedure for addition is the same as

unsigned addition regardless of the signs of the numbers

13

011 (3)

+ 101 (-3)

000 (0)

Lecture 12:

Sign Extension• Replicate the MSB (sign bit)

• Necessary for adding a two’s complement numbers of different lengths

4-bit 8-bit0100 (4) 00000100 (still 4)1100 (-4) 11111100 (still -4)

14

Lecture 12:

Fixed Size Representation• Microprocessors usually represent numbers as fixed size

n-bit values

• Result of adding two n-bit integers is stored as n bits

• Integers are typically 32 or 64 bits (words)– 4 or 8 bytes– byte = 8 bits

15

Lecture 12:

2 0010+ 3 0011

2 0010+ -3 1101

-2 1110+ 6 0110

-2 1110+ -6 1010

7 0111+ 6 0110

-7 1001+ -4 1100

5 0101 -1 1111 4 0100

-8 1000 -3 1101 5 0101

Fixed Size Addition

• Examples with n = 4

Something went wrong!

16

Lecture 12:

Overflow• If operands are too big, sum cannot be

represented as n-bit 2’s complement number

• Overflow occurs if– Signs of both operands are the same, and– Sign of sum is different

• Another test (easy to do in hardware)– Carry into MSB does not equal carry out

01000 (8) 11000 (-8)+ 01001 (9) + 10111 (-9)10001 (-15) 01111 (+15)

17

Lecture 12:

Did Overflow Occur?

11110010+ 01010011

01110010+ 01010011

11000101

1

01000101

18

111 11111

NOYES

Lecture 12:

Two’s Complement Representation• Positive numbers and zero are same as

unsigned binary representation

• To get two’s complement negative notation of an integer– Flip every bit first– Then add one

19

011 (3) 01001 (9)

100 (1’s comp) (1’s comp)

+ 1 + 1101 (-3) 10111 (-9)

10110

Lecture 12: 20

(-X) = (X’+1)• To get two’s complement negative notation of

an integer – Flip every bit first – Then add one 0

1

2

3

-4

-1

-2

-3

000

001

010

011

100

101

110

111

X’X’+1

011 (3)

100 (1’s comp)

+ 1101 (-3)

Lecture 12:

Two’s Complement (2’s C) Shortcut• To get -X

– Copy bits from right to left up to and including the first “1”

– Flip remaining bits to the left

011010000 011010000100101111 (1’s comp)

+ 1100110000 100110000

(copy)(flip)

21

Lecture 12:

Converting Binary (2’s C) to Decimal1. If MSB = 1, take two’s complement to get a

positive number2. Add powers of 2 for bit positions that have a “1”3. If original number was negative,

add a minus sign

X = 11100110two -X = 00011010

= 24+23+21 = 16+8+2= 26ten

X = -26ten

22Assuming 8-bit 2’s complement numbers

n 2n

0 11 22 43 84 165 326 647 1288 2569 512

10 1024

Lecture 12:

Converting Decimal to Binary (2’s C)First Method: Division1. Change to nonnegative decimal number2. Divide by two – remainder is least significant bit3. Keep dividing by two until answer is zero,

recording remainders from right (LSB) to left4. Append a zero as the MSB;

if original number X was negative, return X’+1

X = 104ten 104/2 = 52 r0 bit 0 = 052/2 = 26 r0 bit 1 = 026/2 = 13 r0 bit 2 = 013/2 = 6 r1 bit 3 = 16/2 = 3 r0 bit 4 = 03/2 = 1 r1 bit 5 = 11/2 = 0 r1 bit 6 = 1

X = 01101000two

23

Lecture 12:

Converting Decimal to Binary (2’s C)Second Method: Subtract Powers of Two1. Change to nonnegative decimal number2. Subtract largest power of two

less than or equal to number3. Put a one in the corresponding bit position4. Keep subtracting until result is zero5. Append a zero as MSB;

if original was X negative, return X’+1

X = 104ten 104 - 64 = 40 bit 6 = 140 - 32 = 8 bit 5 = 1

8 - 8 = 0 bit 3 = 1X = 01101000two

n 2n

0 11 22 43 84 165 326 647 1288 2569 512

10 1024

24

Lecture 12:

Full Adder (1 bit Adder with Carry)• Inputs: A, B and Cin (carry-in)• Outputs: S (sum) and Cout (carry-out)

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

25

ABCin

S

Cout

Lecture 12:

Full-Adder Circuit Symbol

A B

Cout Cin

S

26

ABCin

S

Cout

FA

OR

Lecture 12:

Before Next Class • H&H 5.5

Next Time

More Binary Arithmetic ALU

27