ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 5: Data Transfer Instructions / Control Flow Instructions Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy, and classes taught by Ryan Kastner at UCSB
22
Embed
ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 5: Data Transfer Instructions / Control Flow Instructions Partially adapted from Computer.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
ECE 15B Computer OrganizationSpring 2010
Dmitri Strukov
Lecture 5: Data Transfer Instructions / Control Flow Instructions
Partially adapted from Computer Organization and Design, 4th edition, Patterson and Hennessy, and classes taught by Ryan Kastner at UCSB
ECE 15B Spring 2010
Last Lecture: Load and Store Instructions
CPU overview
ECE 15B Spring 2010
Memory Operands• Main memory used for composite data– Arrays, structures, dynamic data
• To apply arithmetic operations– Load values from memory into registers– Store result from register to memory
• Memory is byte addressed– Each address identifies an 8-bit byte
• Words are aligned in memory– Address must be a multiple of 4
• MIPS is Big Endian– Most-significant byte at least address of a word– c.f. Little Endian: least-significant byte at least address
ECE 15B Spring 2010
ECE 15B Spring 2010
Data Transfer: Memory to Register• MIPS load Instruction Syntax lw register#, offset(register#) (1) (2) (3) (4)
Where1) operation name
2) register that will receive value 3) numerical offset in bytes 4) register containing pointer to memory
lw – meaning Load Word32 bits or one word are loaded at a time
ECE 15B Spring 2010
Data Transfer: Register to Memory• MIPS store Instruction Syntax sw register#, offset(register#) (1) (2) (3) (4)
Where1) operation name
2) register that will be written in memory 3) numerical offset in bytes 4) register containing pointer to memory
sw – meaning Store Word32 bits or one word are stored at a time
Memory Operand Example 1
• C code:g = h + A[8];– g in $s1, h in $s2, base address of A in $s3
• Compiled MIPS code:– Index 8 requires offset of 32• 4 bytes per word
lw $t0, 32($s3) # load wordadd $s1, $s2, $t0
offset base register
ECE 15B Spring 2010
Memory Operand Example 2
• C code:A[12] = h + A[8];– h in $s2, base address of A in $s3
• Compiled MIPS code:– Index 8 requires offset of 32lw $t0, 32($s3) # load wordadd $t0, $s2, $t0sw $t0, 48($s3) # store word
ECE 15B Spring 2010
Registers vs. Memory
• Registers are faster to access than memory• Operating on memory data requires loads and
stores– More instructions to be executed
• Compiler must use registers for variables as much as possible– Only spill to memory for less frequently used
variables– Register optimization is important!
ECE 15B Spring 2010
Byte/Halfword Operations
• MIPS byte/halfword load/store– String processing is a common case
lb rt, offset(rs) lh rt, offset(rs)– Sign extend to 32 bits in rt
lbu rt, offset(rs) lhu rt, offset(rs)– Zero extend to 32 bits in rt
sb rt, offset(rs) sh rt, offset(rs)– Store just rightmost byte/halfword
Why do we need them? characters and multimedia data are expressed by less than 32 bits;
having dedicated 8 and 16 bits load and store instructions results in faster operation
ECE 15B Spring 2010
ECE 15B Spring 2010
Control Flow Instructions
Conditional Operations
• Branch to a labeled instruction if a condition is true– Otherwise, continue sequentially
• beq rs, rt, L1– if (rs == rt) branch to instruction labeled L1;
• bne rs, rt, L1– if (rs != rt) branch to instruction labeled L1;
• j L1– unconditional jump to instruction labeled L1
(note that in this case the variable i is not used at all. The last line is just to make C code functionally equivalent to assembly code, since in C variable i will be equal to 11 after the completion of the loop)1 control flow instructions + 4 other instructions in the loop