ecad \...

$Page 1: ecad \ nkjnkfgrjkhbejkrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr$
This document is under revision. Your feedback is valuable! Please send your comments to Arash Tabibiazar: [email protected]

DepartmentofElectricalandComputerEngineering

ECE124LabManualDigitalCircuitsandSystems

This manual is for the exclusive use of registered students in the course. Reproduction for any other purpose is prohibited.

Winter2012

ECE124LabManual‐DigitalCircuitsandSystemshttps://ece.uwaterloo.ca/~ece124/

2

Table of Contents 1 Introduction 3

1.1 Field Programmable Gate Arrays (FPGAs) 4 1.2 Altera Quartus-II FPGA design software 5 1.3 DE2 FPGA board peripherals 5

1.3.1 Light Emitting Diodes (LEDs) 6 1.3.2 7-Segment display 6

1.4 VHDL basics 6 2 Lab 1 – Design entry using Altera Quartus-II 7

2.1 Prelab 7 2.2 VHDL design entry using Altera Quartus-II 7

2.2.1 Pin assignment 7 2.2.2 Adding VHDL codes 8

2.2.2.1 Understanding VHDL structure 8 2.2.2.2 Understanding the VHDL code 8

2.2.3 Compiling the design for the FPGA 9 2.2.4 Simulation 9 2.2.5 Timing analysis 11 2.2.6 Programming the FPGA 12 2.2.7 Test the design on DE2 board 12

2.3 Design your own circuit – Car-Controller 12 2.4 Postlab 13

3 Lab 2 – Combinational circuits; Arithmetic Logic Unit - VHDL Design 14 3.1 Prelab 14 3.2 Lab requirement – ALU VHDL design 14 3.3 Postlab 16

4 Lab 3 – Combinational circuits; Elevator Controller – Schematic design 17 4.1 Prelab 17 4.2 Schematic design entry using Altera Quartus-II 17 4.3 Lab requirement – EC schematic design 18 4.4 Postlab 19

5 Lab 4 – Sequential circuits; Traffic Light Controller – VHDL design 20 5.1 Prelab 21 5.2 Lab requirement – Part A: A Simple Sequencer 21 5.3 Postlab – Part A only 23 5.4 Lab requirement – Part B: TLC VHDL design 23 5.5 Postlab 25

6 Appendix I – DE2 pin assignment file 26


3

1 Introduction

TheLabExperimentsaredoneingroupsoftwo.Findalabpartnerassoonaspossible.Eachlaboratoryexperimenthasseveralparts:

1. Aprelab thatmust be done before coming to the lab. Thiswill includematerial to read, and acircuittodesign.

2. A three‐hour laboratory session duringwhich help is available, progress is demonstrated, anddebuggingisdone.

3. Afinalreport,dueis4:30pm,onedayafteryourdemo,regardingtheguidelinesinthelabmanual.To minimize the VHDL and simulation print‐outs use 2‐up, double sided, and landscapeorientation.Latelabreportswilllosemark10%perday.

4. Absolutely no food or drink in the laboratories. Do not leave the doors orwindows open. Theroomwillbeclosedafterhoursiftherulescannotbefollowed.

5. Youmustmakeareasonableattemptatthelabsinordertopassthecourse.FailuretodosowillresultinagradeofINComplete.

EachworkstationintheECE124labisequippedwith:

1. Altera DE2 Board housing a Cyclone II Field Programmable Gate Array (FPGA) chip and amultitudeofperipheralcomponents

2. AlteraQuartus‐IIFPGADesignSoftware

Inthissectionyouaregoingtobebrieflyintroducedtheon‐boardcomponents.

Figure1 TheDE2board


4

Figure2 FPGAblockdiagramofDE2board

1.1 Field Programmable Gate Arrays (FPGAs)

A FPGA is a Field Programmable Gate Array; basically an array of generic gates to perform any logicfunction.ManyFPGAssimplyusesmallblocksofmemory,calledCLBs(CombinationalLogicBlocks), tolook up the answer to equations of 4 or 5 variables. In the past, AND and OR gates would beinterconnectedtosolveequations;butthishasbeenreplacedwithCLB'sastheyaremoreflexibleandcanbeusedasmemoryblocks.

As not all equations have as little as 4 variables; typical designs will be spread over several CLBs;requiringsignalstoberoutedbetweentheCLBs.Justhowmuchcircuitrythereis,andhowfastitwillrun,in a particular FPGA, depends upon the speed of CLBs, the amount of resources for routing signalsbetweenCLBs,andhowwelladesigncanbe"laidout"oroptimized.


5

NewerFPGAsare tailored forspecificcircuits.TheCyclone IIFPGA,which is inour labs,hashardwaremultipliersandadders,whichrunat250MHz,allowingultra‐fastdigitalsignalprocessingcircuitstobebuilt.

Configurable interconnects are provided between the chip resources (CLBs, hardwaremultipliers andmemoryblocks for theCyclone II FPGA).The logic, circuitry, and interconnects in the architecture areconfiguredbyuploadingaprogrammingfiletotheFPGAchip.ThispropertymakestheFPGAchipveryflexiblesinceitisabletorealizedifferentdigitalcircuitsbyuploadingadifferentprogrammingfile.FPGAsare different that microprocessors or microcontrollers because the designer is able to change thehardwarerealizedbythechipbyprogrammingit.SincehardwareisalwaysfasterthansoftwareFPGAsallowhardwaretobebuiltwithnearlythespeedofsoftwaredevelopment.

1.2 Altera Quartus-II FPGA design software

QuartusisafullFPGAdesignsoftwaresuite.ItaidsthedesignerthroughthedifferentstagesofdescribingthehardwaredesignandtargetingitforacertainAlteraFPGAchip.Thedesignprocessproceedsthroughthefollowingstages:

DesignEntry:allowsthedesignertoenterahardwaredesignspecificationusing:o HardwareDescriptionLanguage:suchasVHDLorVerilog(weuseVHDL)o Schematic Entry: by connecting blocks of ranging complexity. It can be used to

interconnectsimplecomponentssuchassimplelogicgates,ortointerconnectpreviouslycreatedhardwaremodules

DesignCompilation:Oncethedesignhasbeenspecifiedandenteredintothetool,thedesignermustperformcompilationwhichwilltakethedesignthroughvarioussteps:

o AnalysisandSynthesis:AHDLorschematicfileisanalyzedandthehardwareisbrokendownandmapped to thedevice resources (CLBs, flip flops,memory elements, .. etc) sothatdesignlogicisimplementedviatheavailableresourcesonthetargetchip

o PlaceandRoute: actualplacementofdesignon certaindevice resourcesandrouting itthroughtheprogrammableinterconnectiontakeplaceinthisstep

o Assembly:aprogrammingfileisproducedsothatitcanbeuploadedtotheFPGAchip CircuitSimulation:Inorderforadesignertoverifythefunctionalityoftheirdesignsimulationis

required. The simulation step ensures that the circuit operates in the expected manner. Asimulator is fed with the design description files and waveforms describing the input valuesagainst time to the circuit under test. The simulator then produces the logic values that willappearonthecircuitoutputsaswaveformsalsoagainsttime.

TimingAnalysis: It gives an accurate indication of how fast the circuit runs, and if speed andtimingconstraintscanbemet.Electroniccircuitsalwayshavespeedrequirementstobemetandbeing able to ballparkhow fast a designworkswithout having to build andmeasure it greatlyspeedsupdesigntime.

ProgrammingtheFPGA:InthissteptheprogrammingfileisuploadedtotheFPGAchiptorealizethe design. The circuit can be physically tested afterwards by applying inputs and observingoutputs

1.3 DE2 FPGA board peripherals

The DE2 board is equipped with peripherals that can be used to create various applications such asSDRAM,SRAMandflashmemorychips,SDcardsocket,audioCODEC,VGAdigitaltooutputconvertorand


6

many others. For the purposes of the labswe are only using switches andpushbuttons for supplyinginputsandthefollowingperipheralsfordisplayingoutputs:

1.3.1 Light Emitting Diodes (LEDs)

LEDs are electronic components which can emit light withmuch greater efficiency than incandescentlamps.TheAlteraDE2boardhasmanyoutputsbutyouwillonlyusetheLEDs.

1.3.2 7-Segment display

A7‐segmentdecoder takesan input, typicallya4bitbinarynumber, andcorrectlydrivesa7‐segmentLEDdisplaysothatapersoncanseeanumberorletterasopposedtotryingtointerprettheoriginal4bitbinarynumber.

The 7‐segment display is so called because it is 7 bar shaped LEDs arranged in such a way that thenumbers0to9,andlettersAtoF,canbedisplayed.Sevensegmentsistheminimumnumberwhichcanuniquelydisplaynumbersandthatiswhytheyareusedformanycalculatororelectronicdisplays.

1.4 VHDL basics

VHDLisalanguageusedbyahardwaredesignertodescribethebehaviorofhardware.Asynthesistoolthenconvertsthisintoacircuittobebuilt.VHDLishelpfulforthedesignofdigitalcircuits,andisoneoftwomainlanguagesinuse;theotherbeingVerilog.AnarrayofotherlanguagesisbecomingpopularsuchasSystemCandrecentlySystemVerilog.BasiccircuitconstructssuchasAND,OR,NOT(gates)andlook‐up tables (SELECTstatement), countersand flip‐flopsare straight forward.TheVHDL language isverycomplexandwasoriginallydesignedforthesimulationofmostanything.Weencourageyoutousetheprovidedexamplesandstickwithwhatyouknowwillwork.ThemostbasicruleofVHDListhat ifyoucan't understand how the CAD tool will create the circuit within the FPGA; then it's unlikely that thedesignwilldowhatyouexpect.Becauseofthis, it isvitalthatyouhaveanunderstandingofbasic logiccircuitryanddesign.


7

2 Lab 1 – Design entry using Altera Quartus-II

ThegoalofthislabsessionistogainexperiencewiththeAlteraQuartusFPGAdesignsoftwarewithbothcircuitentryandsimulationandthenmodifyingtheprovidedcircuits.Thestudentwillbeprogrammingthe FPGA to verify that the circuitworks in hardware. No prior experiencewith digital design, AlteraQuartusorFPGAsisnecessary;althoughexperiencewithbasicdigitallogicwillenableonetounderstandthecircuit.

2.1 Prelab

No prelab work is necessary for the first part, the introduction, of this lab experiment. A simplemultiplexer circuit has been provided. After the self‐guided introduction the student will modify thiscircuit toperformadifferent task.The lab startswith abrief introduction to the laboratory room, theequipmentandthelabexperiments.Lab1iscomposedoffourpartsinwhichyouwill:

1. DesignentryofaVHDLcodeforasmalldigitalcircuit2. Simulatethecircuitstocheckthattheyoperatecorrectly3. ProgramtheFPGAandcheckthatthehardwareimplementationfunctionscorrectly4. Modifytheprovidedcircuittoprovidenewfunctionality,simulate&testitandsubmitareport

2.2 VHDL design entry using Altera Quartus-II

TostartthesoftwareclickStartthenselecttheprogramgroupAltera.ThenclickontheAlteraQuartusIIicon.TocreateaprojectselectFile‐>NewProjectWizardandthenenterasmuchinformationasyouwish.Createanewproject calledLab1. Inprojectwizardpage1youmust set aworkingdirectory foryour project. You should use “N:\ECE124\Lab1" or something similar; creating a unique, logical,directorynamewhichdescribesyourproject.Nextyoumustselectthenameofyourprojectthatmustbethesamenameasyourtopleveldesignentity(Lab1).ThenclickonNextandsayyesforthecreationofthedirectory.Page2thenallowsyoutoaddVHDLfilestoyourproject.SkipthisnowbyclickingonNext.Inpage3youmustselecttheAlteraFPGAfamilyCycloneII,andEP2C35F672C6fromavailabledevices.In particular the DE2 board uses a FBGA package with 672 pins, and speed grade 6. Once you'veselectedthecorrectpartyoushouldselectFinishinordertoskipthenextpage.

2.2.1 Pin assignment

Pinassignmentistheprocesswhichmapstheinputandoutputsignalsofyourdesigntophysicalpinsofthe FPGA chip available on the hardware board. As mentioned earlier the chip has a vast amount ofresourcesandthedesigncanbebuiltanywhereonthechipintheplaceandroutestep.Theinputsandoutputs can be exported to any pins on the chip. Pin assignments act as constraints to specifywhereexactlyyourpinsaregoingtobeexportedandarenecessaryastheperipheralsarealreadypre‐wired.Touse different DE2 board peripherals such as LEDs, buttons and switches we must go through pinassignment.SinceeachperipheralisconnectedphysicallytoacertainpinintheFPGAontheboard,weshouldmakesurethetoolexportsourinputsandoutputstotheperipheralswetargetforuse.Pinnamesarecomplextousesothepinsassignmentfilegivesalogicalnametoeachpintobeusedthroughoutthedesignandmapsittoacertainphysicalpinname.Youcanopenthesuppliedfiletoseehowthismappingisdone.


8

Download the supplied pin assignment file (DE2_pins.csv) from course web site and save it in yourprojectdirectory.ClickonAssignments‐>ImportAssignments,thenclickonthe[...]toselectthesavedpinassignmentfile(DE2_pins.csv),whichyou'vesavedtoyourworkingdirectoryandclickOK.

For the Altera DE2 FPGA board, unused pins should all be left as inputs tri‐stated. Unfortunately thedefault is to ground unused pins (this reduces noise and is what one should do for a product to beshipped). To change this setting click onAssignments‐>Settings then select theDevice category andclickonDevice&PinOptionsthenselecttheUnusedPinstabandchangethevaluetoInputtri‐stated.ClickOKtwicetoclosethewindows.

2.2.2 Adding VHDL codes

YoumayuseaVHDLorSchematic(BlockDiagram)designinyourproject.Forthispartoflab,downloadthe“lab1.vhd”filefromwebsiteandaddthisfiletoyourprojectdirectory.Toaddittotheproject,clickonProject‐>Add/RemoveFilesinProject,findandselecttheVHDLfileonyourlocaldirectoryandclickAddandtheOK.

2.2.2.1 Understanding VHDL structure

VHDLiscaseinsensitive.Forthisreasonmanycodersusealllowercase.VHDLlanguageusestwomainstructurestodescribeadesignunit(hardwareblock):

1. Entity:itdeclaresthedesignunitnameandtheports(whichareinputsandoutputsoftheentityordesignunit)associatedwithit.Eachportname,type(inputoroutput)andwidth(numberofbits)isdeclaredintheentity.

2. Architecture: the architecture specifies the actual functionality of the entity. Notice that theentityhasnoinformationabouthowthehardwareblockusestheinputstoproducetheoutputs‐thatistheroleofthearchitectureassociatedwiththeentity.

Therearetwowaystodescribethefunctionalityofacertainblock:

1. Behavioral:wheretherelationbetweeninputandoutputisdeclaredusinglogicalequations.2. Structural:whereyoucanusepreviouslycreatedentitiesinyourdesignunitascomponents.For

exampleifyoubuiltanadderunityoucanuseit,asacomponent,indesigningamicroprocessor.

2.2.2.2 Understanding the VHDL code

UnderstandingthegivenVHDLcodewillhelpyouintheupcoming labs.Thegivencodeconsistsofonedesignunit (single entity and architecture). “Lab1” is the top level entity for thedesign. It has2 inputports (key and sw) and 2 output ports (ledr and ledg). Notice that the names of the ports are caseinsensitiveand identical to thoseones in thepinsassignment filesandaresimilar to thenamesontheDE2board.Weareusingthose logicalnames inordertomapour inputstothekeys,switches,redandgreen LEDs respectively. Analyze the code and try to familiarize yourself with VHDL, it is fullycommented.Ifyoustillcannotfigureoutacertainlineaskforhelp.


9

2.2.3 Compiling the design for the FPGA

To compile the design and make a programming file for the FPGA click on Processing‐>StartCompilation or use “Ctrl+L” or the arrow button on the toolbar. You will see around 100messages;mostlydue topinswhichhavebeendefinedbutarenotbeingused.Near thebottomof theQuartus IIwindow you will see several tabs. You can click onWarning or CriticalWarning or Error or Infomessages to see the details. You should always check the Error and CriticalWarning messages andresolve them. Prudent users should also check theWarning messages if the design isn't working asexpected. If thereareanyerror(s),compilationwillbestoppedandonecanreadtheerrormessage(s),divinetheproblemandfixit.ExpecttoseemanywarningsbecauseofthepinassignmentfileasitdefinesalmosteverypinontheFPGAandyouwillbewarned,atleastonce,foreachonethatisnotconnected.

The following steps are doneby the software to convert the schematic circuit and/orHDL (e.g. VHDL,Verilog)circuitintoafilewhichisusedtoprogramtheFPGA:

Analysis&Synthesis:This stage converts thedesign intopartswhichare availablewithin theselected FPGA. Partswhich are available are typically flip flops,memory blocks, look‐up tablesandadders;andsometimesmultipliersandothercomplexsupportparts.

Fitter:ThisplacesthepartswithinanFPGA,connectsthemtogetherandtotheinputandoutputpins,andoptimizesthelayoutfortheusergoals(typicallyspeed).Adesignmayrequirehundreds,or thousands of CLBs (Combinational Logic Elements), LEs (Logic Elements) or LUTs (Look‐UpTables).

Assembler:ConvertsthefitteddesignintoafilewhichcanbeusedtoprogramtheFPGA.

2.2.4 Simulation

Altera Quartus‐II comes with a simple simulator which is limited by its graphical nature. The inputstimulusisappliedaswaveforms,andthenthesimulationisrunandtheoutputanalyzed.Thesimulationisnotinteractive,andsocanbequiteslowfordebugging.Italsodoesnotallowonetoviewanythingbutinputandoutputpinsandinternalregisters.

Tosimulateyourcircuit,avectorwaveformFilemustbecreated.Thisspecifiestheinputstothecircuit.To do this click on File‐>New then select the Verification/Debugging Files tab and select VectorWaveformFile.ThatwillopenafiletypicallycalledWaveform1.wmf.Intheleftwindowofthatfile,rightclickandselectInsertNodeorBusandthenclickontheNodeFinderbutton.InthefiltertabscrollupandselectPins:InputandthenclicktheListbuttontoshowallinputpins.Clickonthe">"arrowtoaddtheseinputpinssw(0),sw(1),sw(3),andkey(0)totheSelectedNodescolumn.YoucouldrepeatthisforPins:Output (ledg[0], ledg[1], ledr[0]) but this is not necessary as the simulator adds all outputs bydefault,thenclickOK.Forsimulationyouneedtosetaseriesof‘0’sor‘1’stoinputs(inputtestpattern).To assign periodic values, right click on a signal and select Value‐>Clock and then set the followingperiod for each signal (Table 1). Itwill switch each signal between ‘0’ and ‘1’ at a certain interval. Bychoosingintervalsthatincreasebyafactorinpoweroftwo(2 _ _ ),allpossiblecombinationsofinputswillbegenerated(Figure3).

Table1 Inputsignalsclockassignments

Inputs sw[0] sw[1] sw[3] key[0]Period 50ns 100ns 200ns 400ns


10

Don’tforgettohit“Ctrl+W”orrightclickinthewaveformwindowandselectZoom‐>FitinWindow.Bytheseassignments,allpossiblecombinationstotheinputswillbegenerated(anexhaustivetest),whichisonlysuitableforautomatedtestingorwherethereareafewcombinationstovisuallycheck.The“OR”and“AND” logic gates are easy to verify. One can force inputs to values other than a periodic wave. Forinstance,theValue‐>CountValueletsyougothroughallpossibleinputs‐asdoestherandommethod‐butforamorecomplexcircuitonewouldtestspecificcombinationsofinputs,notall.Whenyouaredonecreatingyourvectorwaveforminputs,youshouldsavetheresultingfileintoyourprojectdirectory.

Figure3 ExhaustivetestinputgenerationforfunctionF(X0,X1,X2,X3)=~X0&~X1&~X2&X3

Therearetwotypesofsimulation:

Functional: This is a verification of the basic functionality of the circuit with no timinginformation(i.e.gatedelays)included.

Timing: Timing simulationuses information about the circuit design, andhow the circuit is fitintoanFPGA,toestimateaccuratetimedelaysforsignals.Thissimulationisslower;butitisalsonecessarytodetermineifadesigncanmeetthespeedrequirements.

Now,youcanrunthesimulatorbyclickingonProcessing‐>SimulatorTool.SettheEndsimulationatvalueto1us(default).ThenSelectTimingasSimulationmode.FortheSimulationInputfieldselectyoursimulationfilejustcreated.ThenclickonStart.WaituntilitfinishesandthenclicktheReportbuttontoseethesimulatoroutput.Hit“Ctrl‐W”,orrightclickandchooseZoom‐>FitinWindowtoviewtheentiresimulation.

Rememberfrom“lab1.vhd”code(line45)thatforexample:“ledg(0)=sw(0)|sw(1)”.


11

Figure4 Timing‐modesimulationreportforLab1.vhddesign

Fortimingsimulation,youmaynoticethattherearesomeverynarrowspikes.Theseareglitchesduetothe circuit, or theway that simulation isdoneand canbegenerally ignored for this course.You'll alsonoticethatthereisanapproximately10nsdelaybetweentheinputschangingandtheoutputschanging.UnderView, or via themagnifying glass icons, youwill find zoom controls. Zoomout to show the fullsimulation.

Sometimes,afunctionalsimulationisalsorequiredineachlab.YoumustSelectFunctionalasSimulationmodeandthenclickonGenerateFunctionalSimulationNetlisttabtogeneratethenecessaryfiles.Fora functionalsimulation,youwillnotseeany timedelay.Here isasampleresultofa timingsimulation,verifyitsfunctionalitymatcheswiththeVHDLcode.

2.2.5 Timing analysis

Timing analysis can only be run after a design is successfully implemented and it gives an accurateindicationofhowfastthecircuitruns,andifspeedandtimingconstraintscanbemet.Electroniccircuitsalwayshavespeedrequirementstobemetandbeingabletoballparkhowfastadesignworkswithouthavingtobuildandmeasureitgreatlyspeedsupdesigntime.Toruntheanalyzer,clickonProcessing‐>ClassicTimingAnalyzerToolandclicktheStartbutton.Clickonthetpdtabandnotethattheslowestsignalisatthetopofthelist.Thisisthetimedelayfrom"P2P"(PintoPin).Youlikelyhaveavaluearound11ns.Othertabsprovideyoutimedelaysformorecomplexcircuitswithflip‐flops.

Bydefault,allpathsinthecircuitgetanalyzedandlisted.Therearetwocategoriestoconsider:

tpd: This is the time required for a signal to go from an input pin to an output pin throughcombinationallogic


12

tco:Forregistersandflip‐flops,thisisthetimerequiredforanoutputtobecomevalidaftertheaclocksignal transition.AlsopayattentiontothetSU table.Thattable lists the lengthof timesforwhich each datamust be present (setup) before the clock transition. So the worst case is theslowestsumfortCOplusanyassociatesetuptimes.Notethatwe'veneglectedtheholdtimeofthedataforclockeddataandthiscanbeimportantinreal‐worlddesigns.

Toquicklygettiminginformation,clickontheReportbuttonandnotethefirstrowinformation("Worst‐case tpd").Fromthisanalysisonecansee that thecircuitwouldworkatamaximumspeedof>90MHz;whichisn'tveryfastcomparedtothe3+GHzspeedofmoderncomputers.However,muchmorecomplexcircuits would also work at the same speed, and this FPGA has other resources such as adders andmultiplierswhichworkat250MHzallowingforreal‐timeHDTVimagemanipulation.

2.2.6 Programming the FPGA

Make sure that the power to the FPGA board is on (the red button in the upper right corner). TheprogrammertoolcanbefoundunderTools‐>Programmer.Youwillneedtomakesurethatthecorrectprogrammerisselected.ClickonHardwareSetupandselectUSB‐Blaster,ifnecessary.Ensurethatthe“Currentlyselectedhardware”saysUSB‐Blaster[USB‐?].Next,ensurethatforyourprojectthe“Lab1.sof”file in the listhasacheckmark in theboxunder“Program/Configure”,andthen justclickontheStartbuttoninordertoprogramtheFPGA.

2.2.7 Test the design on DE2 board

NowthedesigncanbetestedonFPGAboard.Verifythefunctionalityregardingtothe“lab1.vhd”file:

Turn on/off SW0 and SW1 inputs, to verify the functions behind outputs LEDG0 and LEDG1(checkwithVHDLcodeinlab1.vhd)

Turnon/offSW1,SW3andKEY0inputstoverifythefunctionbehindoutputLEDR0(checkwithVHDLcodeinlab1.vhd)

2.3 Design your own circuit – Car-Controller

Foryourdemo,modifythe“lab1.vhd”codetomakeitsfunctionasanautomotivecontroller.Theinputsandoutputsaredefinedinbelowtable.

Table2 Car‐ControlcircuitIOdefinition

SignalType SignalName AssignedPort Description

Inputs

Gas KEY[0]Clutch KEY[1]Brake KEY[2]Override SW[1] Masterswitchtoshutdownthecar

OutputsGasControl LEDG[0] WhenON (logic‘1’), accelerationisgiventothemotorBrakeControl LEDR[0] WhenON (logic‘1’), thebrakesareengaged


13

Considerthefollowingguidelinesinyourdesign.Atypicalblockdiagramforyourdesignisalsoshown.

Thepushbuttons(KEY[3:0])ontheDE2boardareinverted.Theyare ‘1’whenNOTpressedandbecome‘0’whenpressed.

Note thatsomekeys(KEY[3:0])orswitches(SW[17:0])donotworkproperlysometimes(havephysicaldamage).Replacethemwithotherones.

Make sure that the inputs and outputs you need are in the VHDL code ENTITY declaration.Removeextraportsandsignalsfromthedesign.

Addabrakesafetysothatthe“Brake”beingON,turnsoffthe“GasControl”. Addaclutchsafetysothatthe“Clutch”beingON,turnsoffthe“GasControl”. Addanenginesafetysothatthe“Override”beingON,turnsoffthe“GasControl”andturnsonthe

“BrakeControl”.

Figure5 Car‐Controlcircuitblockdiagram

2.4 Postlab

Download, print and fill out the “Lab1SubmissionForm.pdf” from and demonstrate your Car‐Controldesignonscheduleddate.Thenhandinthereport,onedayafterdemosession.ThesubmittedreportforCar‐Controldesignmustinclude:

1. Completed“Lab1SubmissionForm”asthereportfrontpage.Don’tforgettofilloutthe“totallogicelements”intheform.

2. Implementation procedure, design decisions, encountered problems or bugs with solution tothemanddebuggingtechniques(2pagesmax).Don’tforgettoincludetheRTLviewofyourcircuit(Tools‐>NetlistViewers‐>RTLViewer).

3. FullycommentedVHDLcodeprintout(2‐up,landscapeanddoublesided).Usemeaningfulnameforyoursignals.

4. Timingsimulationwaveformforthecircuitshowingthatthecircuitworksinallcases(exhaustivetest).


14

3 Lab 2 – Combinational circuits; Arithmetic Logic Unit - VHDL Design

ThegoalistobuildasimpleVHDLcircuittochoosebetweenvariouscalculationsandlogicaloperations.This isbasically a calculatorwhich canperformmultipleoperationswithnomemory, i.e. the circuit iscompletelycombinational.

3.1 Prelab

Firstdownloadthe“lab2.vhd”codefromwebsiteandopenitacontextsensitiveeditororQuartusII.Atthetopofthefile,anewentityforaseven‐segmentisdefined.TrytounderstanditsIOmapping(ENTITY)andfunction(ARCHITECTURE).Inthislab,wewillinstantiatethisentitymultipletimestodisplaybinaryvaluesinhexadecimalformat.

3.2 Lab requirement – ALU VHDL design

Createanewproject forLab2andaddthe“lab2.vhd” file to theproject.Aftercompiling,programyourFPGA to watch its functionality. For every VHDL design entry, you need to follow all instructions insection2.2.TestthecircuitwithdifferentcombinationsofinputsignalvaluesandcheckitsoutputwiththeVHDLcode.

Now,foryourdemo,modifythecodein“lab2.vhd”tomakeitsfunctionasanALU.Theinputsandoutputsaredefined inTable3.Youmayuseothermeaningful signalnames inyourdesign.Again, youneed tofollowallinstructionsinsection2.2.

Table3 ALUdesignIOdefinition

SignalType SignalName AssignedPort Comment

InputsOperand1 SW[7..0] 8‐bitinputtobedisplayedonHEX5andHEX4Operand2 SW[15..8] 8‐bitinputtobedisplayedonHEX7andHEX6Operator SW[17..16] 2‐bitinputtobedisplayedonLEDR[17..16]

Outputs OperationResult HEX2,HEX1,HEX0 9‐bitoutput result tobedisplayedonLEDR[8..0] too

Yourdesignissupposedtoimplementasimplecalculatorwithfourpre‐definedoperations.

Table4 ALUoperations

SW[17..16] Operator Description00 AND LogicalAND of8‐bitinputs01 OR LogicalOR of8‐bitinputs10 XOR LogicalXOR of8‐bitinputs11 ADD BinaryADD of8‐bitinputs

Considerthefollowingguidelinesinyourdesign.Atypicalblockdiagramforyourdesignisalsoshown.

SW[7..0] and SW[15..8] represent the inputs from most significant bit (MSB) down to leastsignificant bits (LSB) for the first and second operands. Here, SW[7] and SW[15] are mostsignificantbits.


15

TheresultisdisplayedonHEX2,HEX1andHEX0.HEX2showsthemostsignificanthexdigitoftheresult, while HEX0 shows the least significant hex digit of the result. This makes your resultreadableontheboard.Noticethatweareusing3hexdigitstodisplaytheresult,thoughwehave8‐inputoperands.That’sbecauseadditionoftwo8‐bitnumberscancausecarry(9thbit)tooccur.ThisistheonlycaseinwhichHEX2willdisplay1insteadofbeingblank.ToblankHEX2usetheblankinginputtoblankorturnitoff.

Signals are intermediate values that must be declared using “signal” statement in the VHDLarchitecturebeforethe“begin”statement.

Simulationforthislabhassomeextracomplications.Donotaddthevectorfortheinputs(e.g.KEYorSW)butaddindividualwires(e.g.KEY[0)andwhentheyareadded, intheVectorWaveformFile one can group them together.Onebundle of 8wires canbe labeled as "A". To groupwiretogether,selectthemandthenpressrightclickandchoose"Grouping‐>Group".

Toassignvaluestoinputoperandsandoperators,firstgroupthemwithmeaningfulsignalnamesandthenuse“Value‐>ArbitraryValue",“Value‐>RandomValues”or“Value‐>CountValue”.

Insteadoflookingattheraw7‐segmentoutputsinthesimulatorreport(theyarenotmeaningful),itmakesmore sense to look at the LEDR[8..0] value (group them together) to have faster andmoreintuitivetesting.RemembertodisplaytheoperationresultonLEDR[8..0].

AWHENstatementcanbeusedinsteadofanIFstatementtoimplementamultiplexeraswehaveinsampleVHDLfile“lab2.vhd”.Thismultiplexershouldbetakenintoconsideration.Asmentionedearlier, HEX2 only displays the carry out value in ADD operation. This can be achieved byconcatenationofAandBtoastringof4zerosandthenperformingaddition.Thiswillpreservecarryandshouldproducea12bit result.This result canbeused todrive the3 sevensegmentdecoders.Thisistheheartoftheprojectandwilltake5linesofVHDLcode.

Notethatiftheresultisdeclaredasa12‐bitsignal,alloperationsmustproduce12bitresults.Soconcatenationisnotonlyrequiredonlyforadditionbutalsoforallotheroperationstoo.

Themostdifficultpartwillbetheaddoperationwhiletheresulthas9bitsandforbinaryadditioninVHDLsignalsmustbedeclared inunsigned type.Weneedtorecast thesignals tounsignedtype (which are originally in logical type std_logic_vector) and then recast again tostd_logic_vectortype.Youmayusestatementlikethistorecastsignals:

R<=std_logic_vector(unsigned(A)+unsigned(B))

In total, about15 lines of VHDL code are required tobewritten. If yourdesign is takingmuch

morethanthisSTOP,andtalktothelabstaff.

Figure6 AtypicalblockdiagramforALUdesign


16

3.3 Postlab

Download, print and fill out the “Lab2SubmissionForm.pdf” from and demonstrate your design onscheduleddate.Thenhandinthereport,onedayafterdemosession.Thesubmittedreportmustinclude:

1. Completed“Lab2SubmissionForm”asthereportfrontpage.Don’tforgettofilloutthe“totallogicelements”andtheWorstCaseSpeed(ns)tpdintheform.

2. Implementation procedure, design decisions, encountered problems or bugs with solution tothem,debuggingtechniquesandRTLviewofyourcircuit(2pagesmax).

3. FullycommentedVHDLcodeprintout(2‐up,landscapeanddoublesided).4. Functional simulation waveform with coverage for critical cases. Mark your simulation

waveformsexplaining severaldifferent scenarios foreachoperation.Youmustprove thatwhatyouhavedesignedisworking.Forinstance,testingwiththeinputssetto0doesnotallowonetodistinguishoneoperationfromanotherorifanyoperationinparticularisfullyworking.Oftenonetestscriticalcases‐thelimitswherethingsmaybreak(i.e.overflow).Donotprintwaveformsofallpossiblecases‐givesamplesforcriticalcasesofeachoperationandexplainhowyoucheckedfor proper operation. The goal is to have a simulation to prove that the circuitworks;withoutdoingafullexhaustivetestofallpossibleinputs.Itshouldprovethatalloperationsworkcorrectlyforenoughnumberstogiveconfidencethatthecircuitisfullyfunctional.

Figure7 Samplefunctionalsimulationoutput


17

4 Lab 3 – Combinational circuits; Elevator Controller – Schematic design

ThegoalofthislabsessionistodesigntwosimplecircuitsusingtruthtablesandK‐Maps.TranslatingawrittencircuitdescriptionintoaTruthTableisthebasisofthiscircuitdesign.OptimizingthedesignwithK‐mapsallowsonetomakethedesignsmallerandfaster.Youaretodesignandimplementacircuit tocontrolanelevator.Thecircuithasfourinputstodefinecurrentandrequestedfloorsandtwooutputstoenablethemotorandshowtheup/downdirection.

4.1 Prelab

Toprepareforthislabthestudentshouldreducethedesigndescriptionstotruthtables.Thetruthtablesshouldbe thenused tobuildK‐Maps. Extract logical expressions from theK‐Maps and realize the twocircuitsrequiredasgates.

4.2 Schematic design entry using Altera Quartus-II

In this lab,we firstcreateasimpleprojectusing theschematiceditorand thenmodify it to implementElevatorController.Tostart,createaprojectandnameitLab3,repeatthesamestepstoimportthepinsassignmentfileandtosetunusedpinstoinputtri‐stateinsection2.2.1.Proceedbyaddingtheschematicusing the schematic editor. Click on File‐>New and selectDesign Files‐>BlockDiagram/SchematicFile.Primitiveparts(AND,OR,othergates)canbeenteredviatheSymbolToolwhichlookslikeanANDgate. Click on it and then expand theLibraries item to revealprimitives. Expand that to reveal logicprimitivessuchasgates.Youwillalsoneedtouse thepinandotherprimitivessuchas input,output,gnd (groundor logic ‘0’)aswellasvcc (highor logic ‘1’).Thestorageprimitives include flip‐flops.TodrawwiresyouwillneedtousetheOrthogonalNodeToolfromthetoolboxontheleft.Drawingwirescanbepainfulasyouwilldiscover.Drawwiresinpiecestomakethetaskeasier.Toconnectnetsorwirestotheoutsideworldyouwillalsoneedtousetheinputandoutputpinprimitives.Tonameyourpinsjustdoubleclickonthemandusethestandardnames(e.g.sw[0],ledg[0])whichisdefinedinyourpinoutfile,on theschematicabove(documented inAppendixA).DoNOTrightclickonawireornode,and in theProperties tab assign a name. That sometimes results in a circuitwhich does nothing. Now, draw theschematicshowninFigure8:

Figure8 Lab3.bdf‐Schematicdesignfile


18

CompilethisdesignanddownloadittotheFPGAfortesting.Ifyouhavetime,simulateitbysettingtheproper inputvaluesasclockperiodsforallpossiblescenarios(asdone inprevious labs).Remembertozoomandviewthewholesimulationwith“Ctrl+W”.

4.3 Lab requirement – EC schematic design

For your demo,modify the “lab3.bdf” file tomake it operate as an elevator controller. The inputs andoutputsaredefinedintheTable5.

Table5 Car‐ControlcircuitIOdefinition


InputsCurrentFloor SW[1..0]NextFloor SW[3..2]

OutputsEnable LEDG[0] WhenON(logic‘1’),themotoristurnedonDirection LEDR[0] Definemovingdirection(upwards:‘1’,downwards:’0’)

Designtwoversionsofthiscircuitoneusinganytypesof2‐inputlogicgatesandtheotheronly2‐inputNANDgates.NotethatK‐mapshelpyouminimizeacircuitwithanytypeofgates,butitwillnotdirectlyhelpyoutominimizeadesignwhereyouarerestrictedtouseaspecificgatetype(e.g.NAND,NOR).Therearetwowaystodesignthecircuit:

1. Using only 2‐inputNAND gates exclusively for the first design andminimizingwires and gatesusinganygatesavailablefortheseconddesign

2. Startingwithdesigningacircuitwith2‐inputlogicgatesofanytypesandthenreplacingthegateswith2‐inputNANDequivalents

Consideringoneofaboveapproaches,starttheschematiceditortobuildyourtwodesignsusingswitchesforthefourinputsandLEDsfortheoutputs.SimulateyourdesignsanduploadittotheFPGAforphysicaltesting.

Figure9 3‐floorelevator

Considerthefollowingguidelinesinyourdesign.


19

YoucanfindaschematicinverterintheQuartussoftwarecalledNOTunderprimitives‐>logic K‐Mapsshouldbeusedtominimizetheelevatorcircuitsize.Notethatthereisnoeasywaytodo

this, for theNANDonlydesign,without lotsofexperience.Note that therearemanythings thatcanbeoptimizedfor.OnemaychoosetodesignfortheminimumnumberofwiresORgates‐it'shard tominimizebothat thesametime.Wesuggest trying thisseveral timesand includeall inyourLabReport.

4.4 Postlab

Download, print and fill out the “Lab3SubmissionForm.pdf” form and demonstrate your design onscheduleddate.Thenhandinthereport,onedayafterdemosession.Thesubmittedreportmustinclude:Thesubmittedreportmustinclude:

1. Completed“Lab3SubmissionForm”as the frontpageofyourreport.Don’t forget to fillout the“numberofgates”and“numberofwires”intheformfordemonstratedcircuit.

2. Implementation procedure, design decisions, encountered problems or bugs with solution tothem,debuggingtechniquesandRTLviewofyourcircuit(2pagesmax).

3. Discussionofexpandabilityof thedesign if the4th floor isaddedandeffectof thatonreliability(youdon'tneedtoactuallyimplementthe4thfloorextralogic).Considerthenumberofwiresandgatesasbeingindicatorsofreliability.

4. How does the all NAND design compare to the other design? Howmany gates and wires arerequiredforeach?Note:ThislabusedtobebuiltandsoyoushouldcountALLgates‐ inverterstoo‐astheyallhadtobewiredup.Whichwouldbemorereliable?

5. Include the truth table for the elevator controller, K‐maps and how you deduced logicalexpressionsforthetwocircuits.

6. Schematicprintoutforthetwocircuits7. Simulationwaveforms for the two circuits showing that theywork in all cases (please circle 4

pointsand identifywhat the inputsrepresentandwhy theoutputsarecorrectaccording to therequirements).Demonstratethatyoucaninterpretthesimulationwaveforms.


20

5 Lab 4 – Sequential circuits; Traffic Light Controller – VHDL design

Thegoalofthislabistodesignatrafficlightcontrolsystemasasequentialcircuitwithclock.Thesystemcontrolstwotrafficlightsonanintersectionusingastatemachine.Firstyouwilllearntoimplementandtest,twoclockdividersusingmodulusandbinarycounters.

The standardway to implement a clock divider is to use a binary counter. Binary counters incrementtheir valuebyoneonevery rising/fallingedgeof its input clock signal. If you consider ann‐bitbinarycounter,younoticethatthefirstbitofthecounter(LSB)togglesintheperiodofhalf‐speedoftheoriginalclock.Ifyoulookatthesecondbityouwouldfindittogglingathalfspeedofthefirstbitwhichmeans1/4thespeedof theoriginalclock.ThusNthbit in thecounteroutput isaclock in frequencyof inputclockfrequencydivideby2N+1whereN is thebitpositionstarting frombit0.Thebinarycounter isnotveryaccurateifyouneedaclocksignalwithprecisefrequencybecausethedivisorisalwaysinpoweroftwo.Soforaccuratetimingorclockdivisionamoduluscountercanbeused.Amoduluscounterincrementsuptoacertainnumber(terminalcountvalue)andthenresetstoinitialvalue.Ittogglestheclocksignalattheterminalwhich isequal tohalf theperiodofyourdesiredoutputclock.Thusyouneed tocalculate theperiodofyourclocktodeterminetheterminalvalue.Figure10showsoutputsoftwo25‐bitbinaryandmoduluscountersgeneratedfroma50MHzinputclock.

Figure10 BinaryandModulusclockdividersby25‐bitcounters

InthislabyouneedtoimplementsequentiallogicinVHDL.Sequentiallogichas"memory"andtheoutputdependsontheinputsandwhatthecurrentstateor"memory"is.ThisrequiresaPROCESSstructureinyour architecture to implement flip‐flops and other memory elements. It starts with a tag (name)followedby a colon then thewordPROCESS. Betweenbrackets youmention all the signals that affectyourlogic(sensitivitylist)separatedbyacomma.Thesearethesignalsthatwilltriggerexecutionoftheprocessinsidethesimulator.Thus,anysignalutilizedintheprocesslogicshouldbeinthesensitivitylist.Missing signals from the sensitivity list cause simulation‐synthesis mismatch. The key statement toimplementflipflopsorsequentiallogic,istheIF(rising_edgeclock)THENstatement.

InVHDL,statemachinesarebuiltinsideaprocessblock.Acasestatementcanbeusedtodeterminethenextstatedependingon thecurrentstateandothersignals (inputsor timeevents).On theedgeof theclock the current state is assigned thevalueof thenext state (determinedby the case statement). It isworthmentioningthatsometimesyourdecisioncanbestayinginthesamestate.Tonameyourstatesyoumaydeclareanewtypeinyourarchitectureandthendeclaretwosignalsofthistypetokeepyourcurrentstateandnextstate.


21

5.1 Prelab

Inthislabexperiment,itisimportanttodesignandbuildyourcircuitincrementally.Don’tstartdesigningthewholecircuitatonce.Firstdownloadthe“lab4.vhd”filefromwebsiteandopenitacontextsensitiveeditororQuartusII.BrowsetheVHDLcodecarefullyandtrytounderstandallstatementsinthefile.Lookattheclockdividercircuitsandstudyhowtheywork,howtochangethefrequencyofthesystemclock,andhowitcouldbe furtherdividedby10.Trytoextract theembeddedstatemachine inthiscodeandunderstandsequentiallogicdesignstatementsinVHDL.

5.2 Lab requirement – Part A: A Simple Sequencer

CreateanewprojectforLab4andaddthe“lab4.vhd”filetotheproject.ForeveryVHDLdesignentry,youneedtofollowallinstructionsinsection2.2,i.e.,importpinassignmentfile,setunusedpinstotri‐state,compile,programthedevice,etc.TestthecircuitwithdifferentcombinationsofinputsignalvaluesandcheckitsfunctionwiththeVHDLcode.Donottrytosimulatethedesignatthismoment.

Now, for your demo,modify the “lab4.vhd” file tomake a sequencer to generate the followingpattern(Figure11)repeatedlyongreenandredLEDs.ThepatternstartswithaflashinglightonagreenLEDfortwosecondsfollowedbysolidpatternfor5secondsandthenthesamesequencewithdifferentdurationsonredLED.TheinputsandoutputsaredefinedinTable6.Youmayuseothermeaningfulsignalnamesinyourdesign.Again,youneedtofollowalltheinstructionsprovidedinsection2.2.

Figure11 Sequencertimingdiagram

Table 6 Sequencer circuit IO definition

SignalType SignalName AssignedPort DescriptionInput InputClock CLOCK_50 50MHzon‐boardclock

Outputs

GreenLED LEDG[8] GreenlightpatternRedLED LEDR[11] RedlightpatternClock1HzBin LEDG[2] 1HzoutputfrombinarycounterClock1HzMod LEDG[1] 1HzoutputfrommoduluscounterClock10HzMod LEDG[0] 10HzoutputfrommoduluscounterStateNumber HEX0 4‐bitinternalstatenumberStateCounter HEX2 4‐bitinternalstatecounter

Start your design with modulus 10Hz and 1Hz clock dividers. Use this 1Hz clock to drive your statemachine.Keepthebinary1Hzclockoutputforyourdemo.Figure12showsatypicalblockdiagramforyour design. You must be able to implement the sequencer FSM in four states. Display your internalsignals(statenumberandcounter)onSeven‐Segmentdisplaystodebugyourcircuit.


22

Figure12 Atypicalblockdiagramforasequencerdesign

TrytobuildtherequiredcomponentsonebyonetogeneratethetimingdiagraminFigure11:

1. Amodulusclockdividertocreatea10Hzclockfromtheboard's50MHzclockinput.2. Amodulusclockdividertocreatea1Hzclockfromthe10Hzclock.3. The 1Hz clock will drive a counter to determine the time of transitions between states. The

currentstatedetermineswhichLEDsareONorOFF.Yourstatescanbedefinedas:

GFLASH:thegreenLEDisflashingat10Hz,whileredLEDisOFF. GSOLID:thegreenLEDisON,whileredLEDisOFF. RFLASH:theredLEDisflashingat10Hz,whilegreenLEDisOFF. RSOLID:theredLEDisON,whilegreenLEDisOFF.

InordertosimulateyourdesignbeforeprogrammingtheFPGAdevice,youshouldchangetheterminalcountvalueforyourfirstmoduluscounterinclockchain(10Hz)toskipfromwaitingfor5,000,000clockcycles inyour simulations togenerateonecycleof10Hzclock from50MHz.Youcansetyour terminalcount to "0000000000000000000000001" and then find a proper clock period for CLOCK_50 to haveexactly10Hzand1Hzclocksinsimulationwaveforms(Figure13).

Another way of simulating your design is completely bypassing the clock divider and providing the50MHzclocktothestatemachine.Pleasenoticethatthisstrategyisonlytosimulateyourdesign.

Figure13 Clockgenerationscheme


23

5.3 Postlab – Part A only

Download, print and fill out the “Lab4SubmissionForm.pdf” form and demonstrate your design onscheduleddate.Keepyoursubmissionformfortheseconddemo(partB)andLab4report.ThereisnolabreportrequiredtosubmitseparatelyforpartA.SaveyourworkinaseparateprojectfilebeforeproceedingtoTLCdesigninpartB.

5.4 Lab requirement – Part B: TLC VHDL design

Afterbuilding the simple statemachineand testing that it is functioning according to thegiven timingdiagraminpartA,youarerequiredtoextendthedesignedsequencerinpartAtoimplementarealtrafficlightcontrollerintransportationsystemlikeFigure14.

EW Sen

sor

B 07

EW S

enso

r

Figure14 TrafficLightSystem

Thetrafficlightcontrollershouldhavetwomodesofoperation(SW[17]).

1. DayMode:inthismodethetrafficlightactsnormallyasasimplesequencer,designinpartAtotransitbetweengreen,amberandredlightsinrealtrafficlightsystems.Aswedon’thaveyellowororangeLEDsonourevaluationboard,wereplacethemwithaflashingredlightinourdesign.Youmaydesignitinthreestatesas:

Go:‐thegreenLEDisON.Firsttwosecondsisflashingat10Hzforturningleftcars. PrepareToStop:theredLEDisflashingat10Hztowarndriverstobepreparedtostop. Stop:‐theredLEDisON.

AsshowninFigure15,inthedaymode,thetrafficlightcontrollerswitchesbetweenabovestateswiththepredefineddurations(i.e.6seconds,2secondsand8secondsrespectively)continually.Notethatinthefirst2secondsof“Go”stateinthismode,thegreenLEDisflashing.


24

2. NightMode:inthenightmodethetrafficlightcontrollerhasadefaultside(SW[16])thattrafficlightisalwaysgreenforit.Whenthetimetoswitchlights(ambertored)reaches(attheendofamberlightperiod),ifnocarisdetectedonthenon‐defaultside,thesystemstartsanothergreen‐amber(onlysolidgreen)periodforthedefaultside,otherwiseitactslikedaymodewithgreen‐amber‐redperiods for both sides. For thismode,weuse car detection sensors output for non‐default side to decide for transition between states. These sensors can be implemented usingON/OFFswitches(SW[15:14])ontheboard.WhentheswitchisON,itindicatesthepresenceofacaronthatside.

Figure15 TrafficLightControllerTimingDiagram

Theinputsandoutputsfortheextendedtrafficlightlogicareshownbelow:

Table 7 TLC circuit IO definition


Inputs

InputClock CLOCK_50 50MHzon‐boardclockOperationMode SW[17] ‘0’:day,‘1’:nightDefaultSide SW[16] ‘0’:NS,‘1’:EWCarSensorNS SW[15] CardetectionsensoroutputforNSboundCarSensorEW SW[14] CardetectionsensoroutputforEWbound

Outputs

GreenLEDNS LEDG[8] Greenlightpatternfornorth/southboundsRedLEDNS LEDR[11] Redlightpatternfornorth/southboundsGreenLEDEW LEDG[7] Greenlightpatternforeast/westboundsRedLEDEW LEDR[0] Greenlightpatternforeast/westboundsClock1Hz LEDG[1] 1HzoutputfrommoduluscounterClock10Hz LEDG[0] 10HzoutputfrommoduluscounterStateNumber HEX0 4‐bitinternalstatenumberStateCounter HEX2 4‐bitinternalstatecounterWaitCounterNS HEX4 4‐bitinternalwaitcounterforNSboundsWaitCounterEW HEX6 4‐bitinternalwaitcounterforEWbounds


25

Consider the following guidelines in your design. A typical block diagram for your design is shown inFigure12.

IfyourPROCESShasnestedIFstatementsthentheresultinghardwarewillbeadisasterandhardtodebug!Each IF statementbuildsa2x1multiplexerandnesting IF statementsbuildsacircuitthatisdeepandslowattheleast.ForthiscircuityouneverneedmorethanasingleIFstatement.

Flip‐flops are logic elementswhich can store information. In the sample VHDL code you see aPROCESSstatement.Thisisusedtocreateflipflopssothatinformationcanbestoredinmemoryoracounter.TheD‐typeflip‐flopistheoneprimarilyusedinFPGAs.

ThePROCESSstatement,asgiven in thesampleVHDLcode,mustbeusedtobuildacounterorregister. Anything within the clock edge detection statement IF (rising_edge clock) THEN isautomaticallylatched.SoA<=BwillautomaticallylatchasignalA,whichissetequaltoBattherisingedgeoftheclock.

Besurethatthesensitivitylistincludesallsignalsusedbyaprocessorsimulationwillnotworkasexpected.

Trytominimizethenumberofstatestosixorlessstatesinyourdesign. Thewait‐counterincrements(countsupstarting0h)onlyifthelightisredforthecorresponding

side and car‐detection sensor is on for the same side otherwise itmust be reset to 0h on thedisplay.Thewait‐countersimplementationismandatoryfornightmodeonly.

Note that your Quartus simulation has to employ the 50MHz provided by the board (withoutusingtheclockdivisor).Yourboardtestanddemoshouldemploythedivided(slow)clocksothatyouareabletoseeyourdesignrunningontheboard.

Youdon’tneedtochangethestatesinpartAforpartB,onlythetransitionconditionsarerequiredtobechanged.

YoumayremovethebinaryclockdividerforpartB. Displayinternalstatenumberandtransitioncounter.Theyare ingreathelpfordebuggingyour

design.

5.5 Postlab

Use the previously used “Lab4SubmissionForm.pdf” form to demonstrate your design (part B) onscheduleddate.Thenhandinthereport,onedayafterPartBdemosession.Thesubmitted‐basedonpartB(TLC)design‐mustinclude:

1. Completed“Lab4SubmissionForm”as the frontpageofyourreport.Don’t forget to fillout the“Totallogicelements”and“WorstCaseSpeedParameters”intheformfordemonstratedcircuit.

2. Implementation procedure, design decisions, statemachine diagramwith transition conditions,encounteredproblemsorbugswith solution to them,debugging techniquesandRTLandStateview of your circuit (4 pages max). Use Tools‐>Netlist Viewers‐>StateMachine Viewer. Itrevealsallregistersandstateswithinacircuit.

3. FullycommentedVHDLcodeprintout(2‐up, landscapeanddoublesided)forPart‐AandPart‐B.DonotincludetheSevenSegmentdesign(ENTITY+ARCHITECTURE)inyourprintouts.

4. Functional SimulationWaveforms: Simulationmust be done to prove that the designworks asdesired.Youneedtoshowthatbothnightmodeanddaymodeworkasdesired.Alsoyouneedtoshowthedifferentscenariosthatcanhappeninnightmode(differentdefaultsidesanddifferentcarsensorvalues)usingnumerouswaveforms.Finallythewaitcountersfunctionalityshouldalsobe shown. Please try to cover and explain what happens in your waveforms at different timepointsandhowthisisrelatedtotherequirements.


26

6 Appendix I – DE2 pin assignment file

Name Location Name Location Name Location

SW[0] PIN_N25 HEX2[4] PIN_AB26 HEX7[5] PIN_P9

SW[1] PIN_N26 HEX2[5] PIN_AB25 HEX7[6] PIN_N9

SW[2] PIN_P25 HEX2[6] PIN_Y24 KEY[0] PIN_G26

SW[3] PIN_AE14 HEX3[0] PIN_Y23 KEY[1] PIN_N23

SW[4] PIN_AF14 HEX3[1] PIN_AA25 KEY[2] PIN_P23

SW[5] PIN_AD13 HEX3[2] PIN_AA26 KEY[3] PIN_W26

SW[6] PIN_AC13 HEX3[3] PIN_Y26 LEDR[0] PIN_AE23

SW[7] PIN_C13 HEX3[4] PIN_Y25 LEDR[1] PIN_AF23

SW[8] PIN_B13 HEX3[5] PIN_U22 LEDR[2] PIN_AB21

SW[9] PIN_A13 HEX3[6] PIN_W24 LEDR[3] PIN_AC22

SW[10] PIN_N1 HEX4[0] PIN_U9 LEDR[4] PIN_AD22

SW[11] PIN_P1 HEX4[1] PIN_U1 LEDR[5] PIN_AD23

SW[12] PIN_P2 HEX4[2] PIN_U2 LEDR[6] PIN_AD21

SW[13] PIN_T7 HEX4[3] PIN_T4 LEDR[7] PIN_AC21

SW[14] PIN_U3 HEX4[4] PIN_R7 LEDR[8] PIN_AA14

SW[15] PIN_U4 HEX4[5] PIN_R6 LEDR[9] PIN_Y13

SW[16] PIN_V1 HEX4[6] PIN_T3 LEDR[10] PIN_AA13

SW[17] PIN_V2 HEX5[0] PIN_T2 LEDR[11] PIN_AC14

HEX0[0] PIN_AF10 HEX5[1] PIN_P6 LEDR[12] PIN_AD15

HEX0[1] PIN_AB12 HEX5[2] PIN_P7 LEDR[13] PIN_AE15

HEX0[2] PIN_AC12 HEX5[3] PIN_T9 LEDR[14] PIN_AF13

HEX0[3] PIN_AD11 HEX5[4] PIN_R5 LEDR[15] PIN_AE13

HEX0[4] PIN_AE11 HEX5[5] PIN_R4 LEDR[16] PIN_AE12

HEX0[5] PIN_V14 HEX5[6] PIN_R3 LEDR[17] PIN_AD12

HEX0[6] PIN_V13 HEX6[0] PIN_R2 LEDG[0] PIN_AE22

HEX1[0] PIN_V20 HEX6[1] PIN_P4 LEDG[1] PIN_AF22

HEX1[1] PIN_V21 HEX6[2] PIN_P3 LEDG[2] PIN_W19

HEX1[2] PIN_W21 HEX6[3] PIN_M2 LEDG[3] PIN_V18

HEX1[3] PIN_Y22 HEX6[4] PIN_M3 LEDG[4] PIN_U18

HEX1[4] PIN_AA24 HEX6[5] PIN_M5 LEDG[5] PIN_U17

HEX1[5] PIN_AA23 HEX6[6] PIN_M4 LEDG[6] PIN_AA20

HEX1[6] PIN_AB24 HEX7[0] PIN_L3 LEDG[7] PIN_Y18

HEX2[0] PIN_AB23 HEX7[1] PIN_L2 LEDG[8] PIN_Y12

HEX2[1] PIN_V22 HEX7[2] PIN_L9 CLOCK_27 PIN_D13

HEX2[2] PIN_AC25 HEX7[3] PIN_L6 CLOCK_50 PIN_N2

HEX2[3] PIN_AC26 HEX7[4] PIN_L7

ecad \...

Documents