EC2257 Electronic Circuits II and Simulation LabCIRCUIT
DIAGRAM:With Feedback:
CROCROVin0.1uF560+10V2.2K0.1uFR147KR210KBC107Without
Feedback:
CRO100uFCROVin0.1uF560+10V2.2K0.1uFR147KR210KBC107MODEL
GRAPH
With FeedbackGain(in dB)Frequency (in Hz)
EXP. NO.:1CURRENT SERIES FEEDBACK AMPLIFIER
AIM:To study the frequency response of current series amplifier
with and without feedback
APPARATUS REQUIRED:
Sl. No.ApparatusRangeQuantity
1TransistorBC 1071
2Resistor47K,10K,2.2K,560 4
3Capacitor.1f,100f3
4CRO,FG
5Connecting wires, Bread board
THEORY:An amplifier whose fraction of output is fed back to the
input is called feedback amplifier. A feedback amplifier consists
of two parts namely amplifier circuit and feedback circuit.
Depending upon whether the feedback signal increases or decreases
the input signal it is classified into two.Positive Feedback If the
feedback signal is in phase with the input signal.Negative feedback
If the feedback signal is out of phase with the input signal.The
positive feedback increases the gain of the amplifier whereas the
negative feedback decreases the gain. In the current series
feedback connection a fraction of the output current is converted
into a proportional voltage by the feedback network and then
applied in series with the input.
Tabulation: With feedbackVi = S.NoFREQUENCY in HzOUTPUT VOLTAGE
Vo in voltsGAIN = 20 log(Vo/Vi)in db
DESIGN:
Vcc = IcRc + Vce+ Re Ie , Vce = Vcc /2 , Ve = Vcc /10 , Vb =
(Vce R2 ) / ( R1 + R2)Vb = Vbe + Ve , R2 = ( Ve ) / ( 10 Ie)Given
Ic = 2 mA , Ie = 2 mA , = 200 So Rc = 2 K , Re = 0.5 K , R1 = 47 K
, R2 = 10 K
Tabulation: Without feedbackVi = S.NoFREQUENCY in HzOUTPUT
VOLTAGE Vo in voltsGAIN = 20 log(Vo/Vi)in db
PROCEDURE: The connections are done as shown in the diagram. The
input voltage is set to a fixed value. Vary the frequency and note
down the output voltage. Repeat the same with feedback. Calculate
the gain and plot the graph.
RESULT: Thus the current series amplifier with and without
feedback is designed and its frequency response is plotted.
EXP. NO.:2VOLTAGE SHUNT FEEDBACK AMPLIFIER
AIM:To study the frequency response of voltage shunt feedback
amplifier with and without Feedback.
APPARATUS REQUIRED:
Sl. No.ApparatusRangeQuantity
1TransistorBC 1071
2Resistor3.3K,10K,2.2K
Each 1
3Capacitor.01f2
4CRO,FG
5Connecting wires, Bread board
THEORY:An amplifier whose fraction of output is fed back to the
input is called feedback amplifier. A feedback amplifier consists
of two parts namely amplifier circuit and feedback circuit.
Depending upon whether the feedback signal increases or decreases
the input signal it is classified into two.Positive Feedback If the
feedback signal is in phase with the input signal.Negative feedback
If the feedback signal is out of phase with the input signal.The
positive feedback increases the gain of the amplifier whereas the
negative feedback decreases the gain. In the voltage shunt feedback
connection a fraction of the output voltage is applied in parallel
with the input voltage through the feedback network The voltage
shunt feedback connection decreases both input and output
resistances of the feedback amplifier by a factor equal to (1+
Av)Tabulation: With feedbackVi =S.NoFREQUENCY in HzOUTPUT VOLTAGE
Vo in voltsGAIN = 20 log(Vo/Vi)in db
CIRCUIT DIAGRAM:With Feedback
Without Feedback:
MODEL GRAPH
With FeedbackGain(in dB)Frequency (in Hz)
DESIGN:
Assume Rf = 10 KLet R = Rf Rc = 2.5 KLet Rb = Rs Rf = 1.8 KSo by
solving Rc = 3.3 K and Rs = 2.2 K
Tabulation: Without feedbackVi =S.NoFREQUENCY in HzOUTPUT
VOLTAGE Vo in voltsGAIN = 20 log(Vo/Vi)in db
PROCEDURE: The connections are done as shown in the diagram. The
input voltage is set to a fixed value. Vary the frequency and note
down the output voltage. Repeat the same with feedback. Calculate
the gain and plot the graph.
RESULT: Thus the voltage shunt amplifier with and without
feedback is designed and its frequency response is plotted.
CIRCUIT DIAGRAM:
MODEL GRAPH
amplitude in volts
t in ms
EXP. NO.:3 RC PHASE SHIFT OSCILLATOR
AIM:To design and construct a RC phase shift oscillator to
generate a sine wave of a frequency f = 1.98 KHz.
APPARATUS REQUIRED:
Sl. No.ApparatusRangeQuantity
1TransistorBC 1091
2Resistor1K,10K,2.2K,69 K,4 K
1,1,3,1,1
3Capacitor.01f5
4CRO,FG
5Connecting wires, Bread board
THEORY: Oscillator is a feedback circuit where a fraction of
output voltage of an amplifier is fed back to the input in the same
phase. RC phase shift oscillators are a sine wave oscillator which
is used in the audio frequency range. It has a CE amplifier ,which
provides 180.phase shift to the input signal and three frequency
selective RC phase shift networks provides a phase shift of 60of
each , a total of 180 for a signal with frequency equal to specific
value, which corresponds to the output of the oscillator. Thus the
total phase shift between the input and output is360. The frequency
of oscillation is given byf = 1/ (2 RC(6+4K))
TABULATION:
Amplitudein voltsTime period(ms) (T)Frequency in Hz( f= 1/
T)
DESIGN:
Assume Vcc = 20 V , Ic = 2 mA , = 200 , f = 150 HZ, R =3.3 KVe =
Re Ie, Ve = Vcc /10 , Vce = Vcc / 2, Vcc = Vce + Ve + IcRc , R2 = (
Ve ) /( 10 Ie) Vb = (R2 Vcc)/ (R1 +R2) , f = 1/ (2RcC ( 4K+6)) , k
= Rc/ RSo Re = 1 K , Rc = 4 K , Re = 10 K , R1 = 69 K , k =1.2 and
C = 0.1F
PROCEDURE: The connection is made as per the circuit diagram.
Set the RPS to 20Volts. Observe the output and measure the time
period of the output waveform Vo , determine the frequency and
trace it Plot the output on a graph sheet. Compare the experimental
value with the theoretical value of output frequency.
RESULT: Thus the RC phase shift oscillator is designed to
generate a sine wave of frequency f = 1.98 KHz.
EXP. NO.:4 WEIN BRIDGE OSCILLATOR
AIM:To design Wein bridge oscillator for f=5 kHz using Op
amp.
APPARATUS REQURIED:
S.NoName of the componentsRange/TypeQuantity
1Op-ampIC 7412
2Resistor12K, 24K3.3K12
3Capacitor0.05F2
4CRO,FG30MHz1
5Connecting Wires--
THEORY:Generally, in an oscillator amplifier stage introduces
180 phase shift and feedback network introduces additional 180
phase shift, to obtain a phase shift of 360 around a loop. But wein
bridge oscillator uses non-inverting amplifier and hence does not
provide any phase shift during amplifier stage. As total phase
shift required is 0, in Wein bridge type no phase shift is
necessary through feedback. This is also RC Oscillator, which uses
RC type of feedback network. The closed loop circuit of the Wein
bridge oscillator gives the negative feedback. To compensate the
change ,an adaptive negative feedback is used. Since the op-amp
works as a non inverting amplifier, the feedback network need not
provide any phase shift. The circuit can be viewed as weinbridge
with a series RC network in one arm & a parallel RC network in
the adjoining arm. Resistors R1 &Rfare connected in remaining
two arms. The condition of zero phase shift is obtained by
balancing the bridge.
TABULATION:
TypeAmplitude(v)Time period(ms)
Sine Wave
DESIGN:
f = 5KHZ , C = 0.01 F , R1 = 10 K , gain of wein bridge
oscillator is 3f = 1/ (2RC) , A = 1+ (Rf /R1 )so R = 3.33 K , Rf =
20 K
CIRCUIT DIAGRAM:
VO
MODEL GRAPH:
PROCEDURE: Construct the circuit as shown in circuit diagram .
Observe the output waveform on the CRO. Adjust the feedback
resistor Rf to get a perfect sine waveform. Measure the amplitude
and frequency and plot the waveform.
RESULT: Thus the Wein bridge oscillator is designed to generate
a sine wave of frequency f = 5 KHz.
CIRCUIT DIAGRAM:
MODEL GRAPH
amplitude in volts
t in ms
EXP. NO.:5 HARTLEY OSCILLATOR
AIM:
To design a Hartley oscillator and to generate a sine wave of a
frequency of 4.59 KHz.
APPARATUS REQUIRED:
Sl. No.ApparatusRangeQuantity
1TransistorBC 1481
2Resistor22K,83K,10K,1 K
1,1, 1,1
3Capacitor.01f,.03 f,22 f2,1,1
4Inductance box2
5CRO,FG
6Connecting wires, Bread board
THEORY:It is a sinusoidal oscillator which uses a single tapped
coil having two parts named L1 and L2.The tank circuit also
includes a capacitor. The centre point of L1 and L2 is grounded.
They are inductively coupled and form an auto transformer or a
split tank inductor. Feedback between the input and output circuit
is accomplished through the autotransformer action which gives 180
phase shift .The transistor introduces 180 phase shift, therefore
the total phase shift is 360 and hence the feedback is positive or
regenerative. In The circuit R1 and R2 form a voltage divider for
providing base bias and RE is an emitter swamping resistor to add
stability to the circuit. When Vcc is applied, an initial bias is
established by R1 and R2 and oscillations are produced because of
positive feedback from the LC tank circuit.
TABULATION:Amplitudein voltsTime period(ms) (T)Frequency in Hz(
f= 1/ T)
DESIGN:
Vcc = 10 V , Ic = 1 mA , = 200 , C = 0.01 F Vce = Vcc /2 , Ve =
Vcc /10 , Vb = Vbe + Ve , Vcc = IcRc + Ve + Vce , f = 1/(2 ( Leq
C))Vb = ( R2 Vcc) / (R1+ R2) , R2 = ( Ve ) / (10 Ie) So Vce = 5V,
Ve = 1 V, Re = 1K , Vb = 1.7V , Rc = 4 K , R2 = 20 K , R1 = 100 K ,
Leq = 120 , Leq = L1 +L2so L1 = 60 mH, L2 = 60 mH
PROCEDURE: The connection is made as per the circuit diagram.
Set the RPS to 10Volts. Observe the output and measure the time
period of the output waveform Vo, determine the frequency and trace
it Plot the output on a graph sheet. Compare the experimental value
with the theoretical value of output frequency.
RESULT: Thus the Hartley oscillator is designed to generate a
sine wave of frequency f = 4.59 KHz.
COLPITTS OSCILLATOR
EXP. NO.:6
AIM:To design a Colpitts oscillator to generate a sine wave of a
frequency 9.188 KHz.
APPARATUS REQUIRED:
Sl. No.ApparatusRangeQuantity
1TransistorBC 1481
2Resistor22K,100K,10K,1 K
1,1, 1,1
3Capacitor.01f,0.1 f,22 f1,1,1
4Inductance Box1
5CRO,FG
6Connecting wires, Bread board
THEORY:A colpitts oscillator is to generate sine wave in the
frequency range 1-500Mhz.It uses a LC tuned circuit with a CE
amplifier to obtain oscillations. The feedback consists of two
capacitors C1 and C2 and an inductor L. The Resistors R1 , R2 and
RE provide dc bias to the transistor. The feedback between the
output and input circuit is accomplished by the voltage developed
across the capacitor C2 Feedback between the input and output
circuit is 180 phase shift .The transistor introduces 180 phase
shift, therefore the total phase shift is 360 and hence the
feedback is positive or regenerative. When Vcc is applied, an
initial bias is established by R1 and R2 , the capacitors C1 and C2
are charged . The capacitors discharge through the coil(L) which
sets up the frequency of oscillations f = 1/(2 (L Ceq))where Ceq=
C1 C2 / C1+ C2.The oscillations across the capacitor C2 is fed back
to the base-emitter junction and appear in an amplified form at the
collector.
TABULATION:
Amplitudein voltsTime period(ms) (T)Frequency in Hz( f= 1/
T)
DESIGN:
Vcc = 10 V , Ic = 1 mA , = 200 Vce = Vcc /2 , Ve = Vcc /10 , Vb
= Vbe + Ve , Vcc = IcRc + Ve + Vce , Vb = ( R2 Vcc) / (R1+ R2) , R2
= ( Ve ) / (10 Ie) So Vce = 5V, Ve = 1 V, Re = 1K , Vb = 1.7V , Rc
= 4 K , R2 = 20 K , R1 = 100 Kf = 1 /(2 ( L Ceq))let L = 60 mH , C
eq = (C1 C2) / (C1+C2)so C1 = 0.01 F , C2 = 0.01 F
CIRCUIT DIAGRAM:
Rc4K0.01uF0.1uF+10VRe1KC10.01uFBC148VoL60mHC20.01uFR222KCe22uFR1100K
MODEL GRAPH
amplitude in volts
T in ms
PROCEDURE:1. The connection is made as per the circuit
diagram.2. Set the RPS to 10Volts.3. Observe the output and measure
the time period of the output waveform Vo , determine the frequency
and trace it4. Plot the output on a graph sheet.5. Compare the
experimental value with the theoretical value of output
frequency.
RESULT: Thus the Colpits oscillator is designed to generate a
sine wave of frequency f = 9.188 KHz.
CIRCUIT DIAGRAM:
CROCROVin0.01uF+10V516mH0.01uFR24.7KBC107 0.001f
EXP. NO.:7
CLASS C TUNED AMPLIFIER
AIM:To design construct and test a Class C tuned amplifier for a
tuning frequency of 7 KHz.
APPARATUS REQUIRED:
Sl. No.ApparatusRangeQuantity
1TransistorBC 1071
2Resistor4.7 K
1
3Capacitor.01f,0.1 f,.001 f2,1,1
4Inductance Box1
5CRO,FG
6Connecting wires, Bread board
THEORY:Tuned amplifier is used to amplify the input signal at
the tuned frequency only. The input signal other than tuning
frequency are attenuated. The class C amplifier is developed to
make the circuit operate only for portion of input signal, i.e less
than 90 degrees. The Class C amplifier works on the principle of
tuning the parallel RLC resonant circuit to tuning frequency. The
value of Lc decides the tuning frequency and is related as f= (1/
(2 (Lc))). The values of LC are chosen for the required tuning
frequency interval. During the remaining period the Q is in cut-off
region and no current flows through its collector. The energy in
the tank circuit supplies the load current through capacitor. Once
the input signal frequency is out of the tuning frequency, the
oscillation in the tank circuit cannot be sustained. Thus the
circuit attenuates input signals other than tuning frequency.
TABULATION: Vi = S.NoFREQUENCYin HzOUTPUT VOLTAGEVo in
voltsGAIN= 20 log(Vo/Vi)in db
DESIGN:
fr = 1 / (2 ( LC) ) assume f = 7 KHZ , C = 0.001 F so L = 517
mH
PROCEDURE: Connections are made as shown in the circuit diagram.
Input signal is set at 6MHz , 1V peak is given and the
corresponding output is noted from the CRO Observe the output and
measure the time period and amplitude of the output waveform Vo ,
determine the frequency and trace it Obtain the tuning frequency
from the plot of the frequency response..
RESULT: Thus the Class C tuned amplifier is designed for a
tuning frequency of 7 KHz.
EXP. NO.:8INTEGRATOR ,DIFFERENTIATOR , CLIPPERS AND CLAMPERS
AIM:To construct and test integrator, differentiator, clippers
and clampers circuit and to obtain the output waveform.
APPARATUS REQUUIRED:
Sl. No.ApparatusRangeQuantity
1Resistor1 K,560
1
2Capacitor0.1 f,1 f1,1
3CRO,FG
4Diode1N40071
5Connecting wires, Bread board
THEORY:Integrator:The circuit performs the mathematical
operation of integration, that is , the o/p waveform is the
integral of the i/p waveform. The output voltage Vo (t) = - ( 1 / R
C)vi(t) dtDifferentiator:The circuit performs the mathematical
operation of differentiation , that is , the o/p waveform is the
derivative of the i/p waveform. The output voltageVo(t) = - R C
(dvi / dt) Clippers:Clippers have the ability to clip off a portion
of the input signal without distorting the remaining part of the
alternating waveform.. The half wave rectifier is an example of the
simplest form of diode clipper one resistor and diode. Depending
upon the orientation of the diode, the positive or negative region
of the input signal is clipped off.Clippers are of two: I . Series
ii. ParallelSeries configuration is defined as one where diode is
in series with the load, while the parallel the diode is connected
in parallel to the load.Clampers:The clamping network is one that
will clamp a signal to different dc level. The circuit has a diode,
resistor and a capacitive element, but it can also employ an
independent dc supply to introduce an additional shift. The
magnitude of R and C must be chosen that the time constant = RC is
large enough that the voltage across the capacitor does not
discharge significantly during the interval diode is
nonconducting.
CIRCUIT DIAGRAM
Integrator
Differentiator
TABULATION:
Amplitude in VTime period (ms)
Input
Output
DifferentiatorIntegrator
Amplitude in VTime period (ms)
Input
Output
CLIPPERS:Positive Clipper:
Negative Clipper:
TABULATION:Positive Clipper:Negative Clipper:Amplitude(in
volts)Time Period(in msec)Amplitude(in volts)Time Period(in
msec)
InputInput
OutputOutput
CLAMPERS:Positive Clamper:
Negative Clamper:
TABULATION:Positive Clamper:Negative Clamper:Amplitude(in
volts)Period(in sec)Amplitude(in volts)Period(in sec)
InputInput
OutputOutput
MODEL GRAPH:Clampers:Clippers:Input Signal:Input Signal:
Positive Clamped Output:Negative Clipped Output:
Negative Clamped Output:Positive Clipped Output:
PROCEDURE:
1) Connect the differentiator circuit. Adjust the signal
generator to produce a 1V peak Sine wave at 100Hz. Square wave at
100 Hz 2)Observe i/p and o/p waveform on the oscilloscope .Measure
and record the peak value of Vo and the phase angle of Vo w.r.t
Vi.3) Connect the integrator circuit Adjust the signal generator to
produce a 1V peak Sine wave at 5kHz. Square wave at 5kHz 4)Observe
and record the input and the output waveforms.
RESULT: To integrator, differentiator, clippers and clampers
circuit are constructed and the output waveform is obtained.
CIRCUIT DIAGRAM
MODEL GRAPH
DESIGN:
Let R = 150 K , Vcc = 5 V , hfe = 10 , Ic = 3 mA , Vce (sat) =
0.2 V , PW = PW = 0.69 RC , So C = 0.06 FRc2 = { Vcc Vd - Vce (sat)
] / Ic , Rb2 = [ Vbe + Vcc Vdt ] / Ib2 , Ib2 = Ic / hfe So Rc2 = 1
K = Rc1 , Rb2 = 12 KVb = (Vcc R2) /(R1 +R2) , Vb = Vbe + Ve So R1 =
3.8 K , Vb = 1.2 V
EXP. NO.:9 MONOSTABLE MULTIVIBRATOR
AIM:To design, construct and test a monostablemultivibrator.
APPARATUS REQUIRED:Sl. No.ApparatusRangeQuantity
1TransistorBC 107 2
1Resistor1 K,12K,22 K
3,1,1
2Capacitor0.1 f,1 f1,1
4Diode1N40071
5Connecting wires, Bread board
THEORY:MonostableMultivibrator is also called as one shot
Multivibrator and can be used to generate a gating pulse, whose
width can be controlled. The MonostableMultivibrator provides a
single pulse of desired duration in response to an external
trigger. The external trigger cases the circuit to go to a
Quasi-stable state. After a certain interval, the circuit comes to
stable state.The width or duration of the pulse is obtained at the
collector or output of either transistor of the
MonostableMultivibrator, is given by the expression, tp = 0.69 R3
C1 seconds.
TABULATION:
Amplitude (in volts)Pulse width (in msec)
PROCEDURE:1. The connection is made as per the circuit
diagram.2. Apply a negative going pulse as the input signal.3.
Observe the output voltage across the capacitor Vc and the output
waveform Vo and trace it.
RESULT: Thus a monostable multivibrator is designed and
constructed.
CIRCUIT DIAGRAM:
MODEL GRAPH:
TABULATION:
Amplitude(in volts)Time Period(in msec)
DESIGN:Let Vcc = 10 V , Ic = 10 mA, = 200 , Vce (sat) = 0.2 V ,
f = 7.24 KHZ , R = 10 KVcc = Ic Rc +Vce , T = 1.38 RCSo Rc = 1 K ,
C = 0.01 F
EXP. NO.:10COLLECTOR COUPLED ASTABLE MULTIVIBRATOR
AIM:To design an astablemultivibrator and to obtain the output
waveform for a frequency of 7.24 KHz.
APPARATUS REQUIRED:
Sl. No.ApparatusRangeQuantity
1TransistorBC 109 2
1Resistor10 K,1K,
2,2
2Capacitor0.01 f2
4Connecting wires, Bread board
THEORY:The Astablemultivibrator has 2 Quasi-states. And theyre
unstable. Without any external trigger, the multivibrator keeps on
alternating in states.The frequency of oscillation is determined by
the values of R and C used in the circuit. Astablemultivibrator is
also called as free running oscillator.as soon as we switch on the
power supply any one of the transistor is turned on, since both the
transistors are not identical. There will be voltage drop on the
collector of that transistor, which is taken as an input to the
second transistor. The second transistor is connected to the
collector of the first transistor .Hence the second transistor
turns on now. This process repeats, finally we get a square wave as
an output.
PROCEDURE:Connections are given as per the circuit
diagram.Supply voltage is kept at 10V.CRO connected at the output
is adjusted and the square wave output is obtained.The amplitude
and time period (Ton and Toff) of the signal is noted.The output
waveform is plotted in a graph, taking Amplitude in Y-axis and Time
period in X-axis.Then the practical value of the frequency is
calculated.
RESULT: Thus an astablemultivibrator is designed and its output
waveform for a frequency of 7.24 KHz is obtained.
CIRCUIT DIAGRAM:
EXP. NO.:13 SECOND ORDER LOW PASS FILTER
AIM:To plot the frequency response of active second order low
pass filter using OP-AMP in Pspice.
ALGORITHM:Mark the each node with a number.Enter each component
between nodes.Call the UA 741 Op-amp from the .NOM library.Use the
.AC statement to vary the frequency.Observe the frequency response
of the filter.Calculate the Roll-off rate
SIMULATOR:Pspice simulator.
THEORY:An improved filter response can be obtained by using a
second order active filter consists of two RC pairs. It has a
roll-off rate of -40dB/decade. The transfer function of a low pass
filter is H(s) = AoH2 S2 + HS + H2 For n=2, the clamping factor =
1.414, the pass band gain, Ao=3-=1.586. Cut-off frequency of the
filter =1/2RC.
PSPICE PROGRAM:.Libv1 1 0 ac 1v sin(0v 1v 1k)v2 5 0 dc +15vv3 7
0 dc -15vrf 4 6 5.8kri 4 0 10kc1 2 6 0.1fc2 3 0 0.1fr1 1 2 1.6kr2 2
3 1.6kx 3 4 5 7 6 ua741.lib.ac dec 10 100 3k.probe.end
RESULT: The frequency response of active second order low pass
filter using OP-AMP in Pspice is obtained.
CIRCUIT DIAGRAM:
MODEL GRAPH:
EXP. NO.:12 ACTIVE HIGH PASS FILTER
AIM:To design a active high pass filter for the cutoff frequency
of 1 kHZ.
ALGORITHM:Mark the each node with a number.Enter each component
between nodes.Call the UA 741 Op-amp from the .NOM library.Use the
.AC statement to vary the frequency.Observe the frequency response
of the filter.Calculate the Roll-off rate
SIMULATOR:Pspice simulator
THEORY:A high pass filter is a filter that passes high
frequencies well, but attenuates frequencies lower than the cutoff
frequency. The actual amount of attenuation frequencies varies from
filter to filter. Applications of Active High Pass Filters are in
audio amplifiers, equalizers or speaker systems to direct the high
frequency signals to the smaller tweeter speakers or to reduce any
low frequency noise or "rumble" type distortion.
PROCEDURE: Connections are made as per the circuit diagram.
Gives the input voltage Vin which is constant for all the readings.
Vary the frequency using AFG and note the corresponding output
voltage (Vo) Similarly take several readings Calculate the gain
using 20log(Vo/Vin) Plot the graph between frequency in Hz and gain
in dB.
PSPICE PROGRAM:
.libVin 1 0 ac 5v sin(0v 5v 1k)V2 5 0 dc 15vV3 7 0 dc -15vR1 2 6
1.6kR2 3 0 1.6kRi 4 0 10kRf 4 6 5.86kC1 1 2 .1MC2 2 3 .1MX 3 4 5 6
7 ua741.lib.ac dec 10 100 3k.probe.end
RESULT: Thus a active high pass filter for the cutoff frequency
of 1 kHZ is obtained.
CIRCUIT DIAGRAM:
EXP. NO.:13 CMOS INVERTER
AIM:To plot the transient response of the output signal of the
CMOS INVERTER circuit from 0ms to 50ms in steps of 1ms using
Pspice.
ALGORITHM:Mark the each node with a number.Enter each component
between nodes.Call the UA 741 Op-amp from the .NOM library.Use the
.AC statement to vary the frequency.Observe the frequency response
of the filter.Calculate the Roll-off rate
SIMULATOR:Pspice simulatorPROGRAM:.libVd 1 0 dc 5vVin 2 0 pulse
(0 5v 0 1n 1n 2m 5m)M1 3 2 1 1 pmod.model pmod pmosM2 3 2 0 0
nmod.model nmod nmos.trans 1ms 10ms.probe.end
THEORY:CMOS circuits take the advantage of the fact that both
N-channel and P- channel devices can be fabricated on the same
substrate. The basic CMOS circuit is the INVERTER which consist of
one P-channel and one N-channel transistor. The source terminal of
the P-channel is at VDD and source terminal of N-channel device is
at ground.When the input is low, both gates are at zero potential.
The input is at VDD relative to the source of the P-channel device
and at 0V relative to the source of the N-channel device. The
result is that the P-channel device is under these conditions,
there is a low impedance path from VDD to the output and a very
high impedance from output to ground. Therefore, the output voltage
goes to high level, VDD under normal loading conditions.When the
input is high both gates are at VDD and the situation is reversed.
The P-channel device is turned OFF and N-channel is turned ON. The
result is that the output approaches low level of 0V.
TRUTH TABLE:
INPUTOUTPUT
AY=A
0110
RESULT: Thus the transient response of the output signal of the
CMOS INVERTER circuit from 0ms to 50ms in steps of 1ms using Pspice
is plotted.
CIRCUIT DIAGRAM:
EXP. NO.:14 CMOS NAND
AIM:To plot the transient response of the output signal of the
CMOS NAND circuit from 0ms to 50ms in steps of 1ms using
Pspice.
ALGORITHM:Mark the each node with a number.Enter each component
between nodes.Call the UA 741 Op-amp from the .NOM library.Use the
.AC statement to vary the frequency.Observe the frequency response
of the filter.Calculate the Roll-off rate
SIMULATOR:Pspice simulatorPROGRAM:.libVd 1 0 dc 5vV1 3 0 pulse
(0 5v 0 1n 1n 5m 5m 10m)V2 2 0 pulse (0 5v 0 1n 1n 5m 5m 10m)M1 5 2
1 1 pmodM2 5 3 1 1 pmod.model pmod pmosM3 5 3 4 4 nmodM4 4 2 0 0
nmod.model mod nmos.trans 1ms 50ms.probe.end
THEORY:CMOS circuits take the advantage of the fact that both
N-channel and P- channel devices can be fabricated on the same
substrate. CMOS circuits consists of both types of MOS devices,
interconnected to form logic functions.Another CMOS basic gate is
the NAND gate which consists of two P-type units in parallel and
two N-type units in series as shown in circuit. If all inputs are
high, both P-type transistors are turned OFF and both N-channel
transistors are turned ON. The output has low impedance to the
ground and produces a low state. If any input is low, the
associated N-channel transistor is turned OFF and the associated
P-channel transistor is turned ON. The output is coupled to VDD and
goes to high state. If both the inputs are low, the P-type
transistor are turned ON and both the N-channel transistor are
turned OFF. The output has high impedance to the ground and
produces a high state. Multiple input NAND gates may be formed by
placing equal number of P-type and N-type transistors in parallel
and series respectively.
TRUTH TABLE:
INPUTOUTPUT
ABY=(AB)
001101011110
RESULT: Thus the transient response of the output signal of the
CMOS NAND circuit from 0ms to 50ms in steps of 1ms using P spice is
plotted.
CIRCUIT DIAGRAM:
EXP. NO.:15CMOS NOR
AIM:To plot the transient response of the output signal of the
CMOS NOR circuit from 0ms to 50ms in steps of 1ms using Pspice.
ALGORITHM:1. Mark the each node with a number.2. Enter each
component between nodes.3. Call the UA 741 Op-amp from the .NOM
library.4. Use the .AC statement to vary the frequency.5. Observe
the frequency response of the filter.6. Calculate the Roll-off
rate
SIMULATOR:Pspice simulator
PROGRAM.libvdd 3 0 dc 5vv1 1 0 pulse(0 5v 0 1n 1n 5m 10m) v2 2 0
pulse(0 5v 0 1n 1n 5m 10m)m1 4 1 3 3 pmodm2 5 2 4 4 pmodm3 5 1 0 0
nmodm4 5 2 0 0 nmod.model nmod nmos.model pmod pmos.tran 0ms
50ms.probe.end
THEORY:CMOS circuits take the advantage of the fact that both
N-channel and P- channel devices can be fabricated on the same
substrate. CMOS circuits consists of both types of MOS devices,
interconnected to form logic functions.Another CMOS basic gate is
the NOR gate which consists of two N-type units in parallel and two
P-type units in series as shown in circuit. If all inputs are low,
both P-type transistors are turned ON and both N-channel
transistors are turned OFF. The output is coupled to VDD and goes
to high state. If any input is high, the associated P-channel
transistor is turned OFF and the associated N-channel transistor is
turned ON, connecting the output to the ground and causing a low
level output. If both the inputs are high, the P-channel units are
turned OFF and both the N-channel units are turned ON. The output
goes to low state.
INPUTOUTPUT
ABY=(AB)
001101011110
TRUTH TABLE:
RESULT: Thus the transient response of the output signal of the
CMOS NOR circuit from 0ms to 50ms in steps of 1ms using Pspice is
plotted.
CIRCUIT DIAGRAM:
EXP. NO.:16DIFFERENTIAL AMPLIFIER USING OP-AMP
AIM:To calculate the difference output using OP-AMP and to plot
the transient response of output using Pspice.
ALGORITHM:Mark the each node with a number.Enter each component
between nodes.Call the UA 741 Op-amp from the .NOM library.Use the
.AC statement to vary the frequency.Observe the frequency response
of the filter.Calculate the Roll-off rate
SIMULATOR:Pspice simulatorPROGRAM:.libv1 2 0 ac 10v sin(0 10v
1k)v2 1 0 ac 2v sin(0 2v 1k)v3 5 0 dc +15vv4 7 0 dc -15vr1 2 3 1kr2
1 4 1kr3 3 6 1kr4 4 0 1kx 4 3 5 7 6 ua 741.lib.tran 0.1ms
10ms.probe .end
THEORY:A circuit that amplifier the difference between two
signals is called as difference amplifier or differential
amplifier. This type of amplifier is very useful in instrumentation
circuits. The output voltage of the differential amplifier is given
byVo =R2/R 1 [V 1-V 2]Such a circuit is very useful in detecting
even very small difference in the signals, since the gain R2/R 1
can be chosen to be very large. The main purpose of difference
amplifier is to provide high gain to the difference mode signal and
to cancel the common mode signal. The relative sensitivity of an
OP-AMP to a difference signal as compared to a common mode signal
is called common mode rejection ratio and gives the figure of merit
of the differential amplifier.
RESULT: Thus the difference output using OP-AMP is calculated
and the transient response of output using Pspice is plotted.
CIRCUIT DIAGRAM:
EXP. NO.:17R 2R LADDER D-A CONVERTOR
AIM:To simulate R 2R ladder type D- A convertor using pspice
simulator.
ALGORITHM:Mark the each node with a number.Enter each component
between nodesSimulate the circuit using PSPICE.Use the .PLOT TRAN
functions to obtain the graph.Use the TRAN function to obtain the
transient function.
SIMULATOR:Pspice simulator
THEORY:Wide range of transistors are required for binary
weighted resistor type digital to analog convertor. This can be
avoided by R 2R ladder type digital to analog converter where only
two value of resistor are required. It is well suited integrated
circuits realization. The typical values of ranges from 25 k. for a
bit digital to analog convertor where the position corresponds to
binary word 100 output voltage.[-VR( 2/ 3R) ] /[2R +(R/3R)] =
[-VR/4]
PSPICE PROGRAM:
.libv1 1 0 dc -10vv2 5 0 dc +15vv3 7 0 dc =15vr1 8 0 20kr2 8 1
20kr3 4 1 20kr4 3 1 20kr5 8 4 10kr6 4 3 10kr7 3 2 10kr8 2 6 20kx 0
2 5 7 6 ua 741.lib.tran 1ms 10ms.probe.end
RESULT: Thus R 2R ladder type D- A convertor using pspice
simulator is simulated.
CIRCUIT DIAGRAM:
MODEL GRAPH:
EXP. NO.:18ASTABLE MULTIVIBRATOR
AIM:To simulate an astablemultivibrator using pspice
simulator.
ALGORITHM:Mark the each node with a number.Enter each component
between nodesSimulate the circuit using PSPICE.Use the .PLOT TRAN
functions to obtain the graph.Use the TRAN function to obtain the
transient function.
SIMULATOR:Pspice simulator
THEORY:The multivibrators are important group of regenerative
circuits that are used commonly in timing application. The
astablemultivibrator looks like a comparator with hysteresis
(Schmit trigger) except that the input voltage is replaced by a
capacitor. An astablemultivibrator is a square waveform generator.
Square wave is generated by forcing the op-amp to operate in the
saturation region. The astablemultivibrator is a free running
symmetrical multivibrator because it does not require any external
trigger. so it is also called as free-running oscillator.
PSPICE PROGRAM:
.libv1 3 0 dc +10vrc1 3 1 1krc2 3 6 1kr1 3 7 10kr2 3 2 10kc1 1 7
0.01ufc2 6 2 0.01ufq1 120 qnq2 6 7 0 qn.model qn npn (is=2e-16
bf=50 br=1 rb=5 rc=1 re=0 tf=0.2n tr=5ns).nodeset v(7)=0
v(2)=0.tran 0.1us 10us.probe.end
RESULT: Thus an astable multivibrator using pspice simulator is
simulated.
CIRCUIT DIAGRAM:
EXP. NO.:19 BISTABLE MULTIVIBRATOR
AIM:To simulate anbistablemultivibrator using pspice
simulator.
ALGORITHM:Mark the each node with a number.Enter each component
between nodesSimulate the circuit using PSPICE.Use the .PLOT TRAN
functions to obtain the graph.Use the TRAN function to obtain the
transient function.
SIMULATOR:Pspice simulator
THEORY:The bistable multi vibrator has 2 stable state. The multi
vibrator can exist in two states. It require an external trigger
pulse to change from one stable state to another. The circuit
remains in one stable state unless an external pulse is applied. It
is used for performance of many digital operations such as counting
and storing of binary information.
PSPICE PROGRAM:
.libv1 1 0 dc +12vv2 6 0 dc -3vv3 4 0 pulse(-5v 5v 0 1ns 1ns 5ms
10ms)rc1 1 2 1krc2 1 3 1kr1 5 2 5kr2 4 3 5kr3 4 6 10kq1 2 4 0 qnq2
3 5 0 qn.model qn npn (is=2e-16 bf=50 br=1 rb=5 rc=1 re=0 tf=0.2n
tr=5ns).nodeset v(4)=0 v(5)=0.lib.tran 1ms 100ms.probe.end
RESULT: Thus an bistable multivibrator using pspice simulator is
simulated.
CIRCUIT DIAGRAM:
MODEL GRAPH:
EXP. NO.:20 MONOSTABLE MULTIVIBRATOR
AIM:To simulate anmonostablemultivibrator using pspice
simulator.
ALGORITHM:Mark the each node with a number.Enter each component
between nodesSimulate the circuit using PSPICE.Use the .PLOT TRAN
functions to obtain the graph.Use the TRAN function to obtain the
transient function.
SIMULATOR:Pspice simulator
THEORY:Monostable multi vibrator has only one stable state and
the other state is unstable state. It is when an external trigger
pulse is applied the circuit goes into Quasi- stable state from its
normal state. After some interval the circuit automatically returns
to stable state.
PSPICE PROGRAM:.lib V1 1 0 dc 12v V2 6 0 dc -3v V3 4 0 pulse(-5v
5v 0 1ns 1ns 5ms 10ms) Rc1 1 2 1k Rc2 1 3 1k R1 5 2 5k R2 4 3 5k R3
4 6 10k Q1 2 4 0 qn Q2 3 5 0 qn .model qn npn (is=2e-16 bf=50 br=1
rb=5 rc=1 re=0 tf=0.2n tr=5ns) .nodeset v(4)=0 v(5)=0 .lib .tran
1ms 100ms .probe .end
RESULT: Thus an monostable multivibrator using pspice simulator
is simulated.
Additional Experiments
CIRCUIT DIAGRAM:
EXP. NO.:22 CMOS NAND USING FET
AIM:To plot the transient response of the output signal of the
CMOS NAND circuit from 0ms to 50ms in steps of 1ms.
APPARATUS REQUIRED:
S.No.ApparatusRangeQuantity
1234FETBREAD BOARDCONNECTING WIRESRPS
(0-30)V41FEW1
THEORY:CMOS circuits take the advantage of the fact that both
N-channel and P- channel devices can be fabricated on the same
substrate. CMOS circuits consists of both types of MOS devices,
interconnected to form logic functions.Another CMOS basic gate is
the NAND gate which consists of two P-type units in parallel and
two N-type units in series as shown in circuit. If all inputs are
high, both P-type transistors are turned OFF and both N-channel
transistors are turned ON. The output has low impedance to the
ground and produces a low state. If any input is low, the
associated N-channel transistor is turned OFF and the associated
P-channel transistor is turned ON. The output is coupled to VDD and
goes to high state. If both the inputs are low, the P-type
transistor are turned ON and both the N-channel transistor are
turned OFF. The output has high impedance to the ground and
produces a high state. Multiple input NAND gates may be formed by
placing equal number of P-type and N-type transistors in parallel
and series respectively.
TRUTH TABLE:
INPUTOUTPUT
ABY=(AB)
001101011110
RESULT: Thus the transient response of the output signal of the
CMOS NAND circuit from 0ms to 50ms in steps of 1ms is obtained.
CIRCUIT DIAGRAM:
EXP. NO.:15
CMOS NOR USING FET
AIM:To plot the transient response of the output signal of the
CMOS NOR circuit from 0ms to 50ms in steps of 1ms.
APPARATUS REQUIRED:
S.No.ApparatusRangeQuantity
1234FETBREAD BOARDCONNECTING WIRESRPS
(0-30)V41FEW1
THEORY:CMOS circuits take the advantage of the fact that both
N-channel and P- channel devices can be fabricated on the same
substrate. CMOS circuits consists of both types of MOS devices,
interconnected to form logic functions.Another CMOS basic gate is
the NOR gate which consists of two N-type units in parallel and two
P-type units in series as shown in circuit. If all inputs are low,
both P-type transistors are turned ON and both N-channel
transistors are turned OFF. The output is coupled to VDD and goes
to high state. If any input is high, the associated P-channel
transistor is turned OFF and the associated N-channel transistor is
turned ON, connecting the output to the ground and causing a low
level output. If both the inputs are high, the P-channel units are
turned OFF and both the N-channel units are turned ON. The output
goes to low state.
INPUTOUTPUT
ABY=(AB)
001101011110
TRUTH TABLE:
RESULT: Thus the transient response of the output signal of the
CMOS NOR circuit from 0ms to 50ms in steps of 1ms is obtained.
CIRCUIT DIAGRAM:
Exp. No.:23CLIPPER
Date :
AIM:To simulate an Clipper using pspice simulator.ALGORITHM:1.
Mark the each node with a number.2. Enter each component between
nodes3. Simulate the circuit using PSPICE.4. Use the .PLOT TRAN
functions to obtain the graph.5. Use the TRAN function to obtain
the transient function.SIMULATOR:Pspice
simulatorTHEORY:Clippers:Clippers have the ability to clip off a
portion of the input signal without distorting the remaining part
of the alternating waveform.. The half wave rectifier is an example
of the simplest form of diode clipper one resistor and diode.
Depending upon the orientation of the diode, the positive or
negative region of the input signal is clipped off.Clippers are of
two: I . Series ii. ParallelSeries configuration is defined as one
where diode is in series with the load, while the parallel the
diode is connected in parallel to the load.
TABULATION:Positive Clipper:Negative Clipper:Amplitude(in
volts)Time Period(in msec)Amplitude(in volts)Time Period(in
msec)
InputInput
OutputOutput
PSPICE PROGRAM:CLIPPER:*SPICE 03437.eps* A K ModelNameD1 0 2
diodeR1 2 1 1.0kV1 1 0 SIN(0 5 1k).model diode d.tran .05m
3m.end
Model output
RESULT: Thus an Clipper using pspice simulator is simulated.
CIRCUIT DIAGRAM:
Clamper:
Exp. No.:24CLAMPER
Date :
AIM:To simulate an Clamper using pspice simulator.ALGORITHM:1.
Mark the each node with a number.2. Enter each component between
nodes3. Simulate the circuit using PSPICE.4. Use the .PLOT TRAN
functions to obtain the graph.5. Use the TRAN function to obtain
the transient function.SIMULATOR:Pspice
simulatorTHEORY:Clampers:The clamping network is one that will
clamp a signal to different dc level. The circuit has a diode,
resistor and a capacitive element, but it can also employ an
independent dc supply to introduce an additional shift. The
magnitude of R and C must be chosen that the time constant = RC is
large enough that the voltage across the capacitor does not
discharge significantly during the interval diode is
nonconducting.
PSPICE PROGRAM:CLAMPER:Pspice program*SPICE 03443.epsV1 6 0 5D1
6 3 diodeC1 4 3 1000pD2 0 2 diodeC2 4 2 1000pC3 4 1 1000pD3 1 0
diodeV2 4 0 SIN(0 5 1k).model diode d.tran 0.01m 5m.end
MODEL OUTPUT:
TABULATION:Positive Clamper:Negative Clamper:Amplitude(in
volts)Period(in sec)Amplitude(in volts)Period(in sec)
InputInput
OutputOutput
RESULT: Thus an Clamper using p spice simulator is
simulated.
70Department of ECEACT