EASIROC, an easy & versatile ReadOut device for SiPM Stéphane CALLIER, Christophe DE LA TAILLE, Gisèle MARTIN-CHASSARD, Ludovic RAUX With precious help.

EASIROC, an easy & versatile ReadOut device

for SiPMStéphane CALLIER, Christophe DE LA TAILLE,

Gisèle MARTIN-CHASSARD, Ludovic RAUX

With precious help of : Dominique CUISY, Jean-Jacques JAEGER,

Nathalie SEGUIN-MOREAU, Jean-Luc SOCHA

[email protected] - TIPP 2011, Chicago, IL, USA, 11/06/2011 2

CONTENTS

• EASIROC Features

• EASIROC Measurements

• Projects using EASIROC

• Conclusion


EASIROC FEATURES (BASED ON SPIROC CHIP)

• 32-channel front-end readout• Individual 8-bit DAC for SiPM Gain adjustment• Energy measurement from 160fC to 320pC (1pe to 2000pe @

SiPM gain = 10^6)– 1 pe/noise ratio ~11– Variable gain preamplifier– Variable time constant CRRC² shaper (25 to 175ns)– Common 10-bit DAC for threshold adjustment– 2 multiplexed analog outputs (high gain, low gain) [tri state outputs]

• Trigger output– 1 pe/noise ratio ~24– Trigger on 1/3 pe (50fC)– 32 Trigger outputs– OR32 output– Trigger multiplexed output (latch included) [Tri state output]

• Individually addressable calibration capacitance• Low power : 4.84mW/channel, 155mW/chip

– Unused feature can be disabled to reduce power consumption– Power pulsing facility (idle mode with external signal)


EASIROC ANALOGUE CORE

V a ria ble L owG a in P A (4 b its )

H o ldR e a d

L o w G ai nM ul t i p l e xe dO utput

C h3 1 _ tr i g g e r

C hanne l 0

C o m m o n to the 3 2 c ha nne ls

C hanne l 3 1

V a ria ble H ighG a in P A (4 b its )

+

V_ thL atc h

R S

C hanne l 0 _ tr i g g e r

D isc ri

O R 3 2

S lo w S h a p e r2 5 - 1 7 5 n s

L G S lo w S h ap erVar iab le S h ap in g

T im e ( 3 b its )

1 5 n s

R e a d Tr i g g e rM ul t i p l e xe dO utput

L o w Ga inP r e A m p .

H G S low S ha pe rV a ria ble S ha ping

T im e (3 b its )

0 .1 p F - 1 .5 p F

1 .5 p F

1 0 -bi tD AC

R S o r D is cri

0 .1 p F - 1 .5 p F

1 5 p F

H igh Ga inP r e A m p .

H o ldR e a d

H i g h G ai nM ul t i p l e xe dO utput

+

S lo w S h a p e r2 5 - 1 7 5 n s

3 p F

in_ c a lib

B ip o la r F a s t S h a p e r8 -bi t D AC

0 -5 V

INC h0

O Nc 15p

3 p F

Cte s t

3 2i nputs

1i nput

1o utput

1o utput

1o utput

1o utput

3 2o utputs


EASIROC LAYOUT

Technology : AMS 0,35µm SiGe

Die size : 16.6mm²4.157 x 4.013 mm²

Package :– Naked

(PEBS)– TQFP160

Dis

crim

inat

ors

Sha

per

s

Pre

amp

s

32 S

iPM

in

puts

10-bit DAC

Ana

log

Mem

ory

32 t

rigge

r ou

tput

s

8-bi

t in

put

DA

Cs

2 MUX charge outputs (LG + HG)

OR32 output

1 MUX trigger output

Bandgap

TQFP: heigth=1.4 mm


TEST BOARD

2 ADCs2 ADCs

USBUSB

EASIROCEASIROC

ANALOGUE ANALOGUE OUTPUTsOUTPUTs

HV connectorHV connector

32 SiPM 32 SiPM connectionsconnections

FPGAFPGA

• Testboard allow easy acces to each EASIROC pin• Testboard layout & cabling @ LAL• Firmware using LAL USB interface• Labview software


SOFTWARE

• ASIC versatility :456 slow control bits• Acquisition system


Gain and dark rate uniformity correction

High voltage on the cable shielding

The input DACs allow to adjust HV channel by channel by slow control on each SiPM of the detector

2 examples for SiPM connection allowing input DAC use


INPUT DACs

DAC linearity

0

0,5

1

1,5

2

2,5

3

3,5

4

4,5

5

0 50 100 150 200 250 300

DAC

Volta

ge (V

)

-0,04

-0,03

-0,02

-0,01

0

0,01

0,02

0,03

0 50 100 150 200 250 300

DAC linearity on the 32 channels

• Input DAC to optimize SiPM bias voltage (SiPM gain)

• 8 bits on 4,5V range => LSB : 20mV

• 10µA sink capability• Ultra low power

(<1µW)• Linearity ±2%• DAC uniformity

between the 32 channels : ~3%


ANALOG OUTPUT (CHARGE)

Pedestal uniformity for each Gain output <0.7%

Pedestal removed

High Gain

Low Gain

Hold scanperformed onanalogue data

[using external ADC]

Time (ns)

ADC value

Pedestal dispersion

1,234

1,236

1,238

1,24

1,242

1,244

1,246

1,248

0 5 10 15 20 25 30

Channel

HG V

LG V


CHARGE MEASUREMENT


ANALOG OUTPUT

• Histogram for 1 to 10 pe- on both gains

Courtesy : Ryotaro HONDA


THRESHOLD DAC

• 10-bit DAC for Threshold adjustment (trigger)

• 10 bits on 1.3V range => LSB : 1.3mV

• Linearity ±0.3%


S-CURVES (TRIGGER EFFICIENCY)

OR32 output for 1pe on each channel

Dispersion : <5 DAC unit for 1pe(8fC/DAC unit) [Cf=200fF]

S-curve for 1pe- (160fC)

0

20

40

60

80

100

120

835 840 845 850 855 860 865 870 875 880 885

DAC code

Tri

gg

er

eff

icie

nc

y (

%)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

P edestal

Individual pedestal

OR32 output For pedestal

PEBS

Courtesy: Waclaw KARPINSKI

• PEBS is a project in Research & Development phase The purpose of the experiment is a precision

measurement of the electron & positron cosmic ray flux in the energy range from 1 to 2000 GeV.

250 µm

RTWH Aachen

G. Saracino, Orsay, July 2, 2009 the MU-RAY Project: high-resolution muon radiography with scintillators 16

The MU-RAY project: high-resolution muon radiography with

scintillators

Courtesy : Giulio Saracino

Courtesy : Giulio Saracino

INFN Napoli

• International Collaboration of physicists, geologists and volcanologists to perform muon radiography of geological structures, Mt. Vesuvius first of all

• Design and build muon telescopes to be operated in difficult environments. Requirements:

• modular, light, easy to transport and mount• little need for maintenance• very low power consumption

• Develop a methodology and a versatile instrument

Italy: Bologna,Firenze,Perugia,Napoli (INFN and Universities)

Istituto Nazionale Geofisica e Vulcanologia) Japan: Tokyo University and Hearth Research

InstituteUSA: Fermilab

Given the mountain topology and the deep crater, there are ≈2 km of rock to cross!

Location: Cable Cab(Seggiovia) 2.1 km

1.8 kmThe challenge of Mt. Vesuvius

Need for large detector areas!

International Collaboration of physicist,

Active target with MPPC readout

Tohoku University + KEK

Fast time response • Work in a high beam

intensity

Large gain (105106)• Possible to detect 1 photon

Operation in the magnetic field

• Combination of Imaging and Spectrometer

Trigger possibility

Courtesy: Ryotaro HONDA

SIPMED : SIlicium Photomultiplier for SIPMED : SIlicium Photomultiplier for bioMEDical imagingbioMEDical imaging

To develop a novel compact photodetection system with high To develop a novel compact photodetection system with high energy and temporal measurement capabilities for radio-guided energy and temporal measurement capabilities for radio-guided surgerysurgery Task 1 : Characterization of single SiPMs and SiPMs matrixes

performances (scintillation and fluorescent light measurements) under laboratory and real medical conditions (e.g. temperature up to 37 °C)

Task 2 : Design and conception of a new optimized SiPM read-out electronics for both scintillation and fluorescent light measurement

Miniaturisation of the electronic board ->

Task 3 : Development and validation of new per-operative prototypes :

1) a compact positron probe

2) a mono-pixel fluorescent probe

3) a large field-of-view and ultra-compact intraoperative gamma-camera

Courtesy: Laurent MENARD

IMNC


EASIROC SUMMARY

• 1pe- -> 2000pe- charge measurement

• 100% Trigger efficiency @ 1/3photo-electron

• Versatility & easy use– Testboard & Software ready to use, embedding acquisition system

• Very low power consumption– Full power pulsing capability– Unused stages can be shut down

• Large scale production in 2010– Already used in experiments (astrophysics, vulcanology, nuclear

physics, medical imaging)

• Any extra information available on http://omega.in2p3.fr

http://omega.in2p3.fr/

BACKUP SLIDES


• Reticle size : 18x25 mm2– 50-55 reticles/Wafer– 25 wafers

• Final arrangement:

– « Calice » chips produced:

• 7 Hardroc 2b => ~9000 chips• 1 Spiroc 2a => ~1250 chips• 1 Spiroc 2b => ~1250 chips• 1 Skiroc 2 => ~1250 chips

– Additionnal chips produced:

• 1 Spaciroc : JEM EUSO experiement=> ~1250 chips

• 1 Maroc 3 : for PMT readout=> ~1250 chips

• 3 Easiroc : for PEBS experiment=> ~3750 chips (5000 received)

• Production run for CALICE chips• => cost reduction for CALICE

Engineering run (2010)

SPIROC2BAnalog HCAL(SiPM)36 ch. 32mm²June 07 / June 08 / March 11

HARDROC2BDigital HCAL(RPC, µmegas or GEMs)64 ch. 16mm²Sept 06 / June 08 / Sept 09

SKIROC2ECAL(Si PIN diode)64 ch. 64mm²March 11

E-CAL

H-CAL (analog or digital)


SPIROC : One channel schematic

50 -100ns

50-100ns

Gain selection

4-bit threshold adjustment

10-bit DAC

15ns

DAC output

HOLD

Slow Shaper

Slow Shaper

Fast Shaper

Time measurement

Charge measurement

TDC ramp

300ns/5 µs

12-bit Wilkinson

ADC

Trigger

Depth 16

Depth 16

Depth 16

Common to the 36 channels

8-bit DAC

0-5V

Low gain Preamplifier

High gain Preamplifier

Analog memory

15pF

1.5pF

0.1pF-1.5pF

Conversion

80 µs

READ

Variable delay

0.1pF-1.5pF

IN

Discri

Gain

Flag TDC

DAQASIC

Chip ID register 8 bits

gain

Trigger discri Output

Wilkinson ADC Discri output

gain

Trigger discri Output

Wilkinson ADC Discri output

..…

OR36

EndRamp (Discri ADC Wilkinson)

36

36

36

TM (Discri trigger)

ValGain (low gain or high Gain)

ExtSigmaTM (OR36)

Channel 1

Channel 0

ValDimGray 12 bits

…

Acquisition

readout

Conversion ADC

+

Ecriture RAM

RAM

FlagTDC

ValDimGray

12

8

ChipID

Hit channel register 16 x 36 x 1 bits

TDC rampStartRampTDC

BCID 16 x 8 bits

ADC rampStartrampb (wilkinson

ramp)

16

16ValidHoldAnalogb

RazRangN

16ReadMesureb

Rstb

Clk40MHz

SlowClock

StartAcqt

StartConvDAQb

StartReadOut

NoTrig

RamFull

TransmitOn

OutSerie

EndReadOut

Chipsat


SPIROC ReadOut: token ring

Acquisition A/D conv. DAQ IDLE MODEChip 0

Chip 1 Acquisition A/D conv. DAQ IDLE MODEIDLE

Chip 2 Acquisition A/D conv. IDLE MODEIDLE

Chip 3 Acquisition A/D conv. IDLE MODEIDLE

Chip 4 Acquisition A/D conv. IDLE MODEIDLE DAQ

1ms (.5%) .5ms (.25%) .5ms (.25%)

1% duty cycle 99% duty cycle

198ms (99%)

• Readout architecture common to all calorimeters• Minimize data lines & power

5 ev

ents

3 ev

ents

0 ev

ent

1 ev

ent

0 ev

ent

Chip 0 Chip 1 Chip 2 Chip 3 Chip 4

Data bus

ILC beam


ILC beam structure and SPIROC running modes

Acquisition

1ms (.5%)

A/D conv..5ms (.25%)

DAQ.5ms (.25%)

1% duty cycle

IDLE MODE

99% idle cycle

198ms (99%)

time

Time between two trains: 200ms (5 Hz)

Time between two bunch crossing: 337 ns

Train length 2820 bunch X (950 µs)

Acquisition

1ms (.5%)

A/D conv..5ms (.25%)

DAQ.5ms (.25%)

1% duty cycle

IDLE MODE

99% idle cycle

198ms (99%)

time

Time between two trains: 200ms (5 Hz)

Time between two bunch crossing: 337 ns

Train length 2820 bunch X (950 µs)

Two orders of magnitude saved on the consumption by using the ILC beam structure and the power pulsing


Chip 1 Acquisition DAQ IDLE MODEIDLE

Chip 2 Acquisition IDLE MODEIDLE


Chip 4 Acquisition IDLE MODEIDLE DAQ

A/D conv.

A/D conv.

A/D conv.

A/D conv.


Chip 1 Acquisition DAQ IDLE MODEIDLE



Chip 4 Acquisition IDLE MODEIDLE DAQ

A/D conv.

A/D conv.

A/D conv.

A/D conv.Chip 0 Chip 1 Chip 2 Chip 3 Chip 4

5 ev

ents

3 ev

ents

0 ev

ent

1 ev

ent

0 ev

ent

Data bus

• Readout based on token ring mechanism initiated by DAQ

• One data line activated by each chip sequentially

• Readout rate few MHz to minimize power dissipation


OTHERS

• Default value for Slow Control– Chip ready to use after a simple SC reset (except

Threshold DAC)

• Debug embedded feature :– Analog Probe system allow to monitor each critical point

in the chip• 32 PreAmplifiers High Gain output • 32 PreAmplifiers Low Gain output • 32 Slow Shapers High Gain output • 32 Slow Shapers Low Gain output • 32 Fast Shapers output


S-CURVES (TRIGGER EFFICIENCY)

OR32 output for 1pe on each channel

Dispersion : <5 DAC unit for 1pe(8fC/DAC unit) [Cf=200fF]


INPUT PREAMPLIFIERS

• Bi-gain low noise preamp– Low noise charge preamplifier

capacitively coupled = voltage preamplifier

– Gain adjustable with 4 bits common to all preamps : Cf=0.1, 0.2, 0.4, 0.8 pF

– Positive input pulse– Power : 2 mW (unpulsed)

• High gain : – 15pF coupling capacitor – 8 mV/pe in High Gain– Noise : 1.4 nV/sqrt(Hz)

• Low gain at preamp level – 1.5pF coupling capacitor– 0.8 mV/pe, MAX : 2000 pe (300pC)

[@Cf=400fF]

L o w Ga inP r e A m p .

0 .1 p F - 1 .5 p F

1 .5 p F

0 .1 p F - 1 .5 p F

1 5 p F

H igh Ga inP r e A m p .

0.15

0.10

0.05

0.00

Vo

ut (V

)

500400300200100

Time (x10-9

s)

Cf=100fF Cf=100fF Cf=200fF Cf=300fF Cf=400fF Cf=500fF Cf=600fF Cf=700fF Cf=800fF Cf=900fF Cf=1pF Cf=1.1pF Cf=1.2F Cf=1.3pF Cf=1.4pF Cf=1.5pF

High gain charge output at different Cf Qinj= 1.5pC


TRIGGER TIME WALK

trigger time walk vs injected charge

0

2

4

6

8

10

12

0 1000 2000 3000 4000 5000

charge (in fC)

tim

e (

in n

s)


ANALOG CROSSTALK

• Very low electronic cross-talk : 0.3% (long distance cross talk due to slow shaper voltage reference: If this voltage decoupled with 100µF, it becomes negligible ~0.04%)

EASIROC, an easy & versatile ReadOut device for SiPM Stéphane CALLIER, Christophe DE LA TAILLE, Gisèle MARTIN-CHASSARD, Ludovic RAUX With precious help.

Documents

sipm connection

gain output charge

input dacsinput dac

analog outputs high

easiroc layouttechnology

easiroc analogue

analog outputhistogram

hv channel