Early output logic and Anti-Tokens

1 2004 MAPLD: 153Brej

Early output logic and Anti-Tokens

Charlie Brej

APT Group

Manchester University

2 2004 MAPLD: 153Brej

Overview

Synchronous ProblemsAsynchronous Logic

Why?How?

SolutionsEarly OutputAnti-Tokens

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Problems: Communication

Communication horizon“For a 60 nanometer

process a signal can reach only 5% of the die’s length in a clock cycle” [D. Matzke,1997]

Clock distributed using wave pipelining

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Problems: Performance

Cycletime

Unbalanced Stages

Clock Skew/Jitter

Transistor Variability

Signal Integrity

Worst – Averagecase performance

Real Computation

Clockoverheads

TimingAssumptionoverheads

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Clock! What is it good for?

No arguing with the clock9am - 5pm. No excuses!

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Bundled-Data

When you finish, do the next taskFlexitime

Request + Delay

Acknowledge

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How do you know when you are finished?

Synchronous:EstimateGlobal timing reference

Asynchronous (bundled-data)EstimateLocal delay elements

Asynchronous (delay-insensitive)When the data arrivesIntrinsic

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Becoming Delay Insensitive

Dual-RailTwo wires00 – NULL01 – Zero10 – One(11 – Not used)

Four Phase handshakeReturn to zero

R1

Ack

R0

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Early Output Logic

Dual-Rail interfacesOutput generated as

early as possibleTwo Early output cases

If either input is ‘0’ then the output is ‘0’

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Bit level pipelining

Forward completed parts of the resultPace workDon’t stall parts unless you have to

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Bit level pipelining

Forward completed parts of the resultPace workDon’t stall parts unless you have to

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Bit level pipelining

Forward completed parts of the resultPace workDon’t stall parts unless you have to

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0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

Inputs Present

Pro

babi

lity

of O

utpu

t

Branch unitinc. Coproc.

Branch unit

CompareLT/GE 8bit

CompareEqual 8bit

Adder bit 8

Mux 8:1

Memoryshift unit

ALU Slice

16 inputAND

Early Output cases

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Validity

Unnecessary late inputsMust be acknowledgedMust wait until they arrive

Validity signalLatch generatedReady to be acknowledged

Result before all inputs presentAcknowledge after all inputs present

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Synchronisation Hurts

No need to wait before generating result

Need to wait for input in order to acknowledge it

Unnecessary stall

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Anti-Tokens

Unnecessary late inputsStall the entire stage

Proactive approachSend a ‘cancel’ signal backward to the sourceAcknowledge before data arrives

Anti-Token latchesAssert validity early

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Anti-token generation

0

1

C

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Anti-token generation

0

A 1

C

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Anti-token Propagation

1

C

A

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Anti-token Propagation

1

C

AA

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Anti-token Token collisions

1 1 A A

1 1 A A?

A?1

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Anti-token Token collisions

1 1 A

1 1 A A1

A1

11

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Remove Unnecessary computation

Cycletime

Unbalanced Stages

Clock Skew/Jitter

Transistor Variability

Signal Integrity

Worst – Averagecase performance

Real Computation

Clockoverheads

TimingAssumptionoverheads

Unnecessary Computation/Delays

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Summary

AsynchronousDelay Insensitive

Safe No timing assumptions

Average case performanceRemove unnecessary computationAnti-tokens without mutual exclusion units