e. n Triconex - Nuclear Regulatory Commission · 2.0TEST OBJECTIVE . The objectives of the Hardware Validation Test [Ref. 8.1.3] are: 1. To confirm that the system hardware configuration

· n v e. n s·.~ s' i f"1 v· e. f"1 S·.~ s·

, ~/. Triconex Project: PG&E PROCESS PROTECTION SYSTEM REPLACEMENT Purchase Order No.: 3500897372 Project Sales Order: 993754

PACIFIC GAS & ELECTRIC COMPANY

NUCLEAR SAFETY-RELATED PROCESS PROTECTION SYSTEM

REPLACEMENT DIABLO CANYON POWER PLANT

PROTECTION SET I

HARDWARE V ALIDATION TEST REPORT

Document No. 993754-11-854-0 I Revision 1 I

August 07,2014 I

Author: Reviewers:

A roval: Kevin Vu

Gary.McDonald

NP Suffix

Gary.McDonald

Cover Page - Non-P copy of Redacted doc

Document: 993754-11-854-0 Title: Protection Set I Hardware Validation Test Report Revision: 1 Page: 2 of 9 Date: 08/07/2014

Document Change History

Revision Date Change Author 0 04/21/14 Initial issue S. Phan 1 08/07/14 Update document number per SVVP Rev 5 S. Phan


TABLE OF CONTENTS

1.0 PURPOSE ..................................................................................................... 4

2.0 TEST OBJECTIVE ..................................................................................... 4

3.0 DESCRIPTION OF THE TEST SYSTEM ............................................... 4

4.0 TEST SET-UP AND INSTRUMENTATION ........................................... 4

4.1 TEST SET-UP .............................................................................................................. 4

4.2 MONITORING INSTRUMENTATION AND INPUT SIMULATORS..................... 4

5.0 TEST PROCEDURE ................................................................................... 5

6.0 TEST RESULTS .......................................................................................... 5

6.1 TEST DOCUMENT EXECUTED ............................................................................... 5 6.2 ANOMALIES ............................................................................................................... 7 6.3 INTERIM CHANGES .................................................................................................. 8 6.4 TEST RESULTS SUMMARY ..................................................................................... 8

7.0 CONCLUSIONS .......................................................................................... 9

8.0 REFERENCES............................................................................................. 9

8.1 INVENSYS DOCUMENTS ........................................................................................... 9

9.0 ATTACHMENTS ........................................................................................ 9

9.1 ATTACHMENTS ........................................................................................................... 9


1.0 PURPOSE

The objectives of this Hardware Validation Test (HVT) Report are: 1. To list all executed test documents related to the HVT of the safety-related V10

Tricon System Protection Set I 2. To provide a summary of the HVT test results 3. To document any test failures identify from the HVT procedure document 4. To document the review and approval of the HVT

2.0 TEST OBJECTIVE The objectives of the Hardware Validation Test [Ref. 8.1.3] are:

1. To confirm that the system hardware configuration is consistent with the issued

design documents and is in proper working order 2. To confirm that the test configuration is correct (the required test equipment is

properly calibrated and ready to support acceptance testing)

3.0 DESCRIPTION OF THE TEST SYSTEM The HVT testing was conducted in a controlled environment at the Invensys Facility in Lake Forest, CA. The test system used in system and HVT testing was as follows:

1. V10 Tricon System Protection Set I with HARDWARE_PROTECTION_SET_1, PT2 file.

2. TriStation Laptop with Windows 7™ , TriStation v 4.9.0

More information on the test system used is provided in the Validation Test Plan [Ref. 8.1.1].

4.0 TEST SET-UP AND INSTRUMENTATION

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used including serial numbers and calibration dates, refer to the executed HVT test document.

Additional information on the test set-up and instrumentation is provided in the Validation Test Plan.

5.0 TEST PROCEDURE The HVT procedures demonstrate the compliance of the integrated V10 Tricon System Protection Set I with the functional requirements as described in Section 2.0 Test Objective. The executed versions of the test are listed in Section 6.4 Test Results Summary.

6.0 TEST RESULTS 6.1 TEST DOCUMENT EXECUTED

The table below provides a list of the test sections executed as defined in the Hardware Validation Test Procedure. The information in the table is organized by Document Number, Revision, and Section, referred to hereafter as Test Document Section. The Interim Change Notice (ICN) column lists the ICN(s) that apply to the Test Document Section. The Completion column lists the sign off date for the Test Document step or section. The Anomaly Report column lists the System Integration Deficiency Report(s) (SIDR) written against the Test Document Section. For test details, refer to the HVT procedure in the executed test binders. Note: One SIDR may have resulted in any number of ICNs. One ICN may have been initiated by any number of SIDRs. SIDRs are listed only against the Test Document Section(s) that they were written against (i.e. where the anomaly occurred). ICNs are listed only against the Test Document Section(s) to which they were written and apply.

For details and traceability between SIDRs and ICNs, refer to Sections 6.2 Anomalies and 6.3 Interim Changes. Not all SIDRs initiated during HVT can be directly attributed to test procedure execution. (Refer to Section 6.2 Anomalies, for a complete list of SIDRs)

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Test Document ICN Completion Anomaly

Report Document Number / Section Title Rev Section 993754-11-902-0 (HVT Procedure Protection Set I) 0

Prerequisites 8.0 N/A N/A N/A Prerequisites Requirements 8.1 None 04/14/14 None Procedure 9.0 N/A N/A N/A Protection Set I Hardware Power-Up / Checkout Test 9.1 N/A N/A N/A

Tricon Test Cabinet Protection Set I 9.1.1 None 04/14/14 None Tricon Chassis Power Supply 9.1.2 None 04/14/14 None Communication Module(s) 9.1.3 None 04/14/14 None Field I/O Calibration Check – Protection Set I 9.2 N/A N/A N/A Analog Input Module 3703EN 9.2.1 None 04/15/14 None Analog Input Module 3721N 9.2.2 None 04/15/14 None

Analog Output Module 3805HN and 3805E 9.2.3 None 04/15/14 SIDR 986

Digital Input Module 3503EN2, 3501TN2 and 3501E 9.2.4 ICN

540 04/16/14 SIDR 987

Digital Output Module 3601TN 9.2.5 None 04/16/14 None Relay Output Module 3636T 9.2.6 None 04/16/14 None


6.2 ANOMALIES

The table below provides a listing of the deficiencies identified and documented on System Integration Deficiency Reports (SIDR) during the HVT testing. See SIDR binder for complete detailed description and/or attachments.

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6.3 INTERIM CHANGES

The table below provides a listing of the Interim Change Notices (ICN) applied to the HVT procedure. See ICN binder for complete detailed change description and/or attachments.

6.4 TEST RESULTS SUMMARY The testing implemented all the requirements for the Hardware Validation Test as described in the Validation Test Specification [Ref. 8.1.2] The HVT procedure and Appendix listed below was executed successfully and met the acceptance criteria as defined in the Validation Test Specification.

Test Procedure Document Number Revision

Hardware Validation Test Protection Set I 993754-11-902-0 0

Appendix Document Number Revision Appendix 2 - I/O Verification Checklist – Protection Set I

993754-11-902-0 0

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7.0 CONCLUSIONS

After the execution of the HVT testing for the V10 Tricon System Protection Set I, the test results were independently reviewed by the Project Review Committee in accordance with PPM 6.0. This review ensured that the actual results met the acceptance criteria per the Validation Test Specification.

An anomaly report, (i.e. SIDR), was completed for any deficiencies found during testing. The completed anomaly reports are in the SIDR binder. There were a total of 2 SIDRs generated during test execution resulting in 1 ICN.

The validation test results were reviewed. This review ensured that all necessary test documents were executed successfully, and complete.

8.0 REFERENCES 8.1 INVENSYS DOCUMENTS 8.1.1 Validation Test Plan (VTP), 993754-1-813 Rev 3 8.1.2 Validation Test Specification (VTS), 993754-1-812 Rev 1 8.1.3 Protection Set I Hardware Validation Test (HVT) Procedure, 993754-11-902-0 Rev 0

9.0 ATTACHMENTS 9.1 ATTACHMENTS 9.1.1 Protection Set I Hardware Validation Test Procedure, 993754-11-902-0

e. n Triconex - Nuclear Regulatory Commission · 2.0TEST OBJECTIVE . The objectives of the Hardware Validation Test [Ref. 8.1.3] are: 1. To confirm that the system hardware configuration

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