Dynamic Memory Allocation

1

Dynamic Memory Allocation

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Outline

• Explicit Free List• Segregated Free List

• Suggested reading: 9.9

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Explicit free lists

• Explicit list among the free blocks using

pointers within the free blocks

• Use data space for link pointers

– Typically doubly linked

– Still need boundary tags for coalescing

– It is important to realize that links are not

necessarily in the same order as the blocks

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Explicit free lists

A B C

4 4 4 4 66 44 4 4

Forward links

Back links

A B

C

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Freeing with explicit free lists

• Where to put the newly freed block in the

free list

– LIFO (last-in-first-out) policy

• insert freed block at the beginning of the free list

• pro: simple and constant time

• con: studies suggest fragmentation is worse than

address ordered.

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Freeing with explicit free lists

• Where to put the newly freed block in the free list– Address-ordered policy

• insert freed blocks so that free list blocks are always in address order

– i.e. addr(pred) < addr(curr) < addr(succ)• con: requires search

• pro: studies suggest fragmentation is better than LIFO

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Segregated Storage

• Each size “class” has its own

collection of blocks

– Often have separate collection for every small

size (2,3,4,…)

– For larger sizes typically have a collection for

each power of 2

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Segregated Storage

1-2

3

4

5-8

9-16

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• Separate heap and free list for each size class

• No splitting• To allocate a block of size n:

– if free list for size n is not empty,• allocate first block on list (note, list can be implicit or

explicit)

– if free list is empty, • get a new page • create new free list from all blocks in page• allocate first block on list

– constant time

Simple segregated storage

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• To free a block:

– Add to free list

• Tradeoffs:

– fast, but can fragment badly

Simple segregated storage

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• Array of free lists, each one for some size

class

Segregated fits

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• To allocate a block of size n:– search appropriate free list for block of size m

> n

– if an appropriate block is found:

• split block and place fragment on appropriate list (optional)

– if no block is found, try next larger class

– repeat until block is found

– if no blocks is found in all classes, try more heap memory

Segregated fits

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• To free a block:– coalesce and place on appropriate list

(optional)

• Tradeoffs– faster search than sequential fits (i.e., log

time for power of two size classes)– controls fragmentation

• A simple first-fit approximates a best-fit over entire heap

– coalescing can increase search times• deferred coalescing can help

Segregated fits

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• A special case of segregated fits

– Each size is power of 2

• Initialize

– A heap of size 2m

Buddy Systems

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• Allocate

– Roundup to power of 2 such as 2k

– Find a free block of size 2j (k j m)

– Split the block in half until j=k

• Each remaining half block (buddy) is placed on the

appreciate free list

• Free

– Continue coalescing with the free buddies

Buddy Systems

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Memory Hierarchy (I)

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Outline

• Random-Access Memory (RAM)

• Nonvolatile Memory

• Suggested Reading: 6.1

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Random-Access Memory (RAM)

• Key features

– RAM is packaged as a chip.

– Basic storage unit is a cell (one bit per cell).

– Multiple RAM chips form a memory.

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Random-Access Memory (RAM)

• Static RAM (SRAM)– Each cell stores bit with a six-transistor circuit.

– Retains value indefinitely, as long as it is kept powered.

– Relatively insensitive to disturbances such as electrical noise.

– Faster and more expensive than DRAM.

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Random-Access Memory (RAM)

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Random-Access Memory (RAM)

• Dynamic RAM (DRAM)

– Each cell stores bit with a capacitor and

transistor.

– Value must be refreshed every 10-100 ms.

– Sensitive to disturbances.

– Slower and cheaper than SRAM.

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SRAM vs DRAM summary

Tran. Accessper bit time Persist?Sensitive? Cost Applications

SRAM 6 1X Yes No 100x cache memoriesDRAM 1 10X No Yes 1X Main memories,

frame buffers

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Conventional DRAM organization

• d x w DRAM:– dw total bits organized as d supercells of size w bits

cols

rows

0 1 2 3

0

1

2

3

internal row buffer

16 x 8 DRAM chip

addr

data

supercell(2,1)

2 bits/

8 bits/

memorycontroller

(to CPU)

pins

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Reading DRAM supercell (2,1)

• Step 1(a): Row access strobe (RAS) selects row 2.• Step 1(b): Row 2 copied from DRAM array to row buffer.

RAS=2cols

rows

0 1 2 3

0

1

2

3

internal row buffer

16 x 8 DRAM chip

row 2

addr

data

2/

8/

memorycontroller

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Reading DRAM supercell (2,1)

• Step 2(a): Column access strobe (CAS) selects column 1.• Step 2(b): Supercell (2,1) copied from buffer to data lines, and

eventually back to the CPU.

supercell (2,1)

cols

rows

0 1 2 3

0

1

2

3

internal row buffer

16 x 8 DRAM chip

CAS=1

addr

data

2/

8/

memorycontroller

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Memory modules

: supercell (i,j)

031 78151623243263 394047485556

64-bit doubleword at main memory address A

addr (row = i, col = j)

data

64 MB memory moduleconsisting ofeight 8Mx8 DRAMs

Memorycontroller

bits0-7

DRAM 7

DRAM 0

bits8-15

bits16-23

bits24-31

bits32-39

bits40-47

bits48-55

bits56-63

64-bit doubleword to CPU chip

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Enhanced DRAMs

• All enhanced DRAMs are built around the

conventional DRAM core

• Fast page mode DRAM (FPM DRAM)

– Access contents of row with [RAS, CAS, CAS,

CAS, CAS] instead of [(RAS,CAS), (RAS,CAS),

(RAS,CAS), (RAS,CAS)].

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Enhanced DRAMs

• Extended data out DRAM (EDO DRAM)

– Enhanced FPM DRAM with more closely spaced

CAS signals.

• Synchronous DRAM (SDRAM)

– Driven with rising clock edge instead of

asynchronous control signals

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Enhanced DRAMs

• Double data-rate synchronous DRAM (DDR SDRAM)– Enhancement of SDRAM that uses both clock

edges as control signals.– Different sizes of small prefetch buffers that

increase the effective bandwidth– DDR (2 bits), DDR2 (4 bits), and DDR3 (8 bits)

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Enhanced DRAMs

• Rambus DRAM(RDRAM)– An alternative proprietary technology with a

higher maximum bandwidth than DDR SDRAM

• Video RAM (VRAM)– Like FPM DRAM, but output is produced by

shifting row buffer

– Dual ported (allows concurrent reads and writes)

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Nonvolatile memories

• DRAM and SRAM are volatile memories– Lose information if powered off.

• Nonvolatile memories retain value even if powered off– Generic name is read-only memory (ROM).

– Misleading because some ROMs can be read and modified.

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Types of ROMs

• Programmable ROM (PROM)– Write once

• Erasable programmable ROM (EPROM)– Erase by ultraviolet light– Write by a special device– About 1000 times

• Electrically erasable PROM (EEPROM)– Reprogramming in-place on printed circuit cards

• Flash memory– Based on EEPROM

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Nonvolatile memories

• Firmware– Program stored in a ROM– BIOS (basic input/output system)

• Boot time code• a small set of primitive input and output

functions– graphics cards, disk controllers

• Translate I/O (input/output) requests from the CPU