Krish Chakrabarty 1 Dynamic Logic M p M e V DD PDN In 1 In 2 In 3 Out M e M p V DD PUN In 1 In 2 In 3 Out C L C L 2 phase operation: • Evaluation • Precharge Φ Φ Φ n network Φp network Φ Φ Krish Chakrabarty 2 Dynamic Logic • N+2 transistors for N-input function – Better than 2N transistors for complementary static CMOS – Comparable to N+1 for ratio-ed logic • No static power dissipation – Better than ratio-ed logic • Careful design, clock signal Φ needed
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Krish Chakrabarty 1
Dynamic Logic
Mp
Me
VDD
PDNIn1In2In3
OutMe
Mp
VDD
PUNIn1In2In3
Out
CL
CL
2 phase operation:• Evaluation
• PrechargeΦ
Φ
Φ
n network Φp network
Φ
Φ
Krish Chakrabarty 2
Dynamic Logic• N+2 transistors for N-input function
– Better than 2N transistors for complementary static CMOS – Comparable to N+1 for ratio-ed logic
• No static power dissipation– Better than ratio-ed logic
• Careful design, clock signal Φ needed
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Krish Chakrabarty 3
Example
Mp
Me
VDD
Out
A
B
C
• Ratio les s
• No Static Power Cons umption
• Nois e Margins s mall (NML)
• Requires Clock
Φ
Φ
Krish Chakrabarty 4
Dynamic Logic: Principles
Mp
Me
VDD
PDNIn1In2In3
Out
CL
Φ
Φ
• PrechargeΦ = 0, Out is precharged to VDD by Mp.Me is turned off, no dc current flows(regardless of input values)
• EvaluationΦ = 1, Me is turned on, Mp is turned off.Output is pulled down to zero dependingon the values on the inputs. If not, precharged value remains on CL.
Important: Once Out is discharged, it cannot be charged again!Gate input can make only one transition during evaluation
• Minimum clock frequency must be maintained• Can Me be eliminated?
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Krish Chakrabarty 5
Dynamic 4 Input NAND Gate
In1In2In3In4
Out
VDD
GNDφ
Krish Chakrabarty 6
Reliability Problems — Charge Leakage
Mp
Me
VDD
Out
ACL(1)
(2)
t
t
Vout
(b) Effect on waveforms(a) Leakage sources
precharge evaluate
Minimum Clock Frequency: > 1 MHz
A = 0
Φ
ΦΦ
(1) Leakage through reverse-biased diode of the diffusion area(2) Subthreshold current from drain to source
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Krish Chakrabarty 7
Charge Sharing (redistribution)
Mp
Me
VDD
Out
A
B = 0
CL
Ca
Cb
Ma
Mb
X
• Assume: during precharge, A and B are 0, Ca is discharged• During evaluation, B remains 0 and A rises to 1• Charge stored on CL is now redistributed over CL and Ca