Using IP-XACT™ in complex SoC I/O Integration and SoC Register Management IP-XACT Users Group : Session 1 ( In association with Texas Instruments) Dave Murray CTO Duolog
Using IP-XACT™ in complex SoC I/O Integration and SoC
Register Management IP-XACT Users Group : Session 1
( In association with Texas Instruments)
Dave MurrayCTODuolog
Jul 8, 2008 2
Background
Working on TI’s OMAP platform integration for several years
We have developed a range of SoC integration tools including• Register and memory map management• I/O fabric generation
Jul 8, 2008 3
High-level of
Abstraction
CAPTUREIMPORT GUI
SW HW DOC VAL DFT PWR Any
Duolog Tools Methodology
StandardizedInterfaces
Powerful GenerationFramework
VALIDATEExtensiveCoherency Checking
Data Model
BitwiseRegister Management
Jul 8, 2008 5
Bitwise – Register Management
Bitwise is an enterprise-level register management tool • Capture register and memory map
information• Validate the data and system integrity• Generate multiple output views
Jul 8, 2008 6
GENERATE
CAPTURE
IP/Sub-System Library
EXCELXMLCSVTXT
IP/Sub-System
IP/SubsystemFlow
Chip Level View
SystemFlow
SpecsRTL
Validation & Debug
SuiteValidation
API
FirmwareAPI
VALIDATE
RegisterDescriptions
Bitwise - Flows
Jul 8, 2008 7
IP Capture
Challenges• 1000s of IPs• Legacy data in multiple formats• Corner case scenarios
Solutions• Migrate to industry standard (IP-XACT™)• Efficient capture mechanism• Customized importers
CUSTOMER INTERNAL IPREPOSITORY
3rd Party - IP
New- IP
Challenges• IP-XACT™ syntax/semantics/extensions• Interpretation
Solutions• Co-operation between vendors + customers• Further maturing of standard• Conformance measurement
Challenges• User buy-in
Solutions• High level of abstraction• Efficient capture mechanism• IP-XACT™ user group!
Jul 8, 2008 8
OCM SDRC
L3
C2C USB SSIARM11 DSP
C55xx GFX DisplaySystem
CAMSystem IVA sDMA
GMPC
Example OMAP-Based SoC CoreExample OMAP-Based SoC Core
System Capture
Derived from : ‘Use of OCP in OMAP2420’, James Aldis, DATE 2005
Challenges• 100s of IP blocks• Multi-Core systems• Multi-Discipline views• Non-disruptive
Solution• Standardization• Efficient capture• High level of
automation• Flexible generators
L4
Case Study : TI have captured 37,500 registers on 1645 TI IP’s.
Jul 8, 2008 9
IP-XACT™ in Bitwise
Use IP-XACT™ as a standardized communication mechanism
Import/Export IP-XACT™ 1.1, 1.2• Extract registers, bitfields, memory maps
Duolog works with TI and other IP-XACT™ IP vendors (e.g. Sonics) to ensure alignment
Jul 8, 2008 10
IP-XACT™ - Gain and Pain
Gain Points• Standardization• IP-XACT™ is the industry standard
Pain Points• Complexity (sub-space Map, Local MM, MM,AddressSpaces/
Blocks etc)• Semantic interpretations• IP-XACT™ conformance mechanism for IP• Corner case requirements that require VE• Conflicting requirements between customers and standards
Recommendations• Get the data out of documents!!• Conformance checking of tools & IP• Keep it simple
Spinner I/O Fabric Generator
Jul 8, 2008 12
What is an I/O fabric?
TestbenchInfrastructure
IO LayerIO LayerIO Layer
•All logic/wiring between Core and Top•All logic and wiring for for pin muxing•All logic and wiring for IO Cell + control•All logic and wiring for boundary Scan•All power isolation logic
I/O ‘Fabric’
•Spinner auto-generates the I/O fabric from a single source specification•We treat the I/O fabric, CORE and Chip top-level as IP deliverables
CORE
CHIP-TOP
SOC CORESOC CORE
Jul 8, 2008 13
Increasing Complexity
TestMUX
FunctionalMUX
CTRL&
CFGBSR Power
Isolation
The complexity per I/O pad is increasingModes, Skew, Power, Reset
Jul 8, 2008 14
GENERATE
CAPTURE
DocsSYSTEM LEVEL ENVIRONMENTSYSTEM LEVEL ENVIRONMENTSYSTEM LEVEL ENVIRONMENT
CONFIG_BLOCKCONFIG_BLOCKCONFIG_BLOCKDEMUXLAYER
CONFIG_BLOCKCONFIG_BLOCKCONFIG_BLOCKDEMUXLAYER
TB_BLOCKTB_BLOCKTB_BLOCK
SystemLevel
Testbench
TB_BLOCKTB_BLOCKTB_BLOCK
SystemLevel
Testbench
SoC TOPSoCSoC TOPTOP
IO FabricRTL SWDFT Validation
VALIDATE
StandardizedTool
Interfaces
Powerful GenerationFramework
ExtensiveCoherency Checking
Import GUI
Spinner Flow
Jul 8, 2008 15
Spinner ‘IP’
Port-level annotatione.g. OutputEnable,
ActiveLow, etc
Component-level annotationFrequencies, PUPD, Electrical
characteristics, etc
Jul 8, 2008 16
IP-XACT™ in Spinner
Spinner uses IP-XACT™ to package all I/O cells• I/O cells• BSR cells• PWR cells
Spinner generates complete I/O layer RTL• Core interface, I/O layers, chip top• All logic + interconnectivity• Spinner also generates IP-XACT™ 1.2
- Annotates instances with power domain information for processing by other tools
• Duolog works with TI + other vendors (e.g. Atrenta) to align on VEs for seamless flow
Jul 8, 2008 17
IP-XACT™ - Gain and Pain
Gain Points• IP-XACT™ is an efficient mechanism for annotating Spinner
information• Vendor collaboration works well
Pain Points• IP-XACT™ 1.2 RTL Implementation is not well defined
- e.g. Ad-hoc connectivity- tie-off, connecting vectors between instances and interfaces
- Require VE to fix – needed alignment between vendors- Duolog have recommended these for IP-XACT™ 1.4
• Who is the V in VE?• Scalability?
Recommendations• IP-XACT™ 1.4 has better RTL implementations• Rename VendorExtensions to VE to save us 50 MB