Dual Buck / uad LDO E522 - elmos. · PDF filee522.52 sdo sck csn fosc tst fs_on on1 on2 chp vdda cmp1 ocp1 cmp2 ocp2 sdi. dual buck / uad ldo e522.52 ... 21 inldo2 22 voldo2 2 nldo2

Dual Buck / Quad LDO E522.52Preliminary Information - Nov 17, 2017

Elmos Semiconductor AG Data Sheet QM-No.: 25DS0171E.00

This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.

1/41

Features

Applications

Typical Application Circuit

� Primary buck converter

Input voltage up to 40V

Output voltage 5.5V

Output current up to 1.5A

� Secondary buck converter

Input voltage up to 6.0V

Output voltage 3.3V

Output current up to 1A

� LDO 1

Input voltage up to 40V

Output voltage 3.3V

Output current up to 350mA

� LDO 2


Output voltage 3.3V


� LDO 3


Output voltage 5V


� LDO 4


Output voltage 1.25V


� Internal power sequencing

� Configurable window / timeout watchdog

General DescriptionSMPS Section: Voltage mode buck converter system.

Both buck converters can be activated via high voltage capa-

ble pins ON1 and/or ON2.

LDO section:

LDO1: High voltage input LDO

LDO2-4: Low voltage input LDOs

Device-deactivation

The device is in low current OFF-state, if inputs ON1 and ON2

are inactive.

Power Monitoring:

Output PGOOD indicates undisturbed operation of all regu-

lators.

Output RSTN provides a reset for the controller in case of

watchdog error or system undervoltage.

Output FS_ON sends a failsafe signal if the watchdog is not

triggered properly.

Internal state registers can be read via SPI interface.

A primary buck converter converts from high voltage down to

a link voltage. A secondary buck converter converts from link

voltage. LDOs provide ripple free supply lines.

Ordering InformationOrdering No.: Temp Range

AmbPackage

E52252A78B -40°C to +105°C QFN48L7

SW1A

VIN1B

UB

VIN1A

CINP_FI3

CCMP1 RCMP1

CCMP2

CVDDA

CCHP

RCMP2

CINP_FI1

LPBO

CINP_FI2 CVIN1_2 CVIN1_1

LPBO

LSBO

CPBO_1

CSBO_1

CO_LDO1

CLDO2_O

CLDO3_O

CPBO_2

CSBO_2

CVIN2_2

CVIN2_1

SW1B

PGND1

FB1

SW2A

VIN2B

VIN2A

SW2B

PGND2

PGND3

FB2

VIN_LDO1

VOUT_LDO1

VIN_LDO2

VOUT_LDO2

SNS_LDO2

CLDO4_O

VIN_LDO3

VOUT_LDO3

SNS_LDO3

VIN_LDO4

VOUT_LDO4

SNS_LDO4

VIO

RSTN

INTN

PGOOD

GND

E522.52

SDO

SCK

CSN

FOSC

TST

FS_ON

ON1

ON2

CHP

VDDA

CMP1

OCP1

CMP2

OCP2

SDI


2/41Elmos Semiconductor AG Data Sheet QM-No.: 25DS0171E.00


Functional Diagram

Pin Configuration

Top View

Note: Not to scale, EP Exposed die pad

SW1A

VIN1BVIN1A

SW1B

PGND1

FB1

SW2A

VIN2B

VIN2A

SW2B

PGND2

PGND3

FB2

VIN_LDO1

VOUT_LDO1

VIN_LDO2

VOUT_LDO2

SNS_LDO2

VIN_LDO3

VOUT_LDO3

SNS_LDO3

VIN_LDO4

VOUT_LDO4

SNS_LDO4

VIO

RSTN

INTN

PGOOD

GND

E522.52

SDO

SCK

CSN

FOSC

TST

FS_ON

ON1

ON2

CHP

VDDA

CMP1

OCP1

CMP2

OCP2

SDI

PrimaryBuck

Converter

Digital Control

Oscillator

Supply Monitor

LVInt

erfac

e

LV In

terfac

e

LDO4

LDO3

LDO2

LDO1

InternalSupply

SecondaryBuck

Converter

ChargePump

HVInterface

ON2

FS_ON

n.c.

VIN_LDO1

n.c.

VOUT_LDO1

CHP

PGOOD

Pin 1

SNS_LDO3

Bottom Side

VOUT_LDO3

VIN_LDO3

SNS_LDO4

VOUT_LDO4

VIN_LDO4

RSTN

INTN

1

EP

41

ON1 40

n.c. 39

VIN1B 38

VIN1A 37

42

43

44

45

46

47

48

20

VIN_LDO221

VOUT_LDO222

SNS_LDO223

CMP224

19

18

17

16

15

14

13

TST

CM

P1

OC

P1

OC

P2

VD

DA

GN

D

FOSC VIO

n.c

.

SW1B

SW1A

FB1

PGN

D1

PGN

D2

PGN

D3

SW2B

2 3 4 5 6 7 8

SDO

9

SDI

10

SCK

11

CSN

12

36 35 34 33 32 31 30 29

SW2A

28

VIN

2B

27

VIN

2A

26

FB2

25

E522.52




Pin Description

Pin Name Type 1) Description

1 TST D_I internally connected; reserved for factory use; connect to GND in the application

2 CMP1 A_IO Primary buck converter loop compensation

3 OCP1 A_IO Primary buck converter over current setting

4 OCP2 A_IO Secondary buck converter over current setting

5 VDDA S Regulated supply output

6 GND S Ground

7 FOSC D_I Input for external buck converter frequency; connect to GND if not used in the applica-tion

8 VIO S Host interface supply

9 SDO D_O SPI serial data output

10 SDI D_I SPI serial data input

11 SCK D_I SPI clock, pull down

12 CSN D_I SPI chip select, low active, pull up

13 INTN D_O Interrupt output, low active, pull up

14 RSTN D_O Reset output, low active, open drain

15 VINLDO4 S input LDO4

16 VOUTLDO4 A_O Output LDO4

17 SNSLDO4 A_I Feedback input LDO4

18 VINLDO3 S Input LDO3

19 VOUTLDO3 A_I Output LDO3


21 VINLDO2 S Input LDO2

22 VOUTLDO2 A_O Output LDO2


24 CMP2 A_IO Secondary buck converter loop compensation

25 FB2 A_I Secondary buck converter feedback input

26 VIN2A S (connect to pin 27) Secondary buck converter input 1

27 VIN2B S (connect to pin 26) Secondary buck converter input 2

28 SW2A A_IO (connect to pin 29) Secondary buck converter output 1

29 SW2B A_IO (connect to pin 28) Secondary buck converter output2

30 PGND3 S (connect to pin 31 and to system ground plane) Power ground 3

31 PGND2 S (connect to pin 30 and to system ground plane) Power ground 2

32 PGND1 S (connect to system ground plane) Power ground 1

33 FB1 A_I Primary buck converter feedback input

34 SW1A HV_A_IO (connect to pin 35) Primary buck converter output pin 1

35 SW1B HV_A_IO (connect to pin 34) Primary buck converter output pin 2

36 n.c.

37 VIN1A HV_S (connect to pin 38) Main supply pin1

38 VIN1B HV_S (connect to pin 37) Main supply pin2

39 n.c.

40 ON1 HV_A_I Primary buck converter control input

41 ON2 HV_A_I Secondary buck converter control input

42 FS_ON HV_D_O fail safe output, open drain, high voltage




Pin Name Type 1) Description

43 n.c.

44 VIN_LDO1 HV_S LDO1 input

45 n.c.

46 VOUT_LDO1 A_O LDO1 output

47 CHP A_IO auxiliary internal supply

48 PGOOD D_O Logical output for indication of proper regulator operation, internal pullup resistor

- EP S Exposed Die Pad

1) A= Analog, D= Digital, HV= High Voltage, I/O= Input/Output, S= Supply




1 Absolute Maximum RatingsStresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; opera-

tion of the device at these or any other conditions beyond those listed in the operational sections of this document is not implied. Exposure to

absolute maximum rated conditions for extended periods may affect device reliability. All voltages with respect to ground. Currents flowing into

terminals are positive, those drawn out of a terminal are negative.

Description Condition Symbol Min Max Unit

Exposed pad voltage VEXP_PAD

-0.15 +0.15 V

Power dissipation

EIA/JESD51 standard; test board according to JEDEC standard 51-7; maximum exposed die pad temperature < 135 °C

PDevice

2.5 W

Ambient temperature Θamb

105 °C

Storage temperature unsoldered device Θstore

125 °C

Storage temperature soldered device Θstore

150 °C

Junction temperature ΘJ

150 °C

Voltage at pins VIN1A, VIN1B VVIN1A,B

-0.3 40 V

Voltage at pin GND VGND

-0.15 +0.15 V

Voltage at pin VIO VVIO

-0.3 6.5 V

Voltage at pin FOSC, SDO, SDI, SCK, CSN, PGOOD, INTN, TST

VFOSC, SDO, SDI,

SCK, CSN, PGOOD,

INTN, TST

-0.3 VVIO

+0.3 V

Current at pin FOSC, SDO, SDI, SCK, CSN, PGOOD, INTN, TST

IFOSC, SDO, SDI,

SCK, CSN, PGOOD,

INTN, TST

-5 +5 mA

Voltage at output pins SW1A and SW1B VSW1A,B

-1 VVIN1A,B

V

Voltage at feedback pin FB1 VFB1

-0.3 6.5 V

Voltage at pin ON1 VON1

-0.3 40 V

Voltage at pin OCP1 VOCP1

-0.3 VDDA+0.3 V

Voltage at pin CMP1 VCMP1

-0.3 VDDA+0.3 V

Current at pin ON1 ION1

-5 5 mA

Current at pin OCP1 IOCP1

-5 5 mA

Current at pin CMP1 ICMP1

-5 5 mA

Voltage at pin PGND1 VPGND1

-0.15 +0.15 V

Voltage at input pins VIN2A and VIN2B VIN2A,B

-0.3 6.5 V

Voltage at output pins SW2A and SW2B

static condition (V__SW2A,B may go down to -1V temporarily during operation)

VSW2A,B

-0.3 VIN2A,B

V

Voltage at feedback pin FB2 VFB2

-0.3 VIN2A,B

V

Voltage at pin ON2 VON2

-0.3 40 V

Voltage at pin OCP2 VOCP2

-0.3 VDDA+0.3V V

Voltage at pin CMP2 VCMP2

-0.3 VDDA+0.3V V

Current at pin ON2 ION2

-5 5 mA

Current at pin OCP2 IOCP2

-5 5 mA

Current at pin CMP2 ICMP2

-5 5 mA




1) According to AEC-Q 100-002, Human Body Model, 1.5kΩ resistance, 100pF capacitance.

2) According to AEC-Q 100-011, Charged Device Model, pulse rise time (10% to 90%) <400ps, 1Ω resistance.

2 ESD Protection


ESD HBM protection at pin VIN1A, VIN1B, VINLDO1, ON1, ON2

HBM 1) ±4 - kV

ESD HBM, all other pins HBM 1) ±2 - kV

ESD on IC Level CDM 2) ±0.5 - kV



-0.15 +0.15 V


-0.15 +0.15 V

Voltage at pin VIN_LDO1 VVIN_LDO1

-0.3 40 V

Voltage at pin VOUT_LDO1 VVOUT_LDO1

-0.3 6.5 V

Power dissipation in LDO1 PLDO1

560 mW

Voltage at pins VIN_LDO2-4 VVIN_LDO2-4

-0.3 6.5 V

Voltage at pins VOUT_LDO2-4 VVOUT_LDO2-4

-0.3 6.5 V

Voltage at pins SNS_LDO2-4 VSNS_LDO2-4

-0.3 VOUT_LDO2-4

+0.3 V

Current at pins SNS_LDO2-4 ISNS_LD2-4

-5 +5 mA

Voltage at pin RSTN VRSTN

-0.3 6.5 V

Current at pin RSTN IRSTN

-5 mA

Current at pin RSTN in active state output low IRSTN_act

+5 mA

Voltage at pin FS_ON VFS_ON

-0.3 40 V

Current at pin FS_ON IFS_ON

-5 mA

Current at pin FS_ON in active state output low IFS_ON_act

+5 mA




Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified.

All voltages are referred to ground (0V). Currents flowing into the circuit have positive values. The first electrical potential con-

nected to the IC must be GND. (If not specified specify timing sequence of electrical contacts.)

3 Recommended Operating Conditions

Description Condition Symbol Min Typ Max Unit

Supply voltage at pins VIN1A,B VVIN1A,B

8 12 30 V

Junction temperature during operation < 1000 h Θ

J_150150 °C

Junction temperature during operation < 9000 h Θ

J_105105 °C

Input low level at pin TST operation in application; connect to GND V

TST,INL100 mV

Blocking capacitor at Pin VDDA CVDDA

470 nF

Blocking capacitor at Pin CHP CCHP

1 µF

First external input capacitor for primary buck converter setup parameter C

VIN1_140 µF

Second external input capacitor for pri-mary buck converter setup parameter C

VIN1_2100 1000 nF

External output inductance for primary buck converter

setup parameter (typical input volt-age 12V; outputvoltage 5.5V) L

PBO22 µH

First external output capacitor for primary buck converter

setup parameter (typical input volt-age 12V; outputvoltage 5.5V) C

PBO_147 µF

Second external output capacitor for primary buck converter

setup parameter (typical input volt-age 12V; outputvoltage 5.5V) C

PBO_25.6 µF

Equivalent serial resistance of external output capacitor for primary buck con-verter 1)

setup parameter RESR_C_PBO

50 mΩ

Compensation network for primary buck converter consisting of C

CMP1 and

RCMP1

in seriessetup parameter C

CMP1470 nF

Compensation network for primary buck converter consisting of C

CMP1 and

RCMP1

in seriessetup parameter R

CMP12200 Ω

First external input filter capacitor setup parameter CINP_FI1

100 µF

Second external input filter capacitor 2) setup parameter C

INP_FI2100 µF

Third external input filter capacitor setup parameter CINP_FI3

100 nF

External input filter inductor setup parameter LINP_FI

15 µH

First external input capacitor for secondary buck converter setup parameter C

VIN2_140 µF

Second external input capacitor for sec-ondary buck converter setup parameter C

VIN2_2100 1000 nF

External output inductance for secondary buck converter

setup parameter (typical input volt-age 5.5V; outputvoltage 1.7V) L

SBO10 µH

First external output capacitor for sec-ondary buck converter

setup parameter (typical input volt-age 5.5V; outputvoltage 1.7V) C

SBO_122 µF

Second external output capacitor for secondary buck converter

setup parameter (typical input volt-age 5.5V; outputvoltage 1.7V) C

SBO_25.6 µF

1) Smaller ESR may cause very low phase margins.

2) If CINP_FI2 is applied, CVIN1 can be omitted.




1) Smaller ESR may cause very low phase margins.


Equivalent serial resistance of external output capacitor for secondary buck converter 1)

setup parameter(typical input voltage 5.5V; output-voltage 1.7V)

RESR_C_SBO

50 mΩ

Compensation network consisting of C

CMP2 and R

CMP2 in series setup parameter C

CMP2100 nF

Compensation network consisting of C

CMP2 and R

CMP2 in series setup parameter R

CMP24700 Ω





Supply voltage at pins VIN1A,B for valid-ity of specified parameters setting parameter V

VIN1A,B5.2 14 30 V

Supply current at pins VIN1A,B in active mode

Sum of currents at pins VIN1A, VIN1B, VIN_LDO1; V

VIN1A,B=14V

IVIN_act

18 mA

Supply current in sleep mode with all regulators off (LDO1 disabled via SPI)

Sum of currents at pins VIN1A, VIN1B, VIN_LDO1;7V ≤ V

VIN1A,B≤15V; no

pullup/down current at pins 2)

IVIN_slp

20 30 µA

Supply current in sleep mode with all regulators off except LDO1 on (ao);no output current out of pin VOUT_LDO1

Sum of currents at pins VIN1A, VIN1B, VIN_LDO1;V

VIN1A,B ≤ 15V;

7V ≤ VVIN_LDO1

≤ 15V;LDO1 on (ao);no pullup/down cur-rent at pins 2)

IVIN_slp_ao

30 60 µA

Supply current sleep mode with all reg-ulators off except LDO1 programmed to be always on (ao)measured with maximum output cur-rent at pin VOUT_LDO1, not production tested

I(VIN1A)+I(VIN1B)+ I(VIN_LDO1)-I(VOUT_LDO1);V

VIN1A,B ≤ 15V;

7V ≤ VVIN_LDO1

≤ 15V;I

VOUT_LDO1_MAX= -25mA

LDO1 on (ao);no pullup/down cur-rent at pins 2) 3)

IVIN_slp_ao_imax

75 µA

Low voltage supply output in active mode

active mode, no exter-nal DC load V

VDDA3.2 3.35 3.5 V

Low voltage supply output in sleep mode

sleep mode, no exter-nal DC load V

VDDA_slp3.1 3.31 3.5 V

Power low threshold supply falling VVDDA_UV

2.45 2.75 V

Difference of rising and falling thresh-old

1) VVDDA_UVhys

0.4 V

external blocking capacitor at pin VDDA CVDDA

220 470 1000 nF

auxiliary supply voltage at pin CHP VCHP

7 7.5 8 V

external blocking capacitor at pin CHP CCHP

220 nF

Supply voltage at pad VIO setting parameter VVIO

2.3 5.5 V

(VVIN1A,B

= +5.2V to +30V, TAMB

= -40°C to +105°C, unless otherwise noted. Typical values are at VVIN1A,B

= +14V and TAMB

= +25°C.

Positive currents flow into the device pins.)

1) Defined by design. Not subject to production test.

2) Θamb

≤ 35 °C

3) Information Parameter. Not subject to production test.

4 Electrical Characteristics

4.1 Power Supply





Minimum time step for power sequenc-ing t

PWRS512 µs

Multiplier for power sequencing time step m

PWRS2 2 2


junction temperature for shut down TJ,shutdown

150 170 185 °C

junction temperature for recovery from shut down T

J,recover120 140 155 °C

junction temperature for warning of shut down T

J,warn120 140 155 °C


frequency of internal oscillator for derivation of buck converter switching clock according to frequency divider settings

fCLK

7.3 8 8.5 MHz

input high level for application of external clock V

FOSC_IH0.75 V

VIO

input low level for application of external clock V

FOSC_IL0.25 V

VIO

Pull down resistor at Pin FOSC RFOSC_PD

60 125 190 kΩ

frequency of externally applied clock fOSC_ext

0.2 0.8 MHz

duty cycle of externally applied clock setting parameter DCLK_ext

30 50 70 %

filter time for external clock surveillance tFOSC_filt

50 100 µs


main supply and primary buck converter input voltage range setting parameter VR

PB_I5.2 14 30 V

factory programmed output voltage 5.5V < VVIN1A,B

< 30V VPB_O

5.5V

output voltage deviation from programmed value

5.5V < VVIN1A,B

< 30V; pin FB1 connected to output capacitor

VOTOL_PB

-3 3%

average output current range overall power dissipa-tion within limit I

PB_O-1.5 A

output voltage at pin OCP1 IOCP1

=-175 µA VOCP1

1.20 1.26 1.32 V

custom over current limitationsetting by current from pin OCP1 to ground

IPB_OC

7000 10000 13000 IOCP1

default over current limitation pin OCP1 open IPB_OC_def

-3 -2.5 -2 A

switch on resistance high side switch of primary buck converter RDS_ON

PB_HS0.3 0.65 Ω

voltage regulation loop transconduct-ance 1)

I(CMP1)=0V(CMP1)=0.3 ... 2.2 V G

m_PB1.5 2,0 2.5 mS

converter operating frequency setup parameter fOP_PB

400 kHz

soft start slew rate SRPB_SOS

4 V/ms

control input high voltage VIH_ON1

2.4 V

4.2 Operation States

4.3 Buck Converter Oscillator

4.4 Primary Buck Converter

1) Internal sawtooth voltage is between 0.3 V and 2.2 V

1) Guaranteed by design. Not subject to production test.





Secondary buck converter input voltage range (pins VIN2A,B) setting parameter V

SB_I3.5 5 6 V

factory programmed output voltage 3.5V < VSB_I

< 6V VSB_O

3.3 V

output voltage deviation from programmed value

3.5V < VSB_I

< 6V; pin FB2 connected to out-put capacitor

VOTOL_SB

-90 90 mV

average output current overall power dissipa-tion within limit I

SB_O-1.0 A

output voltage at pin OCP2 IOCP2

= -125 µA VOCP2

1.20 1.26 1.32 V

custom over current limitationsetting by current from pin OCP2 to ground

ISB_OC

7000 10000 13000 IOCP2

magnitude of default over current limitation pin OCP2 open I

SB_OC_def-2.3 -1.8 -1.3 A

switch on resistance high side switch of secondary buck converter RDS_ON

SB_HS0.36 0.65 Ω

switch on resistance low side switch of secondary buck converter RDS_ON

SB_LS0.18 0.3 Ω

voltage regulation loop transconductance 1) I(CMP2)=0 G

m_SB1.5 2.0 2.5 mS

converter operating frequency V(CMP2)=0.3 ... 2.2 V fOP_SB

400 kHz

soft start slew rate information param-eter SR

SB_SOS4 V/ms

control input high voltage VIH_ON2

2.4 V

control input low voltage VIL_ON2

0.95 V

pull down current at pin ON2 IPD_ON2

15 40 µA

control input resistance VI_ON2

= 28V RI_ON2

130 kΩ

debounce time for pin ON2 VI_ON2

< 3V; informa-tion parameter t

ON2,deb100 µs

Discharge current in Sleep mode ISB_PD_SLEEP

15 30 mA

Minimum Capacitance at the compensation network to pass internal start up self test

V(FB2) > 1V CCMP2MIN

300 600 1000 pF

Minimum pulse width without overcurrent

tMinimum Pulse

Width

100 150 200 ns


control input low voltage VIL_ON1

0.95 V

control input pull down current VI_ON1

= 28V IPD_ON1

15 40 µA

control input resistance VI_ON1

< 3V; informa-tion parameter R

I_ON1130 kΩ

Discharge current in Sleep mode V(FB1) > 1V IPB_PD_SLEEP

15 30 mA

debounce time for pin ON1 tON1,deb

100 µs

Minimum Capacitance at the compensation network to pass internal start up self test

CCMP1MIN

300 600 1000 pF

Minimum pulse width without overcurrent

tMinimum Pulse

Width

100 150 200 ns

1) Internal sawtooth voltage is between 0.3 V and 2.2 V

1) Guaranteed by design. Not subject to production test.

4.5 Secondary Buck Converter




4.6 LDO1


input voltage information parameter V

VIN_LDO130 V

factory programmed output voltageV

VIN_LDO1 ≥

VVOUT_LDO1

+ V

DropLDO1

VVOUT_LDO1

3.3 V

output voltage deviation from pro-grammed value 4V < V

VIN_LDO1 < 20V V

OTOL_LDO1-2 2 %

output voltage drop IOUT_LDO1

=-320mA VDropLDO1

1 V

output currentinformation param-eter; power dissipation within limit

IOUT_LDO1

-350 -250 mA

over current thresholdV

VIN_LDO1 ≥

VVOUT_LDO1

+ V

DropLDO1

IOC_LDO1

-700 -450 -370 mA

output voltage deviation from pro-grammed value in low power mode

4V < VVIN_LDO1

< 20V;I

OUT_LDO1 ≥ -20mA V

OTOL_lp_LDO1-2 2 %

output current in low power stateinformation param-eter; power dissipation within limit

IOUT_lp_LDO1

-55 -50 mA

over current threshold in low power state

VVIN_LDO1

≥ V

VOUT_LDO1 +

VDropLDO1

IOC_lp_LDO1

-140 -90 -60 mA

regulator output discharge current in off state V

VOUT_LDO1 > 1V I

disc_LDO115 30 mA

output voltage threshold for indication of regulator on output voltage rising VLDO1

VOUT_

off_r

0.3 1 V

output voltage threshold for indication of regulator off output voltage falling VLDO1

VOUT_

off_f

0.1 0.5 V

output blocking capacitor CO_LDO1

10 120 µF

ESR of output blocking capacitor RESR_C_O

10 500 mΩ


input voltage information parameter V

VIN_LDO2-41.2 6 V

factory programmed output voltage of LDO2

VVIN_LDO2

≥ V

VOUT_LDO2 +

VDropLDO2

VVOUT_LDO2

3.3 V


VVIN_LDO3

≥ V

VOUT_LDO3 +

VDropLDO3

VVOUT_LDO3

5 V


VVIN_LDO4

≥ V

VOUT_LDO4 +

VDropLDO4

VVOUT_LDO4

1.25 V

LDO2-4 output voltage deviation from programmed value V

OTOL_LDO2-4-2 2 %

output current of a single LDOinformation param-eter; power dissipation within limit

IOUT_LDO2-4

-450 -250 mA

output voltag drop IOUT_LDO2-4

= -350mA VDropLDO2-4

0.35 V

over current threshold and limitation of a single LDO

VVIN_LDO2-4

- V

VOUT_LDO2-4 ≥ 1V I

OC_LDO2-4-700 -600 -500 mA

regulator output discharge current in off state V

VOUT_LDO2-4 > 1V I

disc_LDO2-415 30 mA

4.7 LDO2-4





over voltage primary buck converterrefered to measured value of V

PB_O; voltage

risingV

PB_O_OV1.05 1.08 1.11 V

PB_O

under voltage primary buck converterrefered to measured value of V

PB_O; voltage

fallingV

PB_O_UV0.89 0.92 0.95 V

PB_O

primary buck converter filter time for over and under voltage recognition (bi-directional)

1) tPB_OVUV_filt

300 µs

over voltage secondary buck converterrefered to measured value of V

SB_O; voltage

risingV

SB_O_OV1.05 1.08 1.11 V

SB_O

under voltage secondary buck converterrefered to measured value of V

SB_O; voltage

fallingV

SB_O_UV0.89 0.92 0.95 V

SB_O

secondary buck converter filter time for over and under voltage recognition (bi-directional)

1) tSB_OVUV_filt

300 µs

over voltage LDO1refered to measured value of V

VOUT_LDO1;

voltage risingV

LDO1_O_OV1.05 1.08 1.11 V

VOUT_

LDO1

under voltage LDO1refered to measured value of V

VOUT_LDO1;

voltage fallingV

LDO1_O_UV0.89 0.92 0.95 V

VOUT_

LDO1

LDO1 filter time for over and under volt-age recognition (bidirectional)

1) tLDO1_OVUV_filt

100 µs

over voltage LDO2-4refered to measured value of V

VOUT_LDO2-4;

voltage risingV

LDO2-4_O_OV1.05 1.08 1.11 V

VOUT_

LDO2-4

under voltage LDO2-4refered to measured value of V

VOUT_LDO2-4;

voltage fallingV

LDO2-4_O_UV0.89 0.92 0.95 V

VOUT_

LDO2-4

LDO2-4 filter time for over and under voltage recognition (bidirectional)

1) tLDO2-4_OVUV_filt

100 µs

under voltage threshold at pins VIN1A,B, voltage falling voltage falling V

VIN1A,B_UV_vf3.4 3.6 3.8 V

under voltage recovery threshold at pins VIN1A,B, voltage rising voltage rising V

VIN1A,B_UV_vr4.25 4.5 4.7 V

under voltage threshold at pins VIN2A,B, voltage falling voltage falling V

VIN2A,B_UV_vf2.65 2.85 3.15 V

under voltage recovery threshold at pins VIN2A,B, voltage rising voltage rising V

VIN2A,B_UV_vr2.85 3.05 3.35 V

under voltage at pin VIO VVIO_UV

1.9 2.0 2.1 V

debounce time for under voltage at pin VIO (bidirectional)

1) tVIO_deb

100 µs

timeout for under voltage at pin VIO 1) tVIO_tout

500 ms


output voltage threshold for indication of regulator on output voltage rising V

LDO2-4VOUT_

off_r

0.3 1 V

output voltage threshold for indication of regulator off output voltage falling V

LDO2-4VOUT_

off_f

0.1 0.5 V

output blocking capacitor for each sin-gle output C

O_LDO2-42 µF

ESR of output blocking capacitor ESRC_LDO2-4

0.01 10 Ω

4.8 Monitoring

1) Defined by design. Not subject to production test.





supply voltage threshold for activation of internal charge pump voltage falling V

VIN1A,B_CHP_on7.8 8.4 8.9 V

supply voltage threshold for de- activa-tion of internal charge pump voltage rising V

VIN1A,B_CHP_off8.6 9.1 9.7 V

under voltage at pin CHP VCHP_UV

5.9 6.2 6.6 V

Low Level Output Voltage IPGOOD

=2mA VPGOOD,OUTL

0.4 V

internal pull up resistor RPGOOD_PU

25 50 75 kΩ


Minimum watchdog time base impor-tant for safe trigger area t

WD,PER,MIN0.85 t

WD,PER

Maximum watchdog time base impor-tant for safe trigger area t

WD,PER,MAX1.15 t

WD,PER

First open window open window after RSTN is released t

WD,FOW230 290 ms

Watchdog reset time supplier programmed tWD,RSTN

4 6 ms

disable time for LDOs supplier programmed tWD,LDO,OFF

100 ms


High level input voltage at pin CSN VCSN,INH

0.7 VVIO

Low level input voltage at pin CSN VCSN,INL

0.3 VVIO

High level input current at pin CSN VCSN

= VVIO

ICSN,LEAK

-1 0 1 µA

Pull up resistor at pin CSN active mode RCSN,PU

70 180 kΩ

High level input voltage at pin SCK VSCK,INH

0.7 VVIO

Low level input voltage at pin SCK VSCK,INL

0.3 VVIO

Pull down resistor at pin SCK RSCK,PD

70 180 kΩ

High level input voltage at pin SDI VSDI,INH

0.7 VVIO

Low level input voltage at pin SDI VSDI,INL

0.3 VVIO

Low level output voltage at pin SDO ISDO

= 2mA VSDO,OUTL

0.4 V

High level output voltage at pin SDO ISDO

= -2mA VSDO,OUTH

VVIO

- 0.4 V


Serial clock cycle1) SCK, V

VIO ≥ 3V

2) tSCYC

500 ns

SCK "H" pulse width1) SCK2) t

SHW250 ns

SCK "L" pulse width1) SCK2) t

SLW250 ns

data setup time (WR) 1) SDI tSDS

50 ns

data hold time 1) SDI tSDH

50 ns

access time 1) SDO tACC

100 ns

output enable time 1) SDO tOE

250 ns


Low level output voltage at pin RSTN IRSTN

= 2mA VRSTN,OUTL

0.4 V

4.9 Watchdog; pin RSTN

4.10 SPI communication; pins SCK, SDI, SDO, CSN





output low level at pin INTN IINTN

= 2mA VINTN,OUTL

0.4 V

pull up resistor at pin INTN RINTN,PU

70 125 180 kΩ


Low level output voltage at pin FS_ON IFS_ON

= 2mA VFS_ON,OUTL

0.4 V


output disable time 1) SDO tOD

250 ns

SCK-CSN 1) CSN tSCC

250 ns

CSN "H" pulseMinimum time between two consecu-tive SPI accesses

1) CSN tCHW

5 us

CSN-SCK time 1) CSN tCSS

125 ns

1) not ATE tested

2) VVIO

= 5V, fSPI

= 2 MHz

4.11 Interrupt; pin INTN

4.12 Fail Safe; pin FS_ON




5 Functional Description

5.1 Power Supply

Main supply (VIN1A, VIN1B)

Pins VIN1A and VIN1B provide the main supply voltage of the IC. It feeds an internal voltage regulator in order to supply the

internal building blocks. For VVIN1A,B_UV_vf

< VVIN1A,B

< VVIN1A,B_UV_vr

the IC is operable, however, parameter specifications may not

be fully met.

Both pins are connected internally and must be connected together externally also. The supply at pins VIN1A and VIN1B must

be reverse polarity protected externally. Supply the IC with an external filter in order to avoid startup failures due to properties

of the external rectifier diode or even IC destruction due to a too fast rising input voltage.

Regulated Supply (VDDA)

The IC has an internal voltage regulator based on a bandgap reference voltage which feeds the low voltage supply for internal

blocks.Pin VDDA is the regulator output. It must be buffered with an external blocking capacitor at pin VDDA. No additional

external components must be connected to this supply pin.

Host Interface Supply (VIO)

The host interface pins have to be supplied via pin VIO, in order to ensure the correct logic signal levels. Pin VIO shall be con-

nected to the regulator output that feeds the contoller interface.

Auxiliary Internal Supply (pin CHP)

A charge pump circuit provides an auxiliary supply voltage for the LDOs 2-4 in case the supply voltage is lower than the typical

automotive supply case (see VVIN1A,B_CHP_on

). Otherwise the charge pump is inactive and the auxiliary supply is derived from sup-

ply VIN1A, VIN1B. This auxiliary supply needs an external blocking capacitor at pin CHP. No additional external components

must be connected to this pin.

The following paragraphs describe the functionality and parameters that have been set by the supplier.

LDO1 Always On

LDO1 is programmed to be always on. It has a reduced current drive capabilitiy in power down mode.

Power Up Sequence

The sequence of regulator startup and the time steps between regulator starts are set by the supplier to codes 011 („Table 1.

Parallelization and Power Up Sequencing Table“) and 0001 („4.2 Operation States“) respectively. LDOs 2-4 are started in parallel

and operate independently..

LDO Discharge

The LDOs are programmed to be discharged in off state (power down mode with inputs ON1/2 low or SPI command).

RSTN Low

The reset output RSTN remains inactive if an under voltage occurs at the output of LDO1 and in case of under voltage at the

interface supply VIO.

Watchdog Off for LDOs

The LDOs remain active in case of a watchdog trigger reset.

Over Temperature Shut Off

An over temperature warning threshold is monitored and can be read from a register. The IC performs an over temperature

shut off if a temperature limit is reached.

Buck Converter Frequency

Primary and secondary buck converters operate at the same frequency.

5.2 Supplier Settings




ON1/2 Transition

A low level at the ON1/2 pins is regarded active high after power on, as long as these pins have not changed to a high level yet,

i.e. the IC is forced to start in active mode.

Supply Application

If the main supply at pins VIN1A and VIN1B is applied, an internal regulator starts to deliver a 3.3V supply, which is blocked ex-

ternally at pin VDDA. The control circuitry is reset by a power on reset signal and all supplier settings are activated. Pins ON1

and ON2 determine the subsequent IC states.

Power Down

If neither of the regulators is requested to be active (pins ON1 and ON2 low), the IC is in power down state with minimum cur-

rent consumption from pins VIN1A,B. LDO1 remains active all the time.

The main supply voltage at VIN1A,B must be higher than 7V in order to maintain the power down current consumption. If the

main supply is lower, additional internal circuitry will be activated in order to report the failure with increased current con-

sumption.

Digital Interface in Power Down

The subsequent table lists the functionality of the digital interface in power down state.

System Activation

If inputs ON1 or ON2 are in on-state, the respective buck converter starts operation immediately after activation of all auxil-

iary blocks in the IC.

If inputs ON1 and ON2 are set to on-state at the same instant, the secondary buck converter starts operation immediately af-

ter the primary buck converter has reached its nominal output voltage.

After power on the ON1 and ON2 pin values are assumed to have high level as long as no actual high level is applied to the pin.

For a transition to the power down state the pins need a voltage change from high to low level.

If the buck converters which are requested to operate have reached their nominal output voltage with all under voltage flags

inactive, the LDOs 2-4 are enabled. An eventually occuring over voltage condition will have no impact on the startup sequence.

A delay of tPWRS

* mPWRS

is inserted between full operation of each regulator and the activation of the subsequent one („4.2 Op-

eration States“).

Output PGOOD is set to high level, if all requested buck converters and voltage regulators operate with all over- and under-

voltage flags inactive.

Regulator LDO1 is active all the time with different output current capability in active and in low power mode. Activation of

the buck converters is not necessary for its operation.

5.3 Operation States

Output FunctionalityRSTN no active low levelINTN no active output level; internal pull up to VIO supplyPGOOD no active low level; internal pull up to VIO supplyFS_ON no active low level except in case of under voltage at the main supply VIN1A/B

CSN Pull up and SPI interface de- activated in sleep mode an in case of under voltage at interface sup-ply VIO

SCK pull down; SPI interface de- activated in case of under voltage at interface supply VIOSDI SPI interface de- activated in case of under voltage at interface supply VIOSDO no active output levelFOSC pull downTST pull downON1/2 pull down




Power Sequencing

The subsequent table lists the power sequencing steps. Row number 3 is valid for this product.

If only one of the buck converters is activated, only this one is prerequisite for activation of the LDO section.

For power down sequencing the power up sequencing is used in reverse direction. If the normal delay time is not sufficient to

guarantee that the previous regulator output voltage is close to zero, switching off the next regulator is further delayed until

this condition is met.

Delay Time

The delay time between all power sequencing steps is set with a factor of mPWRS

of the minimum delay time tPWRS

.

For the parallel operation of LDOs there is the minimum delay time tPWRS

between switching on the LDOs.

All regulators will continue to operate in case of a watchdog reset.

Regulators may be de- and re- activated via SPI. The power up sequencing is modified accordingly in this case.

On re- activation of regulators pin PGOOD will be set to low level temporarily for the startup time of the re- activated regulator

in order to indicate a successful state change. All other active regulators maintain their operation status.

Buck Converter Clock

The buck converters are controlled by the same internal oscillator clock. Both converters operate phase synchronously.

Converters can be controlled via an external clock signal at pin FOSC.

Over Current Limitation

All buck converters and LDOs limit their output current by default.

The buck converter over current limits can be set to a different value by resistors between pins OCP1, OCP2 and ground.

Temperature Surveillance

The junction temperature of the IC is monitored in active mode.

If the temperature reaches the over temperature warn threshold TJ,warn a warning is signaled via interrupt pin INTN and can

be read via SPI.

In case the temperature reaches the over temperature shutdown threshold TJ,shutdown and the respective programming op-

tion is set, all regulators are shut off in predefined power down sequencing. This includes LDO1 in all application scenarios.

In case of over temperature shut down the failsafe pin FS_ON is pulled down and the over temperature shutdown flag bit in

register FS_ON status register is set.

As soon as the IC has reached its recovery temperature TJ,recover, the previous operation state is activated again.

Number Option Step0 Step1 Step2 Step3 Step4

3 LDOs 2, 3, 4 all in parallel

bucks on; LDO 1 on; buck converters indicate normal operation

LDOs 2, 3 & 4

Table 1. Parallelization and Power Up Sequencing Table




5.4 Buck Converter Oscillator

An internal oscillator provides the clock for the whole IC. The switching clock for the buck converters is derived from it by fre-

quency division. The buck converter operating frequency is set to 400 kHz.

Alternatively an external clock can be applied at pin FOSC. Pin FOSC should be connected to GND if not used in the application.

The two buck converters operate at the same clock frequency.

CLK

8 MHz N [10..40]

F 1N

Monitor

FOP_PB

FOP_SB

12

FOSC

Figure 1. Selection of buck converter frequency

5.5 Primary Buck Converter

Figure 2. Block Schematic of Primary Buck Converter




Topology

The primary buck converter is supplied by the externally reverse polarity protected main supply voltage at pins VIN1A and

VIN1B. Both pins are connected internally and must be connected together externally also.

An internal high side switch delivers current to an external inductor and an external diode provides a current path between

ground and converter outputs SW1A and SW1B. Both pins are connected internally and must also be connected together ex-

ternally. The feedback pin FB1 must be connected to the regulator output capacitor. The ground pin PGND1 must be connected

to the system ground plane.

The converter is activated with a high level at pin ON1. An external resistor between pin OCP1 and ground sets the over cur-

rent limit.

Pin CMP1 is the interface for external components for loop compensation.

The output voltage is factory programmed. Output over and under voltage and over current are monitored and stored in a

register.

A fast external freewheeling diode with a reverse recovery time of <50ns is necessary. A Schottky type is recommended.

Soft start is implemented for a typical startup slope.

The converter is typically driven by an internally generated clock. Alternatively an external clock can be applied to pin FOSC.

Since loss of the feedback connection and loss of the compensation network may cause damage not only to the IC but also to

other circuitry two safety functions are implemented.

During startup an internal self test is performed to ensure that the compensation network is connected. The start up is can-

celled if the CMP1 pin has a short to VDDA or the connected capacitance is smaller than the threshold value.

Additionially, the buck converter does not switch if the FB1 pin is ripped off. A small current forces FB1 to VIN1A/B until FB1

reaches approximatly 103% of the expected output voltage.

The buck converter will continue operation even if there is no diode connected between ground and converter outputs SW1A

and SW1B. This operation mode, however, bears the risk of damaging the IC. Thus the customer must measure a sufficiently

low voltage drop across the external diode in an end of line test on the final board.

Primary Buck Converter Registers

Register Name Address DescriptionPB Status 0x01 Primary Buck Converter Status RegisterPB Control 0x02 Primary Buck Converter Control RegisterPB INT 0x31 Primary Buck Interrupt register




PB Status (0x01) MSB LSB

Content - - - VIN_UV OC OV UV ONReset Value 0 0 0 0 0 0 0 0Access R R R R R R R R

Bit Description

VIN_UV : This Bit is set to '1' when the converter is switched on and an undervoltage on the con-verter input voltage is detected.OC : This Bit is set to '1' when the converter is switched on and an overcurrent is detected.OV : This Bit is set to '1' when the converter is switched on and an overvoltage is detected.UV : This Bit is set to '1' when the converter is switched on and an undervoltage is detected.ON : This bit represents the state of the pin ON1.Bit is set to '1' when pin ON1 is high and '0' when pin ON1 is low.

PB Control (0x02) MSB LSB

Content - - EN_INT2 EN_INT1 EN_OC EN_OV EN_UV -Reset Value 1 0 1 1 1 1 1 0Access R/W R/W R/W R/W R/W R/W R/W R

Bit Description

EN_INT2 : interrupt enable for INT20..disabled1..enabledEN_INT1 : interrupt enable for INT10..disabled1..enabledEN_OC : interrupt enable for overcurrent0..disabled1..enabledEN_OV : interrupt enable for overvoltage0..disabled1..enabledEN_UV : interrupt enable for undervoltage0..disabled1..enabled

Register PB INT (0x31) MSB LSB

Content - - INT2 INT1 OC OV UV -Reset Value 0 0 0 0 0 0 0 0Access R R R/W R/W R/W R/W R/W R

Bit Description

INT2 : This bit indicates an internal buck start failure.INT1 : This bit indicates an internal buck start failure.OC : This Bit is set to '1' when a overcurrent condition occured and cleared by writing a '1' to the bit.OV : This Bit is set to '1' when a overvoltage condition occured and cleared by writing a '1' to the bit.UV : This Bit is set to '1' when a undervoltage condition occured and cleared by writing a '1' to the bit.

Table 2. Primary Buck Converter Status Register

Table 3. Primary Buck Converter Control Register

Table 4. Primary Buck Interrupt register




5.6 Secondary Buck Converter

Figure 3. Block Schematic of Secondary Buck Converter

Topology

The secondary buck converter is typically supplied by the primary buck converter output voltage at pins VIN2A and VIN2B. Both

pins are connected internally and must be connected externally.

An internal high side switch delivers current to an external inductor and an internal low side switch provides a current path

between ground and converter outputs SW2A and SW2B. Both pins are connected internally and must be connected togeth-

er externally also. The feedback pin FB2 shall be connected to the regulator's output capacitor. The ground pins PGND2 and

PGND3 must be connected to the system ground plane.

An external resistor between pin OCP2 and ground sets the over current limit.

Pin CMP2 is the interface for external components for loop compensation.

The output voltage is factory programmed. Output over and under voltage and over current are monitored and stored in a

register.

Soft start is implemented for a typical startup slope.

In a typical configuration the secondary buck converter is supplied by the primary buck converter and starts operation after

the primary buck converter has reached its nominal output voltage. If the primary buck converter is not used and the second-

ary buck converter is activated with a high level at pin ON2 alone, a separate input source is expected and operation starts, if

the input voltage is higher than the input under voltage threshold.

The converter is driven by the same internally generated clock which is used for the primary buck converter.

Since loss of the feedback connection and loss of the compensation network may cause damage not only to the IC but also to

other circuitry two safety functions are implemented.

During startup an internal self test is performed to ensure that the compensation network is connected. The start up is can-

celled if the CMP2 pin has a short to VDDA or the connected capacitance is smaller than the threshold value.

Additionially, the buck converter does not switch if the FB2 pin is ripped off. A small current forces FB2 to the VIN2A/B input

until FB2 reaches the over voltage threshold.




Secondary Buck Converter Registers

Register Name Address DescriptionSB Status 0x03 Secondary Buck Converter Status RegisterSB Control 0x04 Secondary Buck Converter Control RegisterSB INT 0x32 Secondary Buck Interrupt Register

Register SB Status (0x03) MSB LSB

Content - - - VIN_UV OC OV UV ONReset Value 0 0 0 0 0 0 0 0Access R R R R R R R R

Bit Description

VIN_UV : This Bit is set to '1' when the converter is switched on and an undervoltage on the con-verter input voltage is detected.OC : This Bit is set to '1' when the converter is switched on and an overcurrent is detected.OV : This Bit is set to '1' when the converter is switched on and an overvoltage is detected.UV : This Bit is set to '1' when the converter is switched on and an undervoltage is detected.ON : status pin ON2This bit represents the status of pin ON2.Bit is set to '1' when pin ON2 is high and '0' when pin ON2 is low.

Register SB INT (0x32) MSB LSB

Content - - INT2 INT1 OC OV UV -Reset Value 0 0 0 0 0 0 0 0Access R R R R R/W R/W R/W R

Bit Description

INT2 : This bit indicates an internal buck start failure.INT1 : This bit indicates an internal buck start failure.OC : This Bit is set to '1' when a overcurrent condition occured and cleared by writing a '1' to the bit.OV : This Bit is set to '1' when a overvoltage condition occured and cleared by writing a '1' to the bit.UV : This Bit is set to '1' when a undervoltage condition occured and cleared by writing a '1' to the bit.

Register SB Control (0x04) MSB LSB

Content EN_CDIR - EN_INT2 EN_INT1 EN_OC EN_OV EN_UV -Reset Value 1 0 1 1 1 1 1 0Access R/W R/W R/W R/W R/W R/W R/W R

Bit Description

EN_CDIR : enable current direction detection0..disabled1..enabledEN_INT2 : interrupt enable for INT20..disabled1..enabledEN_INT1 : interrupt enable for INT10..disabled1..enabledEN_OC : interrupt enable for overcurrent0..disabled1..enabledEN_OV : interrupt enable for overvoltage0..disabled1..enabledEN_UV : interrupt enable for undervoltage0..disabled1..enabled

Table 5. Secondary Buck Converter Status Register

Table 6. Secondary Buck Converter Control Register

Table 7. Secondary buck interrupt register




5.7 LDO1

Topology

LDO1 is a linear low drop regulator with output current limitation. The regulator is activated as described in chapter „5.3 Op-

eration States“.

The output voltage is factory programmed.

The regulator output is discharged in its off state.

LDO1 can be operated during power down with a reduced internal supply current consumption. The maximum available out-

put current is decreased and the response times in case of line and load fluctuations are increased in this state.

LDO1 Registers

Register Name Address DescriptionLDO1 STAT 0x10 Status Register of LDO1LDO1 Config 0x11 Config Register of LDO1LDO1 INT 0x33 LDO1 interrupt register

Register LDO1 STAT (0x10) MSB LSB

Content OC_COMP OV_COMP UV_COMP CHP_UV OC OV UV ONReset Value 0 0 0 0 0 0 0 0Access R R R R R R R R

Bit Description

OC_COMP : (unfiltered) overcurrent comparator resultOV_COMP : (unfiltered) overvoltage comparator resultUV_COMP : (unfiltered) undervoltage comparator resultCHP_UV : Failure in auxiliary voltage generation.OC : This Bit is set to '1' when the LDO is switched on and an overcurrent is detectedOV : This Bit is set to '1' when the LDO is switched on and an overvoltage is detectedUV : This Bit is set to '1' when the LDO is switched on and an undervoltage is detected.ON : This Bit is set to '1' when the LDO1 is enabled.

Register LDO1 Config (0x11) MSB LSB

Content - - - - EN_OC EN_OV EN_UV ONReset Value 0 0 0 0 1 1 1 1Access R R R R R/W R/W R/W R/W

Bit Description

EN_OC : Bit 3 - enable for overcurrent interrupt0..disabled1..enabledEN_OV : Bit 1 - enable for overvoltage interrupt0..disabled1..enabledEN_UV : Bit 1 - enable for undervoltage interrupt0..disabled1..enabledON : Bit 0 - regulator enable0..disabled1..enabled

Table 8. Status Register of LDO1

Table 9. Config Register of LDO1




Topology

LDOs 2-4 are linear low drop regulators with output current limitation. They are intented to be operated from the outputs

of the buck converters and are activated in the order described in Chapter „5.3 Operation States“. In case the secondary buck

converter is not requested to be active, LDOs 2-4 expect other input sources according to the maximum ratings specification.

The output voltage is factory programmed.

The outputs of LDOs 2-4 are discharged to ground in their off state.

LDO2-4 Registers

Register Name Address DescriptionLDO2 Status 0x12 Status Register of LDO2LDO2 Config 0x13 Config Register of LDO2LDO3 Status 0x14 Status Register of LDO3LDO3 Config 0x15 Config Register of LDO3LDO4 Status 0x16 Status Register of LDO4LDO4 Config 0x17 Config Register of LDO4LDO2 INT 0x34 LDO2 interrupt registerLDO3 INT 0x35 LDO3 interrupt registerLDO4 INT 0x36 LDO4 interrupt register

Register LDO1 INT (0x33) MSB LSB

Content - - - - OC OV UV -Reset Value 0 0 0 0 0 0 0 0Access R R R R R/W R/W R/W R

Bit Description

OC : This Bit is set to '1' when an overcurrent status change occured and cleared by writing a '1' to the bit.OV : This Bit is set to '1' when an overvoltage status change occured and cleared by writing a '1' to the bit.UV : This Bit is set to '1' when an undervoltage status change occured and cleared by writing a '1' to the bit.

Register LDO2 Status (0x12) MSB LSB


Bit Description

OC_COMP : (unfiltered) overcurrent comparator resultOV_COMP : (unfiltered) overvoltage comparator resultUV_COMP : (unfiltered) undervoltage comparator resultCHP_UV : Failure in auxiliary voltage generation.OC : This Bit is set to '1' when the LDO is switched on and an overcurrent is detectedOV : This Bit is set to '1' when the LDO is switched on and an overvoltage is detectedUV : This Bit is set to '1' when the LDO is switched on and an undervoltage is detectedON : This Bit is set to '1' when LDO2 is enabled and reset to '0' whe the LDO2 is disabled.

Table 10. LDO1 interrupt register

5.8 LDO2-4






Content - - - - EN_OC EN_OV EN_UV ONReset Value 0 0 0 0 1 1 1 1Access R R R R R R R/W R/W

Bit Description

EN_OC : interrupt enable for overcurrent0..disabled1..enabledEN_OV : interrupt enable for overvoltage0..disabled1..enabledEN_UV : interrupt enable for undervoltage0..disabled1..enabledON : regulator enable0..disabled1..enabled



Bit Description




Bit Description

OC_COMP : (unfiltered) overcurrent comparator resultOV_COMP : (unfiltered) overvoltage comparator resultUV_COMP : (unfiltered) undervoltage comparator resultCHP_UV : Failure in auxiliary voltage generation.OC : This Bit is set to '1' when the LDO is switched on and an overcurrent is detectedOV : This Bit is set to '1' when the LDO is switched on and an overvoltage is detectedUV : This Bit is set to '1' when the LDO is switched on and an undervoltage is detectedON : This Bit is set to '1' when LDO3 is enabled and reset to '0' whe LDO3 is disabled.



Bit Description











Bit Description




Bit Description

OC_COMP : (unfiltered) overcurrent comparator resultOV_COMP : (unfiltered) overvoltage comparator resultUV_COMP : (unfiltered) undervoltage comparator resultCHP_UV : Failure in auxiliary voltage generation.OC : This Bit is set to '1' when the LDO is switched on and an overcurrent is detectedOV : This Bit is set to '1' when the LDO is switched on and an overvoltage is detectedUV : This Bit is set to '1' when the LDO is switched on and an undervoltage is detectedON : This Bit is set to '1' when LDO4 is enabled and reset to '0' whe the LDO4 is disabled.



Bit Description




Bit Description









5.9 Monitoring

The main supply (pins VIN1A,B), the host interface supply (VIO), the supply for the secondary buck regulator (VIN2A,B), the

auxiliary supply (CHP), the regulator outputs and the chip temperature are monitored. Failure conditions can be read via SPI in

the respective status registers.

Moreover, as soon as all regulator outputs that are requested to be active have reached their nominal output voltage with all

under and over voltage flags inactive, output PGOOD indicates this condition instantaneously with a high level.

Supply Monitoring

In case the supply falls below the VVIN1A,B

range, the IC remains operable, however, parameter specifications may not be fully

met. If the supply voltage decreases further below VVIN1A,B_UV_vf

(power fail), the regulated supply VDDA may fall below VVDDA_UV

.

In this case a power-on reset circuit generates a reset to the circuit control logic. With the logic in reset state output FS_ON is

active low, all IC outputs are disabled. Output RSTN remains inactive in this case.

In power down state no supply monitoring is performed.

The subsequent table lists the IC responses in case of failure conditions.

Monitor Operation Mode FS_ON RSTN Interrupt PGOOD Regulators Watchdog

VIN1A,B un-der voltage normal active low - - - off except

LDO1 -

VIN1A,B un-der voltage sleep active low - - - - -

VIN1A,B un-der voltage

sleep with LDO1 on active low - - - - -

VIN2A,B un-der voltage

normal, buck2 ena-bled

- - - active low Buck2 off -

VDDA under voltage - active low - - -

all regulators off; reset of all configura-tion settings

reset

VIO under voltage normal - - - - -

CHP under voltage normal - - - -

LDO2-4 are not switched on (if on they are not switched off)

-

LDO1 under voltage normal - - yes active low -

LDO1 under voltage

sleep with LDO1 on - - yes active low if

VIO applied - -

BUCK1-2, LDO1-4, over current

normal - - yes - - -

BUCK1-2, LDO1-4, over voltage

normal - - yes active low - -

BUCK1-2, LDO2-4, un-der voltage

normal - - yes active low - -

over temper-ature warning normal - - yes - - -

watchdog fail normal active low - yes - - reset

Table 20. Monitoring Table




The design implements a watchdog functionality that can be used in window or timeout mode.

The watchdog starts operation if VVIO

> VVIO_UV

.

The time out mode is an easier and less secure type of the watchdog modes. A closed window does not exist. The watchdog

trigger can be applied any time within the watchdog cycle.

Writing the correct trigger value to register „Register WD_TRIG (0x22)“ starts a new window period.

Alternating triggers must be used.

In case of an incorrect watchdog trigger the watchdog will generate a watchdog reset.

In case of a watchdog reset the open drain pin RSTN is set to low and the corresponding bit in register „Register WD_STAT

(0x21)“ is set. Pin RSTN needs an external pull up device in order to deliver a logical high level.

5.10 Watchdog; pin RSTN

5.10.1 Time out mode

Figure 4. Watchdog time out mode

Figure 5. Watchdog time out mode without trigger

Behaviour of watchdog in case of missing trigger in open window.




5.10.2 Window mode

The window mode is the secure type of the watchdog modes. It consists of a closed and an open window. A closed window is

50% of the configured watchdog period.

Triggering the watchdog is allowed in the open window only.

Writing the correct trigger value to register „Register WD_TRIG (0x22)“ starts a new window period.

Alternating triggers must be used.

In case of an incorrect watchdog trigger the watchdog will generate a watchdog reset.

In case of a watchdog reset the open drain pin RSTN is set to low and the corresponding bit in register „Register WD_STAT

(0x21)“ is set. Pin RSTN needs an external pull up device in order to deliver a logical high level.


Figure 6. Watchdog window mode

Figure 7. Watchdog window mode no trigger




Behaviour of watchdog in case of trigger in closed window.


Figure 8. Watchdog window mode trigger in closed window

Figure 9. Watchdog window mode no trigger in open window




Figure 10. Watchdog window mode wrong trigger in open window

Figure 11. Safe trigger area

Behaviour of watchdog in case of wrong trigger in open window.




The period can be configured in register „Register WD_PER_CFG (0x23)“ in the range from 4ms up to 1024ms using formula

4ms*(1+PER[7:0]).

The first period always starts with 256ms.

Trigger values A and B must be sent alternately. The first trigger byte must be trigger value A.

Any invalid trigger value results in a watchdog reset.

Registers „Register WD_CFG (0x20)“ and „Register WD_PER_CFG (0x23)“ can be written and read any time. The content of „Reg-

ister WD_CFG (0x20)“ and „Register WD_PER_CFG (0x23)“ is activated by writing an activation trigger value to the „Register

WD_TRIG (0x22)“ register. Register „Register WD_STAT (0x21)“ is updated from „Register WD_CFG (0x20)“, register „Register

WD_PER_STAT (0x24)“ from „Register WD_PER_CFG (0x23)“.

5.10.3 Configuration

Watchdog Register Table

Register Name Address DescriptionWD_CFG 0x20 Watchdog configuration.WD_STAT 0x21 Watchdog status register (active configuration)WD_TRIG 0x22 Watchdog trigger registerWD_PER_CFG 0x23 Watchdog period configurationWD_PER_STAT 0x24 Status of watchdog period (active configuration)

Register WD_CFG (0x20) MSB LSB

Content - - - - - - SWDM MODEReset Value 0 0 0 0 0 0 0 1Access R R R R R R R/W R/W

Bit Description

SWDM : Software development mode1...software development mode enabled0...software development mode disabledMODE : Watchdog mode1...time out mode0...window mode

Register WD_TRIG (0x22) MSB LSB

Content TRIG[7] TRIG[6] TRIG[5] TRIG[4] TRIG[3] TRIG[2] TRIG[1] TRIG[0]Reset Value 0 0 0 0 0 0 0 0Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description TRIG[7] : Watchdog trigger value (alternating content according to following table)

Register WD_STAT (0x21) MSB LSB

Content - - - - - WDRSTN SWDM MODEReset Value 0 0 0 0 0 0 0 0Access R R R R R R R R

Bit Description

WDRSTN : Watchdog reset1...watchdog failure event occured0...no watchdog failure event occuredThe bit is reset by updating the configuration registers (sending an update trigger).SWDM : Software development mode1...software development mode enabled0...software development mode disabledMODE : Watchdog mode1...time out mode0...window mode

Table 21. Watchdog configuration

Table 22. Watchdog status register (active configuration)

Table 23. Watchdog trigger register




Register WD_PER_CFG (0x23) MSB LSB

Content PER[7] PER[6] PER[5] PER[4] PER[3] PER[2] PER[1] PER[0]Reset Value 0 0 1 1 1 1 1 1Access R/W R/W R/W R/W R/W R/W R/W R/WBit Description PER[7] : Bit 7 .. 0: watchdog period configuration value

Register WD_PER_STAT (0x24) MSB LSB

Content PER[7] PER[6] PER[5] PER[4] PER[3] PER[2] PER[1] PER[0]Reset Value 0 0 1 1 1 1 1 1Access R R R R R R R RBit Description PER[7] : Bit 7 .. 0: watchdog period configuration value

Table 24. Watchdog period configuration

Table 25. Status of watchdog period (active configuration)

value trigger event register update0x65 trigger A no register update0x6a trigger B no register update0x95 trigger A config register content activated0x9a trigger B config register content activatedany other invalid trigger no register update

Table 26. Valid Watchdog Trigger Values

5.11 SPI communication; pins SCK, SDI, SDO, CSN

The SPI interface is used for:

• status information for over- and under voltages, on-status, over currents, over temperature warning

• watchdog configuration (time) and trigger via SPI

By setting CSN to low level, the communication can be enabled and setting it to high level disables the communication (in this

case, pin SDO is high impedance). Data shifts are controlled by the serial clock signal (SCK) during the transmission according

to the following rules:

• data is shifted MSB first, LSB last

• data is shifted out on the rising edge of SCK and is sampled on the falling edge of SCK

• data transmission length is always 16 Bit

SPI write is performed setting bit RW value to 1. During read bit RW needs to be 0.

The pull up for pin CSN is de- activated in sleep mode.

Bit RW

• 1: write access

• 0: read access

Figure 12. SPI access




Register INT (0x30) MSB LSB

Content LDO4 LDO3 LDO2 LDO1 SB PB BIST OTWReset Value 0 0 0 0 0 0 0 0Access R R R R R R R R/W

Bit Description

LDO4 : 1: A LDO4 event is reason for interruptLDO3 : 1: A LDO3 event is reason for interruptLDO2 : 1: A LDO2 event is reason for interruptLDO1 : 1: A LDO1 event is reason for interruptSB : 1: A secondary buck event is reason for interruptPB : 1: A primary buck event is reason for interruptBIST : 1: An internal startup interrupt occuredOTW : 1: An overtemperature warning level crossing is reason for interrupt

SPI timing diagram. For configuration of write and read access check corresponding diagrams.

The interrupt pin is driven low if the following interrupt sources/conditions occur:

• over temperature warning

• undervoltage at LDO1..4, PB, SB

• overvoltage at LDO1..4, PB, SB

• overcurrent at LDO1..4, PB, SB

• internal failures

Interrupts can be enabled in configuration registers of the corresponding modules.

For over temperature warning, under/over voltage and current the appearance and disappearance is signaled via an interrupt.

The interrupt is cleared by writing the corresponding status register, 5.12-1.

During startup of the IC and after sleep mode deactivation the IC checks its configuration. In case of detection of a configu-

ration failure an interrupt is raised and additional failure information is provided in the internal interrupt register. In case of a

severe failure the IC is sent to a failsafe mode with all voltage sources are switched off and RSTN and FS_ON are driven to low

level.

Figure 13. SPI Timing diagram

5.12 Interrupt; pin INTN

INTN Register Table

Register Name Address DescriptionINT 0x30 Interrupt status registerBIST 0x37 Internal failure registerINT_EN 0x38 enable register for over temperature and BIST interruptsOT_STAT 0x39 over temperature status register

Table 27. Interrupt status register




Register BIST (0x37) MSB LSB

Content - - - - INT3 INT2 INT1 INT0Reset Value 0 0 0 0 0 0 0 0Access R R R R R R R R

Bit Description

INT3 : The bit reflects the state of an internal startup failure.INT2 : The bit reflects the state of an internal startup failure.INT1 : The bit reflects the state of an internal startup failure.INT0 : The bit reflects the state of an internal startup failure.

Register INT_EN (0x38) MSB LSB

Content - - - - - - BIST_EN OT_ENReset Value 0 0 0 0 0 0 1 1Access R R R R R R R/W R/W

Bit Description

BIST_EN : enable for BIST interrupt0..disabled1..enabledOT_EN : enable for over temperatur interrupt0..disabled1..enabled

Register OT_STAT (0x39) MSB LSB

Content - - - - - - - OT_WReset Value 0 0 0 0 0 0 0 0Access R R R R R R R RBit Description OT_W : over temperature warning

Table 28. Internal failure register

Table 29. Enable register for over temperature and BIST interrupts

Table 30. Over temperature status register

Figure 14. Interrupt and status register dependency

In case of interrupt detailed information can be read from the device in order to evaluate the reason for interrupt.




Register FS_ON status register (0x25) MSB LSB

Content - - - BIST VIN VIO WD OTReset Value 0 0 0 0 0 0 0 0Access R R R R R R R R

Bit Description

BIST : BIST failed (internal failure)VIN : under voltage at pin VIN1A or VIN1BVIO : VIO time out exceededWD : Watchdog resetOT : Over temperatur shut down occured

Pin FS_ON is released and can be set to high level by an external pull up resistor after the reception of three valid watchdog

trigger pulses after output RSTN had been released.

The reason for a fail safe condition is stored in FS_ON status register.

It is recommended to read FS_ON status register after every start up.

5.13 Fail Safe; pin FS_ON

Table 31. FS_ON Status Register

6 Register Table

Register Name Address DescriptionPB Status 0x01 Primary Buck Converter Status RegisterPB Control 0x02 Primary Buck Converter Control RegisterSB Status 0x03 Secondary Buck Converter Status RegisterSB Control 0x04 Secondary Buck Converter Control RegisterLDO1 STAT 0x10 Status Register of LDO1LDO1 Config 0x11 Config Register of LDO1LDO2 Status 0x12 Status Register of LDO2LDO2 Config 0x13 Config Register of LDO2LDO3 Status 0x14 Status Register of LDO3LDO3 Config 0x15 Config Register of LDO3LDO4 Status 0x16 Status Register of LDO4LDO4 Config 0x17 Config Register of LDO4WD_CFG 0x20 Watchdog configurationWD_STAT 0x21 Watchdog status register (active configuration)WD_TRIG 0x22 Watchdog trigger registerWD_PER_CFG 0x23 Watchdog period configurationWD_PER_STAT 0x24 Status of watchdog period (active configuration)FS_ON status register 0x25 FS_ON Status RegisterINT 0x30 Interrupt status registerPB INT 0x31 Primary Buck Interrupt registerSB INT 0x32 Secondary buck interrupt registerLDO1 INT 0x33 LDO1 interrupt registerLDO2 INT 0x34 LDO2 interrupt registerLDO3 INT 0x35 LDO3 interrupt registerLDO4 INT 0x36 LDO4 interrupt registerBIST 0x37 Internal failure registerINT_EN 0x38 Enable register for over temperature and BIST interruptsOT_STAT 0x39 Over temperature status register




7 List of AbbreviationsTerm ExplanationASIC Application specific integrated circuitIC Integrated circuitPB Primary Buck ConverterSB Secondary Buck ConverterLDO Low Dropout RegulatorOTP One time programmable memoryao LDO1 always on

Signature ExplanationE Volume production52252A ELMOS project number + revision codeXXXX Production lot numberU Assembler codeYWW Year and week of assembly* # Mask revision code

8 Marking � E L M O S

� 52252

� YWW*#

� XXXU

Table 32. Marking of the Devices




9 Package ReferenceThe E522.52 is available in a Pb free, RoHs compliant QFN48L7 plastic package according to JEDEC MO-220 K, variant VKKD-6.

The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a soldering peak tempera-

ture of (260+5)°C.

SpecificationQM-No.:

08SP0644.04

Title:

Package Outline Specification48 lead quad flat non leaded package

(QFN48L7)

Package Outline and Dimensions are according JEDEC MO-220 K, variant VKKD-6, except reduced terminal length to 0.4mm.

Description Symbolmm inch

min typ max min typ maxPackage height A 0.80 0.90 1.00 0.031 0.035 0.039

Stand off A1 0.00 0.02 0.05 0.000 0.0008 0.002

Thickness of terminal leads, including lead finish A3 0.20 REF 0.0079 REF

Width of terminal leads b 0.18 0.25 0.30 0.007 0.010 0.012

Package length / width D / E 6.90 7.00 7.10 0.272 0.276 0.280

Distance between the two outer most terminals of one side (center to center)

D1 / E1 5.50 REF 0.217 REF

Length / width of exposed pad D2 / E2 4.60 4.75 4.90 0.181 0.187 0.193

Lead pitch e 0.50 BSC 0.020 BSC

Length of terminal for soldering to substrate L 0.35 0.40 0.45 0.014 0.016 0.018

Number of terminal positions N 48 48

Note: the mm values are valid, the inch values contains rounding errorsNote 1: for assembler specific pin1 identification please see QM-document 08SP0363.xx (Pin 1 Specification)

Document History

Revision Date Chapter Description/Reason for Change Author/Editor

.04 06.12.14 new document template, update drawing, no changes in values

ASto

06.12.14 ©Elmos GROUP / Transfer, reproduction, distribution and/or editing, in part or completely, without the prior written consent, are prohibited.

Page 1 of 1




Chapter Revision Change and Reason for Change Date Released Elmos- .00 Initial revision Nov 17, 2017 ZOE/DHOE

10 Record of Revisions

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Dual Buck / uad LDO E522 - elmos. · PDF filee522.52 sdo sck csn fosc tst fs_on on1 on2 chp vdda cmp1 ocp1 cmp2 ocp2 sdi. dual buck / uad ldo e522.52 ... 21 inldo2 22 voldo2 2 nldo2

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