DSP Based Equalization for 40-Gbps Fiber Optic Communication

DSP Based Equalization for 40-Gbps Fiber Optic

Communication

Shahriar Shahramian

Pro

ble

m &

Motiv

atio

n

• At high bit rates (> 10 Gbps) fiber optic channel’s impairments become prominent.

• Differential Mode Dispersion (in Multi Mode Fiber) & Polarization Mode Dispersion (in Single Mode Fiber) degrade signal quality over long haul fiber channels.

• Equalization techniques are required to achieve high bit rate over fiber optic channels.

Pro

ble

m &

Motiv

atio

n II

• Some analog equalization techniques have been shown for 40-Gbps communication.

• Another possibility for equalization is digital equalization.

• The main challenge of high speed digital equalization is the design of the ADC at such high bit rates.

• Provided that high speed ADCs can be built, digital equalization is more accurate and offers more flexibility.

DS

P E

qualize

r Blo

ck D

iagra

m

Detector&

Pre-Amp

Optical Fiber Ultra Fast

ADC(40-GS/s)

AdaptiveChannelEqualizer

ClockRecovery

EqualizedData

AdaptiveChannelEqualizer

Slicer+

DFE

FFE

-

Flash

AD

C B

lock

Dia

gra

m

TIA INV TH DRV T/H

Data Tree

1 16

Input Stage Track & Hold

16

GAINOffset Amp.INVINV

Comparators (16)Thermometer Code

Output

Clock Tree

1 16

16

S/H Clock

External Clock

Latch

TH

A B

lock D

iag

ram

TIA INV TH DRV

Input Stage Track & Hold

DRV

Output Driver

TIA

Clock Distribution

INVINV CLKDRV

T/H

TH

A D

ie P

hoto

• Chip Area: – 1.1mm2

• Technology:– 0.18μm SiGe BiCMOS

HBT

– 150/155 GHz fT/fmax

• Foundry:– Jazz Semiconductor

Clock Input (40 GHz)

Data

Inp

ut

(DC

– 2

0 G

Hz)

Data

Outp

ut

DC & Biasing Input

TH

A M

easu

rem

en

t Resu

lts

OP

ON

Diff. Output

OP

Diff. Output

• Both data and clock input have been applied single ended.

• In Differential mode, the “in phase” clock feed-through signal is eliminated.

TH

A M

easu

rem

en

ts II

• Two tone signals at the input (separated by 100 MHz) have been used to measure the IM3 output power and the input compression point.

• An abstract has been submitted to CSICS 2005 based on this circuit as (to our best knowledge) the world’s fastest THA.