DS031 - Virtex-II Platform FPGAs: Complete Data Sheetweb.mit.edu/6.111/www/labkit/datasheets/virtex2datasheet.pdf · 2005. 4. 1. · R Virtex-II Platform FPGAs: Introduction and Overview

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DS031 (v3.4) March 1, 2005 www.xilinx.comProduct Specification 1

Module 1: Introduction and Overview7 pages

• Summary of Features• General Description• Architecture• Device/Package Combinations and Maximum I/O• Ordering Examples

Module 2: Functional Description41 pages

• Detailed Description- Input/Output Blocks (IOBs)- Digitally Controlled Impedance (DCI)- Configurable Logic Blocks (CLBs)- 18-Kb Block SelectRAM™ Resources- 18-Bit x 18-Bit Multipliers- Global Clock Multiplexer Buffers- Digital Clock Manager (DCM)

• Routing• Creating a Design• Configuration

Module 3: DC and Switching Characteristics43 pages

• Electrical Characteristics• Performance Characteristics• Switching Characteristics• Pin-to-Pin Output Parameter Guidelines• Pin-to-Pin Input Parameter Guidelines• DCM Timing Parameters• Source-Synchronous Switching Characteristics

Module 4: Pinout Information226 pages

• Pin Definitions• Pinout Tables

- CS144/CSG144 Chip-Scale BGA Package- FG256/FGG256 Fine-Pitch BGA Package- FG456/FGG456 Fine-Pitch BGA Package- FG676/FGG676 Fine-Pitch BGA Package- BG575/BGG575 Standard BGA Package- BG728/BGG728 Standard BGA Package- FF896 Flip-Chip Fine-Pitch BGA Package- FF1152 Flip-Chip Fine-Pitch BGA Package- FF1517 Flip-Chip Fine-Pitch BGA Package- BF957Flip-Chip BGA Package

IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own RevisionHistory at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.

1Virtex-II Platform FPGAs:

Complete Data Sheet

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DS031-1 (v3.4) March 1, 2005 www.xilinx.com Module 1 of 4Product Specification 1

Summary of Virtex-II™ Features• Industry First Platform FPGA Solution • IP-Immersion Architecture

- Densities from 40K to 8M system gates- 420 MHz internal clock speed (Advance Data)- 840+ Mb/s I/O (Advance Data)

• SelectRAM™ Memory Hierarchy- 3 Mb of dual-port RAM in 18 Kbit block SelectRAM

resources- Up to 1.5 Mb of distributed SelectRAM resources

• High-Performance Interfaces to External Memory- DRAM interfaces

· SDR / DDR SDRAM· Network FCRAM · Reduced Latency DRAM

- SRAM interfaces· SDR / DDR SRAM· QDR™ SRAM

- CAM interfaces• Arithmetic Functions

- Dedicated 18-bit x 18-bit multiplier blocks- Fast look-ahead carry logic chains

• Flexible Logic Resources- Up to 93,184 internal registers / latches with Clock

Enable- Up to 93,184 look-up tables (LUTs) or cascadable

16-bit shift registers- Wide multiplexers and wide-input function support- Horizontal cascade chain and sum-of-products

support- Internal 3-state bussing

• High-Performance Clock Management Circuitry- Up to 12 DCM (Digital Clock Manager) modules

· Precise clock de-skew· Flexible frequency synthesis· High-resolution phase shifting

- 16 global clock multiplexer buffers• Active Interconnect Technology

- Fourth generation segmented routing structure- Predictable, fast routing delay, independent of

fanout• SelectIO™-Ultra Technology

- Up to 1,108 user I/Os- 19 single-ended and six differential standards- Programmable sink current (2 mA to 24 mA) per I/O- Digitally Controlled Impedance (DCI) I/O: on-chip

termination resistors for single-ended I/O standards

- PCI-X compatible (133 MHz and 66 MHz) at 3.3V- PCI compliant (66 MHz and 33 MHz) at 3.3V- CardBus compliant (33 MHz) at 3.3V- Differential Signaling

· 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers

· Bus LVDS I/O· Lightning Data Transport (LDT) I/O with current

driver buffers· Low-Voltage Positive Emitter-Coupled Logic

(LVPECL) I/O· Built-in DDR input and output registers

- Proprietary high-performance SelectLink Technology· High-bandwidth data path· Double Data Rate (DDR) link· Web-based HDL generation methodology

• Supported by Xilinx Foundation™ and Alliance Series™ Development Systems- Integrated VHDL and Verilog design flows- Compilation of 10M system gates designs- Internet Team Design (ITD) tool

• SRAM-Based In-System Configuration- Fast SelectMAP configuration- Triple Data Encryption Standard (DES) security

option (Bitstream Encryption)- IEEE 1532 support - Partial reconfiguration- Unlimited reprogrammability- Readback capability

• 0.15 µm 8-Layer Metal Process with 0.12 µm High-Speed Transistors

• 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V VCCAUX Auxiliary and VCCO I/O Power Supplies

• IEEE 1149.1 Compatible Boundary-Scan Logic Support

• Flip-Chip and Wire-Bond Ball Grid Array (BGA) Packages in Three Standard Fine Pitches (0.80 mm, 1.00 mm, and 1.27 mm)

• Wire-Bond BGA Devices Available in Pb-Free Packaging (www.xilinx.com/pbfree)

• 100% Factory Tested

7Virtex-II Platform FPGAs:

Introduction and Overview

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Virtex-II Platform FPGAs: Introduction and OverviewR


General DescriptionThe Virtex-II family is a platform FPGA developed for highperformance from low-density to high-density designs thatare based on IP cores and customized modules. The familydelivers complete solutions for telecommunication, wire-less, networking, video, and DSP applications, includingPCI, LVDS, and DDR interfaces.

The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metalprocess and the Virtex-II architecture are optimized for highspeed with low power consumption. Combining a wide vari-ety of flexible features and a large range of densities up to10 million system gates, the Virtex-II family enhances pro-grammable logic design capabilities and is a powerful alter-native to mask-programmed gates arrays. As shown inTable 1, the Virtex-II family comprises 11 members, rangingfrom 40K to 8M system gates.

PackagingOfferings include ball grid array (BGA) packages with0.80 mm, 1.00 mm, and 1.27 mm pitches. In addition to tra-ditional wire-bond interconnects, flip-chip interconnect isused in some of the BGA offerings. The use of flip-chipinterconnect offers more I/Os than is possible in wire-bondversions of the similar packages. Flip-chip constructionoffers the combination of high pin count with high thermalcapacity.

Wire-bond packages CS, FG, and BG are optionally avail-abe in Pb-free versions CSG, FGG, and BGG. See Virtex-IIOrdering Examples, page 6.

Table 2 shows the maximum number of user I/Os available.The Virtex-II device/package combination table (Table 6 atthe end of this section) details the maximum number of I/Osfor each device and package using wire-bond or flip-chiptechnology.

Table 1: Virtex-II Field-Programmable Gate Array Family Members

DeviceSystem Gates

CLB (1 CLB = 4 slices = Max 128 bits)

Multiplier Blocks

SelectRAM Blocks

DCMsMax I/O Pads(1)

Array Row x Col. Slices

Maximum Distributed RAM Kbits

18 Kbit Blocks

Max RAM (Kbits)

XC2V40 40K 8 x 8 256 8 4 4 72 4 88

XC2V80 80K 16 x 8 512 16 8 8 144 4 120

XC2V250 250K 24 x 16 1,536 48 24 24 432 8 200

XC2V500 500K 32 x 24 3,072 96 32 32 576 8 264

XC2V1000 1M 40 x 32 5,120 160 40 40 720 8 432

XC2V1500 1.5M 48 x 40 7,680 240 48 48 864 8 528

XC2V2000 2M 56 x 48 10,752 336 56 56 1,008 8 624

XC2V3000 3M 64 x 56 14,336 448 96 96 1,728 12 720

XC2V4000 4M 80 x 72 23,040 720 120 120 2,160 12 912

XC2V6000 6M 96 x 88 33,792 1,056 144 144 2,592 12 1,104

XC2V8000 8M 112 x 104 46,592 1,456 168 168 3,024 12 1,108

Notes: 1. See details in Table 2, “Maximum Number of User I/O Pads”.

Table 2: Maximum Number of User I/O Pads

Device Wire-Bond Flip-Chip

XC2V40 88 -

XC2V80 120 -

XC2V250 200 -

XC2V500 264 -

XC2V1000 328 432

XC2V1500 392 528

XC2V2000 - 624

XC2V3000 516 720

XC2V4000 - 912

XC2V6000 - 1,104

XC2V8000 - 1,108




Architecture

Virtex-II Array OverviewVirtex-II devices are user-programmable gate arrays with various configurable elements. The Virtex-II architecture is optimized for high-density and high-performance logic designs. As shown in Figure 1, the programmable device is comprised of input/output blocks (IOBs) and internal configurable logic blocks (CLBs).

Programmable I/O blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by the programmable IOBs.

The internal configurable logic includes four major elementsorganized in a regular array.

• Configurable Logic Blocks (CLBs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. BUFTs (3-state buffers) associated with each CLB element drive dedicated segmentable horizontal routing resources.

• Block SelectRAM memory modules provide large 18 Kbit storage elements of dual-port RAM.

• Multiplier blocks are 18-bit x 18-bit dedicated multipliers.

• DCM (Digital Clock Manager) blocks provide self-calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication and division, coarse- and fine-grained clock phase shifting.

A new generation of programmable routing resources calledActive Interconnect Technology interconnects all of theseelements. The general routing matrix (GRM) is an array ofrouting switches. Each programmable element is tied to aswitch matrix, allowing multiple connections to the generalrouting matrix. The overall programmable interconnection ishierarchical and designed to support high-speed designs.

All programmable elements, including the routingresources, are controlled by values stored in static memorycells. These values are loaded in the memory cells during

configuration and can be reloaded to change the functionsof the programmable elements.

Virtex-II FeaturesThis section briefly describes Virtex-II features.

Input/Output Blocks (IOBs)

IOBs are programmable and can be categorized as follows:

• Input block with an optional single-data-rate or double-data-rate (DDR) register

• Output block with an optional single-data-rate or DDR register, and an optional 3-state buffer, to be driven directly or through a single or DDR register

• Bidirectional block (any combination of input and output configurations)

These registers are either edge-triggered D-type flip-flopsor level-sensitive latches.

IOBs support the following single-ended I/O standards:

• LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)

• PCI-X compatible (133 MHz and 66 MHz) at 3.3V

• PCI compliant (66 MHz and 33 MHz) at 3.3V

• CardBus compliant (33 MHz) at 3.3V

• GTL and GTLP

Figure 1: Virtex-II Architecture Overview

Global Clock Mux

DCM DCM IOB

CLBProgrammable I/Os

Block SelectRAM Multiplier

Configurable Logic

DS031_28_100900




• HSTL (Class I, II, III, and IV)

• SSTL (3.3V and 2.5V, Class I and II)

• AGP-2X

The digitally controlled impedance (DCI) I/O feature auto-matically provides on-chip termination for each I/O element.

The IOB elements also support the following differential sig-naling I/O standards:

• LVDS

• BLVDS (Bus LVDS)

• ULVDS

• LDT

• LVPECL

Two adjacent pads are used for each differential pair. Two orfour IOB blocks connect to one switch matrix to access therouting resources.

Configurable Logic Blocks (CLBs)

CLB resources include four slices and two 3-state buffers.Each slice is equivalent and contains:

• Two function generators (F & G)

• Two storage elements

• Arithmetic logic gates

• Large multiplexers

• Wide function capability

• Fast carry look-ahead chain

• Horizontal cascade chain (OR gate)

The function generators F & G are configurable as 4-inputlook-up tables (LUTs), as 16-bit shift registers, or as 16-bitdistributed SelectRAM memory.

In addition, the two storage elements are either edge-trig-gered D-type flip-flops or level-sensitive latches.

Each CLB has internal fast interconnect and connects to aswitch matrix to access general routing resources.

Block SelectRAM Memory

The block SelectRAM memory resources are 18 Kb ofdual-port RAM, programmable from 16K x 1 bit to 512 x 36bits, in various depth and width configurations. Each port istotally synchronous and independent, offering three"read-during-write" modes. Block SelectRAM memory iscascadable to implement large embedded storage blocks.Supported memory configurations for dual-port and sin-gle-port modes are shown in Table 3.

A multiplier block is associated with each SelectRAM mem-ory block. The multiplier block is a dedicated 18 x 18-bitmultiplier and is optimized for operations based on the blockSelectRAM content on one port. The 18 x 18 multiplier canbe used independently of the block SelectRAM resource.Read/multiply/accumulate operations and DSP filter struc-tures are extremely efficient.

Both the SelectRAM memory and the multiplier resourceare connected to four switch matrices to access the generalrouting resources.

Global Clocking

The DCM and global clock multiplexer buffers provide acomplete solution for designing high-speed clockingschemes.

Up to 12 DCM blocks are available. To generate de-skewedinternal or external clocks, each DCM can be used to elimi-nate clock distribution delay. The DCM also provides 90-,180-, and 270-degree phase-shifted versions of its outputclocks. Fine-grained phase shifting offers high-resolutionphase adjustments in increments of 1/256 of the clockperiod. Very flexible frequency synthesis provides a clockoutput frequency equal to any M/D ratio of the input clockfrequency, where M and D are two integers. For the exacttiming parameters, see Virtex-II Electrical Characteristics.

Virtex-II devices have 16 global clock MUX buffers, with upto eight clock nets per quadrant. Each global clock MUXbuffer can select one of the two clock inputs and switchglitch-free from one clock to the other. Each DCM block isable to drive up to four of the 16 global clock MUX buffers.

Routing Resources

The IOB, CLB, block SelectRAM, multiplier, and DCM ele-ments all use the same interconnect scheme and the sameaccess to the global routing matrix. Timing models areshared, greatly improving the predictability of the perfor-mance of high-speed designs.

There are a total of 16 global clock lines, with eight availableper quadrant. In addition, 24 vertical and horizontal longlines per row or column as well as massive secondary andlocal routing resources provide fast interconnect. Virtex-IIbuffered interconnects are relatively unaffected by netfanout and the interconnect layout is designed to minimizecrosstalk.

Horizontal and vertical routing resources for each row orcolumn include:

• 24 long lines• 120 hex lines• 40 double lines• 16 direct connect lines (total in all four directions)

Table 3: Dual-Port And Single-Port Configurations

16K x 1 bit 2K x 9 bits

8K x 2 bits 1K x 18 bits

4K x 4 bits 512 x 36 bits




Boundary Scan

Boundary scan instructions and associated data registerssupport a standard methodology for accessing and config-uring Virtex-II devices that complies with IEEE standards1149.1 — 1993 and 1532. A system mode and a test modeare implemented. In system mode, a Virtex-II device per-forms its intended mission even while executing non-testboundary-scan instructions. In test mode, boundary-scantest instructions control the I/O pins for testing purposes.The Virtex-II Test Access Port (TAP) supports BYPASS,PRELOAD, SAMPLE, IDCODE, and USERCODE non-testinstructions. The EXTEST, INTEST, and HIGHZ test instruc-tions are also supported.

Configuration

Virtex-II devices are configured by loading data into internalconfiguration memory, using the following five modes:

• Slave-serial mode• Master-serial mode• Slave SelectMAP mode• Master SelectMAP mode• Boundary-Scan mode (IEEE 1532)

A Data Encryption Standard (DES) decryptor is availableon-chip to secure the bitstreams. One or two triple-DES keysets can be used to optionally encrypt the configurationinformation.

Readback and Integrated Logic Analyzer

Configuration data stored in Virtex-II configuration memorycan be read back for verification. Along with the configura-tion data, the contents of all flip-flops/latches, distributed

SelectRAM, and block SelectRAM memory resources canbe read back. This capability is useful for real-time debug-ging.

The Integrated Logic Analyzer (ILA) core and software pro-vides a complete solution for accessing and verifyingVirtex-II devices.

Virtex-II Device/Package Combinations and Maximum I/OWire-bond and flip-chip packages are available. Table 4 andTable 5 show the maximum possible number of user I/Os inwire-bond and flip-chip packages, respectively. Table 6shows the number of available user I/Os for all device/pack-age combinations.

• CS denotes wire-bond chip-scale ball grid array (BGA) (0.80 mm pitch).

• CSG denotes Pb-free wire-bond chip-scale ball grid array (BGA) (0.80 mm pitch).

• FG denotes wire-bond fine-pitch BGA (1.00 mm pitch). • FGG denotes Pb-free wire-bond fine-pitch BGA (1.00

mm pitch). • BG denotes standard BGA (1.27 mm pitch).• BGG denotes Pb-free standard BGA (1.27 mm pitch).• FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).• BF denotes flip-chip BGA (1.27 mm pitch).

The number of I/Os per package include all user I/Os exceptthe 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,DXP, and RSVD) and VBATT.

Table 4: Wire-Bond Packages Information

Package(1)CS144/CSG144

FG256/FGG256

FG456/FGG456

FG676/FGG676

BG575/BGG575

BG728/BGG728

Pitch (mm) 0.80 1.00 1.00 1.00 1.27 1.27

Size (mm) 12 x 12 17 x 17 23 x 23 27 x 27 31 x 31 35 x 35

I/Os 92 172 324 484 408 516

Notes: 1. Wire-bond packages include FGGnnn Pb-free versions. See Virtex-II Ordering Examples (Module 1).

Table 5: Flip-Chip Packages Information

Package FF896 FF1152 FF1517 BF957

Pitch (mm) 1.00 1.00 1.00 1.27

Size (mm) 31 x 31 35 x 35 40 x 40 40 x 40

I/Os 624 824 1,108 684




Virtex-II Ordering Examples

Table 6: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os (Advance Information)

Package(1,2)

Available I/Os

XC2V40

XC2V80

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

CS144/CSG144 88 92 92 - - - - - - - -

FG256/FGG256 88 120 172 172 172 - - - - - -

FG456/FGG456 - - 200 264 324 - - - - - -

FG676/FGG676 - - - - - 392 456 484 - - -

FF896 - - - - 432 528 624 - - - -

FF1152 - - - - - - - 720 824 824 824

FF1517 - - - - - - - - 912 1,104 1,108

BG575/BGG575 - - - - 328 392 408 - - - -

BG728/BGG728 - - - - - - - 516 - - -

BF957 - - - - - - 624 684 684 684 -

Notes: 1. All devices in a particular package are pinout (footprint) compatible. In addition, the FG456/FGG456 and FG676/FGG676 packages

are compatible, as are the FF896 and FF1152 packages.2. Wire-bond packages CS144, FG256, FG456, FG676, BG575, and BG728 are also available in Pb-free versions CSG144, FGG256, FGG456,

FGG676, BGG575, and BGG728. See Virtex-II Ordering Examples for details on how to order.

Figure 2: Virtex-II Ordering Example. Regular Package

Example: XC2V1000-5FG456C

Device Type Temperature RangeC = Commercial (Tj = 0˚C to +85˚C)I = Industrial (Tj = –40˚C to +100˚C)

Number of Pins

Package Type

Speed Grade(-4, -5, -6)

DS031_35_033001

Figure 3: Virtex-II Ordering Example. Pb-Free Package

Example: XC2V3000-6BGG728C

Device Type Temperature RangeC = Commercial (Tj = 0˚C to +85˚C)I = Industrial (Tj = –40˚C to +100˚C)Number of PinsPb-Free PackagePackage Type

Speed Grade(-4, -5, -6)

DS031_35a_061804




Revision HistoryThis section records the change history for this module of the data sheet.

Virtex-II Data SheetThe Virtex-II Data Sheet contains the following modules:

• Virtex-II Platform FPGAs: Introduction and Overview (Module 1)

• Virtex-II Platform FPGAs: Functional Description (Module 2)

• Virtex-II Platform FPGAs: DC and Switching Characteristics (Module 3)

• Virtex-II Platform FPGAs: Pinout Information (Module 4)

Date Version Revision

11/07/00 1.0 Early access draft.

12/06/00 1.1 Initial release.

01/15/01 1.2 Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics sections.

01/25/01 1.3 The data sheet was divided into four modules (per the current style standard).

04/02/01 1.5 Skipped v1.4 to sync up modules. Reverted to traditional double-column format.

07/30/01 1.6 Made minor changes to items listed under Summary of Virtex-II™ Features.

10/02/01 1.7 Minor edits.

07/16/02 1.8 Updated Virtex-II Device/Package Combinations shown in Table 6.

09/26/02 1.9 Updated Table 2 and Table 6 to reflect supported Virtex-II Device/Package Combinations.

08/01/03 2.0 All Virtex-II devices and speed grades now Production. See Table 13, Module 3.

03/29/04 2.0.1 Recompiled for backward compatibility with Acrobat 4 and above. No content changes.

06/24/04 3.3 Added references to available Pb-free wire-bond packages. (Revision number advanced to level of complete data sheet.)

03/01/05 3.4 No changes in Module 1 for this revision.




Detailed Description

Input/Output Blocks (IOBs)Virtex-II™ I/O blocks (IOBs) are provided in groups of twoor four on the perimeter of each device. Each IOB can beused as input and/or output for single-ended I/Os. TwoIOBs can be used as a differential pair. A differential pair isalways connected to the same switch matrix, as shown inFigure 1.

IOB blocks are designed for high performances I/Os, sup-porting 19 single-ended standards, as well as differentialsignaling with LVDS, LDT, Bus LVDS, and LVPECL.

Note: Differential I/Os must use the same clock.

Supported I/O Standards

Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-puts that support a wide variety of I/O signaling standards.In addition to the internal supply voltage (VCCINT = 1.5V),output driver supply voltage (VCCO) is dependent on the I/Ostandard (see Table 1 and Table 2). An auxiliary supplyvoltage (VCCAUX = 3.3 V) is required, regardless of the I/Ostandard used. For exact supply voltage absolute maximumratings, see DC Input and Output Levels in Module 3.

All of the user IOBs have fixed-clamp diodes to VCCO and toground. As outputs, these IOBs are not compatible or com-pliant with 5V I/O standards. As inputs, these IOBs are notnormally 5V tolerant, but can be used with 5V I/O standardswhen external current-limiting resistors are used. For moredetails, see the “5V Tolerant I/Os“ Tech Topic at www.xil-inx.com.

Table 3 lists supported I/O standards with Digitally Con-trolled Impedance. See Digitally Controlled Impedance(DCI), page 8.

40 Virtex-II Platform FPGAs:

Functional Description

DS031-2 (v3.4) March 1, 2005 Product Specification

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Figure 1: Virtex-II Input/Output Tile

IOBPAD4

IOBPAD3

Differential Pair

IOBPAD2

IOBPAD1

Differential Pair

SwitchMatrix

DS031_30_101600

Table 1: Supported Single-Ended I/O Standards

IOSTANDARD Attribute

OutputVCCO

InputVCCO

InputVREF

Board Termination Voltage (VTT)

LVTTL 3.3 3.3 N/R(3) N/R

LVCMOS33 3.3 3.3 N/R N/R




PCI33_3 3.3 3.3 N/R N/R

PCI66_3 3.3 3.3 N/R N/R

PCI-X 3.3 3.3 N/R N/R

GTL Note (1) Note (1) 0.8 1.2

GTLP Note (1) Note (1) 1.0 1.5

HSTL_I 1.5 N/R 0.75 0.75

HSTL_II 1.5 N/R 0.75 0.75

HSTL_III 1.5 N/R 0.9 1.5

HSTL_IV 1.5 N/R 0.9 1.5

HSTL_I_18 1.8 N/R 0.9 0.9

HSTL_II_18 1.8 N/R 0.9 0.9

HSTL_III _18 1.8 N/R 1.1 1.8

HSTL_IV_18 1.8 N/R 1.1 1.8

SSTL18_I(2) 1.8 N/R 0.9 0.9

SSTL18_II 1.8 N/R 0.9 0.9

SSTL2_I 2.5 N/R 1.25 1.25

SSTL2_II 2.5 N/R 1.25 1.25

SSTL3_I 3.3 N/R 1.5 1.5

SSTL3_II 3.3 N/R 1.5 1.5

AGP-2X/AGP 3.3 N/R 1.32 N/R

Notes: 1. VCCO of GTL or GTLP should not be lower than the termination

voltage or the voltage seen at the I/O pad. Example: If the pin High level is 1.5V, connect VCCO to 1.5V.

2. SSTL18_I is not a JEDEC-supported standard.3. N/R = no requirement.

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Virtex-II Platform FPGAs: Functional DescriptionR


Logic Resources

IOB blocks include six storage elements, as shown inFigure 2.

Each storage element can be configured either as anedge-triggered D-type flip-flop or as a level-sensitive latch.On the input, output, and 3-state path, one or two DDR reg-isters can be used.

Double data rate is directly accomplished by the two regis-ters on each path, clocked by the rising edges (or fallingedges) from two different clock nets. The two clock signalsare generated by the DCM and must be 180 degrees out ofphase, as shown in Figure 3. There are two input, output,and 3-state data signals, each being alternately clockedout.

Table 2: Supported Differential Signal I/O Standards

I/O StandardOutputVCCO

Input VCCO

InputVREF

OutputVOD

LVPECL_33 3.3 N/R(1) N/R 0.490 - 1.220

LDT_25 2.5 N/R N/R 0.500 - 0.700

LVDS_33 3.3 N/R N/R 0.250 - 0.400

LVDS_25 2.5 N/R N/R 0.250 - 0.400

LVDSEXT_33 3.3 N/R N/R 0.440 - 0.820

LVDSEXT_25 2.5 N/R N/R 0.440 - 0.820

BLVDS_25 2.5 N/R N/R 0.250 - 0.450

ULVDS_25 2.5 N/R N/R 0.500 - 0.700

Notes: 1. N/R = no requirement.

Table 3: Supported DCI I/O Standards

I/OStandard

OutputVCCO

InputVCCO

InputVREF

TerminationType

LVDCI_33(1) 3.3 3.3 N/R(4) Series

LVDCI_DV2_33(1) 3.3 3.3 N/R Series

LVDCI_25(1) 2.5 2.5 N/R Series






GTL_DCI 1.2 1.2 0.8 Single

GTLP_DCI 1.5 1.5 1.0 Single

HSTL_I_DCI 1.5 1.5 0.75 Split

HSTL_II_DCI 1.5 1.5 0.75 Split

HSTL_III_DCI 1.5 1.5 0.9 Single

HSTL_IV_DCI 1.5 1.5 0.9 Single

HSTL_I_DCI_18 1.8 1.8 0.9 Split

HSTL_II_DCI_18 1.8 1.8 0.9 Split

HSTL_III_DCI_18 1.8 1.8 1.1 Single

HSTL_IV_DCI_18 1.8 1.8 1.1 Single

SSTL18_I_DCI(3) 1.8 1.8 0.9 Split

SSTL18_II_DCI 1.8 1.8 0.9 Split

SSTL2_I_DCI(2) 2.5 2.5 1.25 Split

SSTL2_II_DCI(2) 2.5 2.5 1.25 Split

SSTL3_I_DCI(2) 3.3 3.3 1.5 Split

SSTL3_II_DCI(2) 3.3 3.3 1.5 Split

LVDS_25_DCI 2.5 2.5 N/R Split

LVDSEXT_25_DCI 2.5 2.5 N/R Split

Notes: 1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled

impedance buffers, matching the reference resistors or half of the reference resistors.

2. These are SSTL compatible.3. SSTL18_I is not a JEDEC-supported standard.4. N/R = no requirement.

Figure 2: Virtex-II IOB Block

Reg

OCK1

Reg

OCK2

Reg

ICK1

Reg

ICK2

DDR muxInput

PAD

3-State

Reg

OCK1

Reg

OCK2

DDR mux

Output

IOB

DS031_29_100900




The DDR mechanism shown in Figure 3 can be used to mir-ror a copy of the clock on the output. This is useful for prop-agating a clock along the data that has an identical delay. Itis also useful for multiple clock generation, where there is aunique clock driver for every clock load. Virtex-II devicescan produce many copies of a clock with very little skew.

Each group of two registers has a clock enable signal (ICEfor the input registers, OCE for the output registers, andTCE for the 3-state registers). The clock enable signals areactive High by default. If left unconnected, the clock enablefor that storage element defaults to the active state.

Each IOB block has common synchronous or asynchro-nous set and reset (SR and REV signals).

SR forces the storage element into the state specified by theSRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.SRLOW forces a logic “0”. When SR is used, a second input(REV) forces the storage element into the opposite state. Thereset condition predominates over the set condition. The ini-tial state after configuration or global initialization state isdefined by a separate INIT0 and INIT1 attribute. By default,the SRLOW attribute forces INIT0, and the SRHIGH attributeforces INIT1.

For each storage element, the SRHIGH, SRLOW, INIT0,and INIT1 attributes are independent. Synchronous orasynchronous set / reset is consistent in an IOB block.

All the control signals have independent polarity. Anyinverter placed on a control input is automatically absorbed.

Each register or latch (independent of all other registers orlatches) (see Figure 4) can be configured as follows:

• No set or reset• Synchronous set• Synchronous reset• Synchronous set and reset• Asynchronous set (preset)• Asynchronous reset (clear)• Asynchronous set and reset (preset and clear)

The synchronous reset overrides a set, and an asynchro-nous clear overrides a preset.

Figure 3: Double Data Rate Registers

D1

CLK1

DDR MUX

Q1

FDDR

D2

CLK2

(50/50 duty cycle clock)

CLOCK

Q Q

Q2

D1

CLK1

DDR MUX

DCM

Q1

FDDR

D2

CLK2

Q2

180° 0°

DS031_26_100900




Input/Output Individual Options

Each device pad has optional pull-up and pull-down in allSelectI/O-Ultra configurations. Each device pad hasoptional weak-keeper in LVTTL, LVCMOS, and PCISelectI/O-Ultra configurations, as illustrated in Figure 5.Values of the optional pull-up and pull-down resistors are inthe range 10 - 60 KΩ, which is the specification for VCCOwhen operating at 3.3V (from 3.0 to 3.6V only). The clampdiode is always present, even when power is not.

The optional weak-keeper circuit is connected to each userI/O pad. When selected, the circuit monitors the voltage onthe pad and weakly drives the pin High or Low. If the pin isconnected to a multiple-source signal, the weak-keeperholds the signal in its last state if all drivers are disabled.Maintaining a valid logic level in this way eliminates buschatter. An enabled pull-up or pull-down overrides theweak-keeper circuit.

LVTTL sinks and sources current up to 24 mA. The currentis programmable for LVTTL and LVCMOS SelectI/O-Ultrastandards (see Table 4). Drive-strength and slew-rate con-trols for each output driver, minimize bus transients. ForLVDCI and LVDCI_DV2 standards, drive strength andslew-rate controls are not available.

Figure 4: Register / Latch Configuration in an IOB Block

FFLATCH

SR REV

D1 Q1

CE

CK1

FFLATCH

SR REV

D2

FF1

FF2DDR MUX

Q2

CECK2

REV

SR

(O/T) CLK1

(OQ or TQ)

(O/T) CE

(O/T) 1

(O/T) CLK2

(O/T) 2

Attribute INIT1INIT0SRHIGHSRLOW

Attribute INIT1INIT0SRHIGHSRLOW

Reset TypeSYNCASYNC

DS031_25_110300

Sharedby all

registers

Figure 5: LVTTL, LVCMOS or PCI SelectI/O-Ultra Standards

VCCO

VCCO

VCCO

WeakKeeper

ProgramDelay

OBUF

IBUF

ProgramCurrent

ClampDiode

PAD

VCCAUX = 3.3V

DS031_23_022205

VCCINT = 1.5V

10KΩ – 60KΩ

10KΩ – 60KΩ




Figure 6 shows the SSTL2, SSTL3, and HSTL configura-tions. HSTL can sink current up to 48 mA. (HSTL IV)

All pads are protected against damage from electrostaticdischarge (ESD) and from over-voltage transients. Virtex-IIuses two memory cells to control the configuration of an I/Oas an input. This is to reduce the probability of an I/O con-figured as an input from flipping to an output when sub-jected to a single event upset (SEU) in space applications.

Prior to configuration, all outputs not involved in configura-tion are forced into their high-impedance state. Thepull-down resistors and the weak-keeper circuits are inac-tive. The dedicated pin HSWAP_EN controls the pull-upresistors prior to configuration. By default, HSWAP_EN isset high, which disables the pull-up resistors on user I/Opins. When HSWAP_EN is set low, the pull-up resistors areactivated on user I/O pins.

All Virtex-II IOBs support IEEE 1149.1 compatible boundaryscan testing.

Input Path

The Virtex-II IOB input path routes input signals directly tointernal logic and / or through an optional input flip-flop orlatch, or through the DDR input registers. An optional delayelement at the D-input of the storage element eliminatespad-to-pad hold time. The delay is matched to the internalclock-distribution delay of the Virtex-II device, and whenused, assures that the pad-to-pad hold time is zero.

Each input buffer can be configured to conform to any of thelow-voltage signaling standards supported. In some ofthese standards the input buffer utilizes a user-suppliedthreshold voltage, VREF. The need to supply VREF imposesconstraints on which standards can be used in the samebank. See I/O banking description.

Output Path

The output path includes a 3-state output buffer that drivesthe output signal onto the pad. The output and / or the3-state signal can be routed to the buffer directly from theinternal logic or through an output / 3-state flip-flop or latch,or through the DDR output / 3-state registers.

Each output driver can be individually programmed for awide range of low-voltage signaling standards. In most sig-naling standards, the output High voltage depends on anexternally supplied VCCO voltage. The need to supply VCCOimposes constraints on which standards can be used in thesame bank. See I/O banking description.

I/O Banking

Some of the I/O standards described above require VCCOand VREF voltages. These voltages are externally suppliedand connected to device pins that serve groups of IOBblocks, called banks. Consequently, restrictions exist aboutwhich I/O standards can be combined within a given bank.

Eight I/O banks result from dividing each edge of the FPGAinto two banks, as shown in Figure 7 and Figure 8. Eachbank has multiple VCCO pins, all of which must be con-nected to the same voltage. This voltage is determined bythe output standards in use.

Table 4: LVTTL and LVCMOS Programmable Currents (Sink and Source)

SelectI/O-Ultra Programmable Current (Worst-Case Guaranteed Minimum)

LVTTL 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA

LVCMOS33 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA

LVCMOS25 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA

LVCMOS18 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a

LVCMOS15 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a

Figure 6: SSTL or HSTL SelectI/O-Ultra Standards

VCCO

OBUF

VREF

ClampDiode

PAD

VCCAUX = 3.3VVCCINT = 1.5V

DS031_24_100900




Some input standards require a user-supplied thresholdvoltage (VREF), and certain user-I/O pins are automaticallyconfigured as VREF inputs. Approximately one in six of theI/O pins in the bank assume this role.

VREF pins within a bank are interconnected internally, andconsequently only one VREF voltage can be used withineach bank. However, for correct operation, all VREF pins inthe bank must be connected to the external reference volt-age source.

The VCCO and the VREF pins for each bank appear in thedevice pinout tables. Within a given package, the number ofVREF and VCCO pins can vary depending on the size ofdevice. In larger devices, more I/O pins convert to VREFpins. Since these are always a superset of the VREF pinsused for smaller devices, it is possible to design a PCB thatpermits migration to a larger device if necessary.

All VREF pins for the largest device anticipated must be con-nected to the VREF voltage and not used for I/O. In smaller

devices, some VCCO pins used in larger devices do not con-nect within the package. These unconnected pins can beleft unconnected externally, or, if necessary, they can beconnected to VCCO to permit migration to a larger device.

Rules for Combining I/O Standards in the Same Bank

The following rules must be obeyed to combine differentinput, output, and bi-directional standards in the same bank:

1. Combining output standards only. Output standards with the same output VCCO requirement can be combined in the same bank. Compatible example:

SSTL2_I and LVDS_25_DCI outputsIncompatible example:

SSTL2_I (output VCCO = 2.5V) and LVCMOS33 (output VCCO = 3.3V) outputs

2. Combining input standards only. Input standards with the same input VCCO and input VREF requirements can be combined in the same bank.Compatible example:

LVCMOS15 and HSTL_IV inputsIncompatible example:

LVCMOS15 (input VCCO = 1.5V) and LVCMOS18 (input VCCO = 1.8V) inputs

Incompatible example:HSTL_I_DCI_18 (VREF = 0.9V) and HSTL_IV_DCI_18 (VREF = 1.1V) inputs

3. Combining input standards and output standards. Input standards and output standards with the same input VCCO and output VCCO requirement can be combined in the same bank. Compatible example:

LVDS_25 output and HSTL_I inputIncompatible example:

LVDS_25 output (output VCCO = 2.5V) and HSTL_I_DCI_18 input (input VCCO = 1.8V)

4. Combining bi-directional standards with input or output standards. When combining bi-directional I/O with other standards, make sure the bi-directional standard can meet rules 1 through 3 above.

5. Additional rules for combining DCI I/O standards.

a. No more than one Single Termination type (input oroutput) is allowed in the same bank.Incompatible example:

HSTL_IV_DCI input and HSTL_III_DCI input

b. No more than one Split Termination type (input or output) is allowed in the same bank.Incompatible example:

HSTL_I_DCI input and HSTL_II_DCI input

The implementation tools will enforce these design rules.

Table 5 summarizes all standards and voltage supplies.

Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond Packages (CS/CSG, FG/FGG, & BG/BGG)

Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip Packages (FF & BF)

ug002_c2_014_112900

Bank 0 Bank 1

Bank 5 Bank 4

Ban

k 7

Ban

k 6

Ban

k 2

Ban

k 3

ds031_66_112900

Bank 1 Bank 0

Bank 4 Bank 5

Ban

k 2

Ban

k 3

Ban

k 7

Ban

k 6




Table 5: Summary of Voltage Supply Requirements for All Input and Output Standards

I/O Standard

VCCO VREF Termination Type

Output Input Input Output Input

LVDS_33

3.3

N/R

N/R(1) N/R N/R

LVDSEXT_33 N/R N/R N/R

LVPECL_33 N/R N/R N/R

SSTL3_I 1.5 N/R N/R

SSTL3_II 1.5 N/R N/R

AGP 1.32 N/R N/R

LVTTL

3.3

N/R N/R N/R

LVCMOS33 N/R N/R N/R

LVDCI_33 N/R Series N/R

LVDCI_DV2_33 N/R Series N/R

PCI33_3 N/R N/R N/R

PCI66_3 N/R N/R N/R

PCIX N/R N/R N/R

SSTL3_I_DCI 1.5 N/R Split

SSTL3_II_DCI 1.5 Split Split

LVDS_25

2.5

N/R

N/R N/R N/R

LVDSEXT_25 N/R N/R N/R

LDT_25 N/R N/R N/R

ULVDS_25 N/R N/R N/R

BLVDS_25 N/R N/R N/R

SSTL2_I 1.25 N/R N/R


LVCMOS25

2.5

N/R N/R N/R



LVDS_25_DCI N/R N/R Split

LVDSEXT_25_DCI

N/R N/R Split



HSTL_III_18

1.8

N/R

1.1 N/R N/R

HSTL_IV_18 1.1 N/R N/R

HSTL_I_18 0.9 N/R N/R

HSTL_II_18 0.9 N/R N/R

SSTL18_I 0.9 N/R N/R


LVCMOS18

1.8

N/R N/R N/R



HSTL_III_DCI_18 1.1 N/R Single

HSTL_IV_DCI_18 1.1 Single Single

HSTL_I_DCI_18 0.9 N/R Split

HSTL_II_DCI_18 0.9 Split Split



HSTL_III

1.5

N/R

0.9 N/R N/R

HSTL_IV 0.9 N/R N/R

HSTL_I 0.75 N/R N/R

HSTL_II 0.75 N/R N/R

LVCMOS15

1.5

N/R N/R N/R



GTLP_DCI 1 Single Single

HSTL_III_DCI 0.9 N/R Single

HSTL_IV_DCI 0.9 Single Single

HSTL_I_DCI 0.75 N/R Split

HSTL_II_DCI 0.75 Split Split

GTL_DCI 1.2 1.2 0.8 Single Single

GTLPN/R N/R

1 N/R N/R

GTL 0.8 N/R N/R

Notes: 1. N/R = no requirement.

Table 5: Summary of Voltage Supply Requirements for All Input and Output Standards (Continued)

I/O Standard

VCCO VREF Termination Type

Output Input Input Output Input




Digitally Controlled Impedance (DCI)Today’s chip output signals with fast edge rates require ter-mination to prevent reflections and maintain signal integrity.High pin count packages (especially ball grid arrays) cannot accommodate external termination resistors.

Virtex-II XCITE DCI provides controlled impedance driversand on-chip termination for single-ended and differentialI/Os. This eliminates the need for external resistors, andimproves signal integrity. The DCI feature can be used onany IOB by selecting one of the DCI I/O standards.

When applied to inputs, DCI provides input parallel termina-tion. When applied to outputs, DCI provides controlledimpedance drivers (series termination) or output paralleltermination.

DCI operates independently on each I/O bank. When a DCII/O standard is used in a particular I/O bank, external refer-ence resistors must be connected to two dual-function pinson the bank. These resistors, voltage reference of N transis-tor (VRN) and the voltage reference of P transistor (VRP)are shown in Figure 9.

When used with a terminated I/O standard, the value ofresistors are specified by the standard (typically 50Ω).When used with a controlled impedance driver, the resistorsset the output impedance of the driver within the specifiedrange (25Ω to 100Ω). For all series and parallel termina-tions listed in Table 6 and Table 7, the reference resistorsmust have the same value for any given bank. One percentresistors are recommended.

The DCI system adjusts the I/O impedance to match thetwo external reference resistors, or half of the referenceresistors, and compensates for impedance changes due tovoltage and/or temperature fluctuations. The adjustment isdone by turning parallel transistors in the IOB on or off.

Controlled Impedance Drivers (Series Term.)

DCI can be used to provide a buffer with a controlled outputimpedance. It is desirable for this output impedance tomatch the transmission line impedance (Z0). Virtex-II inputbuffers also support LVDCI and LVDCI_DV2 I/O standards.

Controlled Impedance Drivers (Parallel)

DCI also provides on-chip termination for SSTL3, SSTL2,HSTL (Class I, II, III, or IV), and GTL/GTLP receivers ortransmitters on bidirectional lines.Table 7 and Table 8 list the on-chip parallel terminationsavailable in Virtex-II devices. VCCO must be set according toTable 3. Note that there is a VCCO requirement for GTL_DCIand GTLP_DCI, due to the on-chip termination resistor.

Figure 9: DCI in a Virtex-II BankDS031_50_101200

VCCO

GND

DCI

DCI

DCI

DCI

VRN

VRP

1 Bank

RREF (1%)

RREF (1%)

Figure 10: Internal Series Termination

Table 6: SelectI/O-Ultra Controlled Impedance Buffers

VCCO DCI DCI Half Impedance

3.3 V LVDCI_33 LVDCI_DV2_33




Table 7: SelectI/O-Ultra Buffers With On-Chip Parallel Termination

I/O Standard Description


External Termination

On-Chip Termination

SSTL3 Class I SSTL3_I SSTL3_I_DCI(1)

SSTL3 Class II SSTL3_II SSTL3_II_DCI(1)

SSTL2 Class I SSTL2_I SSTL2_I_DCI(1)

SSTL2 Class II SSTL2_II SSTL2_II_DCI(1)

HSTL Class I HSTL_I HSTL_I_DCI

HSTL Class II HSTL_II HSTL_II_DCI

HSTL Class III HSTL_III HSTL_III_DCI

HSTL Class IV HSTL_IV HSTL_IV_DCI

GTL GTL GTL_DCI

GTLP GTLP GTLP_DCI

Notes: 1. SSTL-compatible

Z

IOB

Z

Virtex-II DCI

DS031_51_110600VCCO = 3.3 V, 2.5 V, 1.8 V or 1.5 V




Figure 11 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/Ostandards. For a complete list, see the Virtex-II Platform FPGA User Guide.

Table 8: SelectI/O-Ultra Differential Buffers With On-Chip Termination

I/O Standard Description


External Termination On-Chip Termination

LVDS 2.5V LVDS_25 LVDS_25_DCI

LVDS Extended 2.5V LVDSEXT_25 LVDSEXT_25_DCI

Figure 11: HSTL DCI Usage Examples

Virtex-II DCI

R R

VCCO VCCO

R R

VCCO VCCO

R

VCCO

R

VCCO

Virtex-II DCI

Virtex-II DCI

R

VCCO

R

VCCO

Virtex-II DCI

R R

VCCO/2 VCCO/2

2R

Virtex-II DCI

2R

R

VCCO VCCO/2

Virtex-II DCI

2R

R

VCCO/2

2R

VCCO

2R

Virtex-II DCI

2R

VCCO

Virtex-II DCI

2R

2R

VCCO

DS031_65a_100201

Conventional

DCI TransmitConventionalReceive

ConventionalTransmitDCI Receive

DCI TransmitDCI Receive

Bidirectional

ReferenceResistor

RecommendedZ0

(1)

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

HSTL_I HSTL_II HSTL_III HSTL_IV

N/A N/A

Virtex-II DCI

R

VCCO

R

VCCO

R

VCCO

Virtex-II DCI

R

VCCO

Virtex-II DCI

Z0

R

VCCO/2

Virtex-II DCI

R

VCCO/2

Virtex-II DCI

2R

2R

VCCO

Virtex-II DCIVirtex-II DCI

2R

2R

VCCO

Z0

Z0

Z0

Z0Z0

Z0Z0

Z0

Z0Z0Z0

Z0

Z0

Z0

Z0

Virtex-II DCI

Virtex-II DCI

Z0

Virtex-II DCI

2R

2R

VCCO

2R

2R

VCCO

Virtex-II DCI

Z0

Virtex-II DCI

R

VCCO

R

VCCO

Note:1. Z0 is the recommended PCB trace impedance.

http://www.xilinx.comhttp://www.xilinx.com/bvdocs/guides/ug002.pdf



Figure 12 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/Ostandards. For a complete list, see the Virtex-II Platform FPGA User Guide.

Figure 12: SSTL DCI Usage Examples

DS031_65b_112502

Conventional

DCI TransmitConventionalReceive


DCI TransmitDCI Receive

Bidirectional

ReferenceResistor

Recommended Z0

(2)

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

SSTL2_I SSTL2_II SSTL3_I SSTL3_II

N/A N/A

Virtex-II DCI

Z0

R

VCCO/2

Z0R/2

R R

VCCO/2 VCCO/2

Z0R/2

R R

VCCO/2 VCCO/2

Z0R/2

R

VCCO/2

Z0R/2

R

VCCO/2

Z0R/2

Virtex-II DCI

2R

2R

VCCO

R

VCCO/2

Z0R/2

Virtex-II DCI

2R

2R

VCCO

Z0R/2

Virtex-II DCI

2R

2R

VCCO

Z0R/2

Virtex-II DCI

2R

2R

VCCO

Virtex-II DCI

R

VCCO VCCO/2

2R

Virtex-II DCI

R

VCCO VCCO/2

2R

Virtex-II DCI

R

VCCO/2

Z0 Z0Z0

Virtex-II DCI

R

VCCO/2

Z02R

2R

2R

Virtex-II DCI

2R

VCCO

Virtex-II DCI

2R

2R

VCCO

Z0

Virtex-II DCIVirtex-II DCI

2R

2R

VCCO

Z0

2R

Virtex-II DCI

2R

VCCO

Virtex-II DCI

2R

2R

VCCO

Z0

Virtex-II DCI

2R

2R

VCCO

Virtex-II DCI

Z0

Virtex-II DCI

2R

2R

VCCO

2R

2R

VCCO

Virtex-II DCI

Z0

Virtex-II DCI

2R

2R

VCCO

2R

2R

VCCO

25Ω(1)

25Ω(1) 25Ω(1)

25Ω(1)

25Ω(1)

25Ω(1)

25Ω(1)

25Ω(1)

25Ω(1)

25Ω(1)

25Ω(1)

25Ω(1)

Notes:1. The SSTL-compatible 25Ω series resistor is accounted for in the DCI buffer, and it is not DCI controlled.2. Z0 is the recommended PCB trace impedance.




Figure 13 provides examples illustrating the use of the LVDS_DCI and LVDSEXT_DCI I/O standards. For a complete list,see the Virtex-II Platform FPGA User Guide.

Figure 13: LVDS DCI Usage Examples

DS031_65c_022103

Conventional


ReferenceResistor

RecommendedZ0

VRN = VRP = R = Z0

50 Ω

LVDS_DCI and LVDSEXT_DCI Receiver

Virtex-II LVDS DCI

Z0

2R

2R

VCCO

Z0

2R

2R

VCCO

Virtex-II LVDS

Z0

2R

Z0

NOTE: Only LVDS25_DCI is supported (VCCO = 2.5V only)




Configurable Logic Blocks (CLBs)The Virtex-II configurable logic blocks (CLB) are organizedin an array and are used to build combinatorial and synchro-nous logic designs. Each CLB element is tied to a switchmatrix to access the general routing matrix, as shown inFigure 14. A CLB element comprises 4 similar slices, withfast local feedback within the CLB. The four slices are splitin two columns of two slices with two independent carrylogic chains and one common shift chain.

Slice Description

Each slice includes two 4-input function generators, carrylogic, arithmetic logic gates, wide function multiplexers andtwo storage elements. As shown in Figure 15, each 4-inputfunction generator is programmable as a 4-input LUT, 16bits of distributed SelectRAM memory, or a 16-bit vari-able-tap shift register element.

The output from the function generator in each slice drives both the slice output and the D input of the storage element. Figure 16 shows a more detailed view of a single slice.

Configurations

Look-Up Table

Virtex-II function generators are implemented as 4-inputlook-up tables (LUTs). Four independent inputs are pro-vided to each of the two function generators in a slice (F andG). These function generators are each capable of imple-menting any arbitrarily defined boolean function of fourinputs. The propagation delay is therefore independent ofthe function implemented. Signals from the function gener-ators can exit the slice (X or Y output), can input the XORdedicated gate (see arithmetic logic), or input the carry-logicmultiplexer (see fast look-ahead carry logic), or feed the Dinput of the storage element, or go to the MUXF5 (notshown in Figure 16).

In addition to the basic LUTs, the Virtex-II slice containslogic (MUXF5 and MUXFX multiplexers) that combinesfunction generators to provide any function of five, six,seven, or eight inputs. The MUXFX are either MUXF6,MUXF7 or MUXF8 according to the slice considered in theCLB. Selected functions up to nine inputs (MUXF5 multi-plexer) can be implemented in one slice. The MUXFX canalso be a MUXF6, MUXF7, or MUXF8 multiplexers to mapany functions of six, seven, or eight inputs and selectedwide logic functions.

Register/Latch

The storage elements in a Virtex-II slice can be configuredeither as edge-triggered D-type flip-flops or as level-sensi-tive latches. The D input can be directly driven by the X or Youtput via the DX or DY input, or by the slice inputs bypass-ing the function generators via the BX or BY input. Theclock enable signal (CE) is active High by default. If leftunconnected, the clock enable for that storage elementdefaults to the active state.

In addition to clock (CK) and clock enable (CE) signals,each slice has set and reset signals (SR and BY sliceinputs). SR forces the storage element into the state speci-fied by the attribute SRHIGH or SRLOW. SRHIGH forces alogic “1” when SR is asserted. SRLOW forces a logic “0”.When SR is used, a second input (BY) forces the storageelement into the opposite state. The reset condition is pre-dominant over the set condition. (See Figure 17.)

The initial state after configuration or global initial state isdefined by a separate INIT0 and INIT1 attribute. By default,setting the SRLOW attribute sets INIT0, and setting theSRHIGH attribute sets INIT1. For each slice, set and resetcan be set to be synchronous or asynchronous. Virtex-IIdevices also have the ability to set INIT0 and INIT1 inde-pendent of SRHIGH and SRLOW.

The control signals clock (CLK), clock enable (CE) andset/reset (SR) are common to both storage elements in oneslice. All of the control signals have independent polarity. Anyinverter placed on a control input is automatically absorbed.

Figure 14: Virtex-II CLB Element

Figure 15: Virtex-II Slice Configuration

SliceX1Y1

SliceX1Y0

SliceX0Y1

SliceX0Y0

FastConnectsto neighbors

SwitchMatrix

DS031_32_101600

SHIFTCIN

COUT

TBUF X0Y1COUT

CIN

TBUF X0Y0

Register

MUXF5

MUXFx

CYSRL16

RAM16

LUTG

Register

Arithmetic Logic

CYLUT

F

DS031_31_100900

SRL16

RAM16

ORCY




Figure 16: Virtex-II Slice (Top Half)

G4

SOPIN

A4G3 A3G2 A2G1 A1

WG4 WG4WG3 WG3WG2 WG2WG1

BY

WG1

Dual-Port

LUT

FFLATCH

RAMROM

Shift-Reg

D

0

MC15

WS

SR

SR

REV

DI

G

Y

G2

G1BY

10

PROD

D Q

CECECKCLK

MUXCYYB

DIG

DY

Y

0 1

MUXCY0 1

1

SOPOUT

DYMUX

GYMUX

YBMUX

ORCY

WSGWE[2:0]

SHIFTOUT

CYOG

XORG

WECLK

WSF

ALTDIG

CE

SR

CLK

SLICEWE[2:0]

MULTAND

Shared betweenx & y Registers

SHIFTIN COUT

CIN DS031_01_112502

Q




The set and reset functionality of a register or a latch can beconfigured as follows:

• No set or reset• Synchronous set• Synchronous reset• Synchronous set and reset• Asynchronous set (preset)• Asynchronous reset (clear)• Asynchronous set and reset (preset and clear)

The synchronous reset has precedence over a set, and anasynchronous clear has precedence over a preset.

Distributed SelectRAM Memory

Each function generator (LUT) can implement a 16 x 1-bitsynchronous RAM resource called a distributed SelectRAMelement. The SelectRAM elements are configurable withina CLB to implement the following:

• Single-Port 16 x 8 bit RAM• Single-Port 32 x 4 bit RAM• Single-Port 64 x 2 bit RAM• Single-Port 128 x 1 bit RAM• Dual-Port 16 x 4 bit RAM• Dual-Port 32 x 2 bit RAM• Dual-Port 64 x 1 bit RAM

Distributed SelectRAM memory modules are synchronous(write) resources. The combinatorial read access time isextremely fast, while the synchronous write simplifieshigh-speed designs. A synchronous read can be imple-mented with a storage element in the same slice. The dis-tributed SelectRAM memory and the storage element sharethe same clock input. A Write Enable (WE) input is activeHigh, and is driven by the SR input.

Table 9 shows the number of LUTs (2 per slice) occupiedby each distributed SelectRAM configuration.

For single-port configurations, distributed SelectRAM mem-ory has one address port for synchronous writes and asyn-chronous reads.

For dual-port configurations, distributed SelectRAM mem-ory has one port for synchronous writes and asynchronousreads and another port for asynchronous reads. The func-tion generator (LUT) has separated read address inputs(A1, A2, A3, A4) and write address inputs (WG1/WF1,WG2/WF2, WG3/WF3, WG4/WF4).

In single-port mode, read and write addresses share thesame address bus. In dual-port mode, one function genera-tor (R/W port) is connected with shared read and writeaddresses. The second function generator has the A inputs(read) connected to the second read-only port address andthe W inputs (write) shared with the first read/write portaddress.

Figure 17: Register / Latch Configuration in a Slice

FF

FFY

LATCH

SR REV

D Q

CE

CK

YQ

FF

FFX

LATCH

SR REV

D Q

CE

CK

XQ

CE

DX

DY

BY

CLK

BX

SR

Attribute

INIT1INIT0SRHIGHSRLOW

Attribute

INIT1INIT0SRHIGHSRLOW

Reset TypeSYNCASYNC

DS031_22_110600

Table 9: Distributed SelectRAM Configurations

RAM Number of LUTs

16 x 1S 1

16 x 1D 2

32 x 1S 2

32 x 1D 4

64 x 1S 4

64 x 1D 8

128 x 1S 8

Notes: 1. S = single-port configuration; D = dual-port configuration




Figure 18, Figure 19, and Figure 20 illustrate various exam-ple configurations.

Similar to the RAM configuration, each function generator(LUT) can implement a 16 x 1-bit ROM. Five configurationsare available: ROM16x1, ROM32x1, ROM64x1,ROM128x1, and ROM256x1. The ROM elements are cas-cadable to implement wider or/and deeper ROM. ROM con-tents are loaded at configuration. Table 10 shows thenumber of LUTs occupied by each configuration.

Figure 18: Distributed SelectRAM (RAM16x1S)

Figure 19: Single-Port Distributed SelectRAM (RAM32x1S)

A[3:0]

D

D

DIWS

WSG

WEWCLK

RAM 16x1S

D Q

RAM

WECK

A[4:1]

WG[4:1]

Output

RegisteredOutput

(optional)

(SR)

4

4

(BY)

DS031_02_100900

A[3:0]

D

WSG

F5MUX

WEWCLK

RAM 32x1S

D Q

WEWE0

CKWSF

D

DIWS

RAM

G[4:1]

A[4]

WG[4:1]

D

DIWSRAM

F[4:1]

WF[4:1]

Output

RegisteredOutput

(optional)

(SR)

4

(BY)

(BX)

4

DS031_03_110100

Figure 20: Dual-Port Distributed SelectRAM (RAM16x1D)

Table 10: ROM Configuration

ROM Number of LUTs

16 x 1 1

32 x 1 2

64 x 1 4

128 x 1 8 (1 CLB)

256 x 1 16 (2 CLBs)

A[3:0]

D

WSG

WEWCLK

RAM 16x1D

WECK

D

DIWS

RAMG[4:1]

WG[4:1]

dual_port

RAMdual_port

4

(BY)

DPRA[3:0]

SPO

A[3:0]

WSG

WECK

D

DIWS

G[4:1]

WG[4:1]

DPO4

4

DS031_04_110100

(SR)




Shift Registers

Each function generator can also be configured as a 16-bitshift register. The write operation is synchronous with aclock input (CLK) and an optional clock enable, as shown inFigure 21. A dynamic read access is performed through the4-bit address bus, A[3:0]. The configurable 16-bit shift reg-ister cannot be set or reset. The read is asynchronous, how-ever the storage element or flip-flop is available toimplement a synchronous read. The storage elementshould always be used with a constant address. For exam-ple, when building an 8-bit shift register and configuring theaddresses to point to the 7th bit, the 8th bit can be theflip-flop. The overall system performance is improved byusing the superior clock-to-out of the flip-flops.

An additional dedicated connection between shift registersallows connecting the last bit of one shift register to the firstbit of the next, without using the ordinary LUT output. (SeeFigure 22.) Longer shift registers can be built with dynamicaccess to any bit in the chain. The shift register chainingand the MUXF5, MUXF6, and MUXF7 multiplexers allow upto a 128-bit shift register with addressable access to beimplemented in one CLB.

Figure 21: Shift Register Configurations

A[3:0]

SHIFTIN

SHIFTOUT

D(BY)

D

MC15

DI

WSG

CE (SR)CLK

SRLC16

D Q

SHIFT-REG

WECK

A[4:1] Output

RegisteredOutput

(optional)

4

DS031_05_110600

WS

Figure 22: Cascadable Shift Register

SRLC16MC15

MC15

D

SRLC16DI

SHIFTIN

CASCADABLE OUT

SLICE S0

SLICE S1

SLICE S2

SLICE S3

1 Shift Chainin CLB

CLB

DS031_06_110200

FF

FFD

SRLC16MC15

MC15

D

SRLC16DI

SHIFTIN

SHIFTOUT

FF

FFD

SRLC16MC15

MC15

D

SRLC16

DI

DI

SHIFTIN

IN

SHIFTOUT

FF

FFD

SRLC16MC15

MC15

D

SRLC16

DI

SHIFTOUT

FF

FFD

DI

DI

DI

OUT




Multiplexers

Virtex-II function generators and associated multiplexerscan implement the following:

• 4:1 multiplexer in one slice• 8:1 multiplexer in two slices• 16:1 multiplexer in one CLB element (4 slices) • 32:1 multiplexer in two CLB elements (8 slices)

Each Virtex-II slice has one MUXF5 multiplexer and oneMUXFX multiplexer. The MUXFX multiplexer implementsthe MUXF6, MUXF7, or MUXF8, as shown in Figure 23.Each CLB element has two MUXF6 multiplexers, oneMUXF7 multiplexer and one MUXF8 multiplexer. Examplesof multiplexers are shown in the Virtex-II Platform FPGAUser Guide. Any LUT can implement a 2:1 multiplexer.

Fast Lookahead Carry Logic

Dedicated carry logic provides fast arithmetic addition andsubtraction. The Virtex-II CLB has two separate carrychains, as shown in the Figure 24.

The height of the carry chains is two bits per slice. The carrychain in the Virtex-II device is running upward. The dedi-cated carry path and carry multiplexer (MUXCY) can also

be used to cascade function generators for implementingwide logic functions.

Arithmetic LogicThe arithmetic logic includes an XOR gate that allows a2-bit full adder to be implemented within a slice. In addition,a dedicated AND (MULT_AND) gate (shown in Figure 16)improves the efficiency of multiplier implementation.

Figure 23: MUXF5 and MUXFX multiplexers

Slice S1

Slice S0

Slice S3

Slice S2

CLB

DS031_08_100201

F5

F6

F5

F7

F5

F6

F5

F8

MUXF8 combines the two MUXF7 outputs (Two CLBs)

MUXF6 combines the two MUXF5 outputs from slices S2 and S3

MUXF7 combines the two MUXF6 outputs from slices S0 and S2

MUXF6 combines the two MUXF5outputs from slices S0 and S1

G

F

G

F

G

F

G

F




Figure 24: Fast Carry Logic Path

FFLUT

O I MUXCY

FFLUT

O I MUXCY

FFLUT

O I MUXCY

FFLUT

O I MUXCY

CIN

CIN CIN

COUT

FFLUT

O I MUXCY

FFLUT

O I MUXCY

FFLUT

O I MUXCY

FFLUT

O I MUXCY

CIN

COUT

COUTto CIN of S2 of the next CLB

COUTto S0 of the next CLB

(First Carry Chain)

(Second Carry Chain)

SLICE S1

SLICE S0

SLICE S3

SLICE S2

CLB

DS031_07_110200




Sum of Products

Each Virtex-II slice has a dedicated OR gate named ORCY,ORing together outputs from the slices carryout and the ORCYfrom an adjacent slice. The ORCY gate with the dedicatedSum of Products (SOP) chain are designed for implementing

large, flexible SOP chains. One input of each ORCY is con-nected through the fast SOP chain to the output of the previ-ous ORCY in the same slice row. The second input isconnected to the output of the top MUXCY in the same slice,as shown in Figure 25.

LUTs and MUXCYs can implement large AND gates orother combinatorial logic functions. Figure 26 illustrates

LUT and MUXCY resources configured as a 16-input ANDgate.

Figure 25: Horizontal Cascade Chain

MUXCY4

MUXCY4

Slice 1

ds031_64_110300

ORCY

LUT

LUT

MUXCY4

MUXCY4

Slice 0

VCC

LUT

LUT

MUXCY4

MUXCY4

Slice 3

ORCY

LUT

LUT

MUXCY4

MUXCY4

Slice 2

VCC

LUT

LUT

SOP

CLB

MUXCY4

MUXCY4

Slice 1

ORCY

LUT

LUT

MUXCY4

MUXCY4

Slice 0

VCC

LUT

LUT

MUXCY4

MUXCY4

Slice 3

ORCY

LUT

LUT

MUXCY4

MUXCY4

Slice 2

VCC

LUT

LUT

CLB

Figure 26: Wide-Input AND Gate (16 Inputs)

MUXCY

AND

4

16

MUXCY4

“0”

0 1

0 1

“0”

0 1

“0”

MUXCY4

Slice

OUT

OUT

Slice

LUT

DS031_41_110600

LUT

LUT

VCC

MUXCY4

0 1LUT




3-State Buffers

Introduction

Each Virtex-II CLB contains two 3-state drivers (TBUFs)that can drive on-chip busses. Each 3-state buffer has itsown 3-state control pin and its own input pin.

Each of the four slices have access to the two 3-state buff-ers through the switch matrix, as shown in Figure 27.TBUFs in neighboring CLBs can access slice outputs bydirect connects. The outputs of the 3-state buffers drive hor-izontal routing resources used to implement 3-state busses.

The 3-state buffer logic is implemented using AND-OR logicrather than 3-state drivers, so that timing is more predict-able and less load dependant especially with largerdevices.

Locations / Organization

Four horizontal routing resources per CLB are provided foron-chip 3-state busses. Each 3-state buffer has accessalternately to two horizontal lines, which can be partitionedas shown in Figure 28. The switch matrices correspondingto SelectRAM memory and multiplier or I/O blocks areskipped.

Number of 3-State Buffers

Table 11 shows the number of 3-state buffers available ineach Virtex-II device. The number of 3-state buffers is twicethe number of CLB elements.

CLB/Slice Configurations

Table 12 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can beimplemented in one of the configurations listed. Table 13 shows the available resources in all CLBs.

Figure 27: Virtex-II 3-State Buffers

SliceS3

SliceS2

SliceS1

SliceS0

SwitchMatrix

DS031_37_060700

TBUF

TBUF

Table 11: Virtex-II 3-State Buffers

Device3-State Buffers

per RowTotal Number

of 3-State Buffers

XC2V40 16 128

XC2V80 16 256

XC2V250 32 768

XC2V500 48 1,536

XC2V1000 64 2,560

XC2V1500 80 3,840

XC2V2000 96 5,376

XC2V3000 112 7,168

XC2V4000 144 11,520

XC2V6000 176 16,896

XC2V8000 208 23,296

Figure 28: 3-State Buffer Connection to Horizontal Lines

SwitchmatrixCLB-II

SwitchmatrixCLB-II

DS031_09_032700

Programmableconnection

3 - state lines

Table 12: Logic Resources in One CLB

Slices LUTs Flip-Flops MULT_ANDsArithmetic & Carry-Chains

SOP Chains

Distributed SelectRAM

Shift Registers TBUF

4 8 8 8 2 2 128 bits 128 bits 2




18 Kbit Block SelectRAM Resources

Introduction

Virtex-II devices incorporate large amounts of 18 Kbit blockSelectRAM. These complement the distributed SelectRAMresources that provide shallow RAM structures imple-mented in CLBs. Each Virtex-II block SelectRAM is an 18Kbit true dual-port RAM with two independently clocked andindependently controlled synchronous ports that access acommon storage area. Both ports are functionally identical.CLK, EN, WE, and SSR polarities are defined through con-figuration.

Each port has the following types of inputs: Clock and ClockEnable, Write Enable, Set/Reset, and Address, as well asseparate Data/parity data inputs (for write) and Data/paritydata outputs (for read).

Operation is synchronous; the block SelectRAM behaveslike a register. Control, address and data inputs must (andneed only) be valid during the set-up time window prior to arising (or falling, a configuration option) clock edge. Dataoutputs change as a result of the same clock edge.

Configuration

The Virtex-II block SelectRAM supports various configura-tions, including single- and dual-port RAM and variousdata/address aspect ratios. Supported memory configura-

tions for single- and dual-port modes are shown inTable 14.

Single-Port Configuration

As a single-port RAM, the block SelectRAM has access tothe 18 Kbit memory locations in any of the 2K x 9-bit,1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbitmemory locations in any of the 16K x 1-bit, 8K x 2-bit, or4K x 4-bit configurations. The advantage of the 9-bit, 18-bitand 36-bit widths is the ability to store a parity bit for eacheight bits. Parity bits must be generated or checked exter-nally in user logic. In such cases, the width is viewed as 8 +1, 16 + 2, or 32 + 4. These extra parity bits are stored andbehave exactly as the other bits, including the timingparameters. Video applications can use the 9-bit ratio ofVirtex-II block SelectRAM memory to advantage.

Each block SelectRAM cell is a fully synchronous memoryas illustrated in Figure 29. Input data bus and output databus widths are identical.

Table 13: Virtex-II Logic Resources Available in All CLBs

Device

CLB Array: Row x

Column

Number of

Slices

Number of

LUTs

Max Distributed SelectRAM or Shift

Register (bits)

Number of

Flip-Flops

Number of

Carry-Chains(1)

Number of SOP

Chains(1)

XC2V40 8 x 8 256 512 8,192 512 16 16

XC2V80 16 x 8 512 1,024 16,384 1,024 16 32

XC2V250 24 x 16 1,536 3,072 49,152 3,072 32 48

XC2V500 32 x 24 3,072 6,144 98,304 6,144 48 64

XC2V1000 40 x 32 5,120 10,240 163,840 10,240 64 80

XC2V1500 48 x 40 7,680 15,360 245,760 15,360 80 96

XC2V2000 56 x 48 10,752 21,504 344,064 21,504 96 112

XC2V3000 64 x 56 14,336 28,672 458,752 28,672 112 128

XC2V4000 80 x 72 23,040 46,080 737,280 46,080 144 160

XC2V6000 96 x 88 33,792 67,584 1,081,344 67,584 176 192

XC2V8000 112 x 104 46,592 93,184 1,490,944 93,184 208 224

Notes: 1. The carry-chains and SOP chains can be split or cascaded.

Table 14: Dual- and Single-Port Configurations

16K x 1 bit 2K x 9 bits

8K x 2 bits 1K x 18 bits

4K x 4 bits 512 x 36 bits




Dual-Port Configuration

As a dual-port RAM, each port of block SelectRAM hasaccess to a common 18 Kbit memory resource. These arefully synchronous ports with independent control signals foreach port. The data widths of the two ports can be config-ured independently, providing built-in bus-width conversion.

Table 15 illustrates the different configurations available onports A and B.

If both ports are configured in either 2K x 9-bit, 1K x 18-bit,or 512 x 36-bit configurations, the 18 Kbit block is accessi-ble from port A or B. If both ports are configured in either16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the16 K-bit block is accessible from Port A or Port B. All otherconfigurations result in one port having access to an 18 Kbitmemory block and the other port having access to a 16 K-bitsubset of the memory block equal to 16 Kbits.

Figure 29: 18 Kbit Block SelectRAM Memory in Single-Port Mode

DOP

DIP

ADDR

WE

ENSSR

CLK

18 Kbit Block SelectRAM

DS031_10_071602

DI

DO

Table 15: Dual-Port Mode Configurations

Port A 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1

Port B 16K x 1 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36

Port A 8K x 2 8K x 2 8K x 2 8K x 2 8K x 2

Port B 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36

Port A 4K x 4 4K x 4 4K x 4 4K x 4

Port B 4K x 4 2K x 9 1K x 18 512 x 36

Port A 2K x 9 2K x 9 2K x 9

Port B 2K x 9 1K x 18 512 x 36

Port A 1K x 18 1K x 18

Port B 1K x 18 512 x 36

Port A 512 x 36

Port B 512 x 36




Each block SelectRAM cell is a fully synchronous memory,as illustrated in Figure 30. The two ports have independentinputs and outputs and are independently clocked.

Port Aspect Ratios

Table 16 shows the depth and the width aspect ratios for the18 Kbit block SelectRAM. Virtex-II block SelectRAM alsoincludes dedicated routing resources to provide an efficientinterface with CLBs, block SelectRAM, and multipliers.

Read/Write Operations

The Virtex-II block SelectRAM read operation is fully syn-chronous. An address is presented, and the read operationis enabled by control signals WEA and WEB in addition toENA or ENB. Then, depending on clock polarity, a rising orfalling clock edge causes the stored data to be loaded intooutput registers.

The write operation is also fully synchronous. Data andaddress are presented, and the write operation is enabledby control signals WEA or WEB in addition to ENA or ENB.Then, again depending on the clock input mode, a rising or

falling clock edge causes the data to be loaded into thememory cell addressed.

A write operation performs a simultaneous read operation.Three different options are available, selected by configura-tion:

1. “WRITE_FIRST”

The “WRITE_FIRST” option is a transparent mode. The same clock edge that writes the data input (DI) into the memory also transfers DI into the output registers DO as shown in Figure 31.

2. “READ_FIRST”

The “READ_FIRST” option is a read-before-write mode.

The same clock edge that writes data input (DI) into the memory also transfers the prior content of the memory cell addressed into the data output registers DO, as shown in Figure 32.

Figure 30: 18 Kbit Block SelectRAM in Dual-Port Mode

Table 16: 18 Kbit Block SelectRAM Port Aspect Ratio

Width Depth Address Bus Data Bus Parity Bus

1 16,384 ADDR[13:0] DATA[0] N/A

2 8,192 ADDR[12:0] DATA[1:0] N/A

4 4,096 ADDR[11:0] DATA[3:0] N/A

9 2,048 ADDR[10:0] DATA[7:0] Parity[0]

18 1,024 ADDR[9:0] DATA[15:0] Parity[1:0]

36 512 ADDR[8:0] DATA[31:0] Parity[3:0]

DOPA

DOPB

DIPA

ADDRA

WEA

ENASSRA

CLKA

DIPB

ADDRB

WEB

ENBSSRB

CLKB

18 Kbit Block SelectRAM

DS031_11_071602

DOB

DOA

DIA

DIB

Figure 31: WRITE_FIRST Mode

Figure 32: READ_FIRST Mode

CLK

WE

Data_in

Data_in

New

aaAddress

Internal Memory DO Data_out = Data_in

Data_out

DI

DS031_14_102000

New

RAM Contents NewOld

CLK

WE

Data_in

Data_in

New

aa

Old

Address

Internal Memory DO Prior stored data

Data_out

DI

DS031_13_102000

RAM Contents NewOld




3. “NO_CHANGE”

The “NO_CHANGE” option maintains the content of the output registers, regardless of the write operation. The clock edge during the write mode has no effect on the content of the data output register DO. When the port is configured as “NO_CHANGE”, only a read operation loads a new value in the output register DO, as shown in Figure 33.

Control Pins and AttributesVirtex-II SelectRAM memory has two independent portswith the control signals described in Table 17. All controlinputs including the clock have an optional inversion.

Initial memory content is determined by the INIT_xxattributes. Separate attributes determine the output registervalue after device configuration (INIT) and SSR is asserted(SRVAL). Both attributes (INIT_B and SRVAL) are availablefor each port when a block SelectRAM resource is config-ured as dual-port RAM.

LocationsVirtex-II SelectRAM memory blocks are located in eitherfour or six columns. The number of blocks per columndepends of the device array size and is equivalent to thenumber of CLBs in a column divided by four. Column loca-tions are shown in Table 18.

Figure 33: NO_CHANGE Mode

Table 17: Control Functions

Control Signal Function

CLK Read and Write Clock

EN Enable affects Read, Write, Set, Reset

WE Write Enable

SSR Set DO register to SRVAL (attribute)

CLK

WE

Data_in

Data_in

New

aa

Last Read Cycle Content (no change)

Address

Internal Memory DO No change during write

Data_out

DI

DS031_12_102000

RAM Contents NewOld

Table 18: SelectRAM Memory Floor Plan

Device Columns

SelectRAM Blocks

Per Column Total

XC2V40 2 2 4

XC2V80 2 4 8

XC2V250 4 6 24

XC2V500 4 8 32

XC2V1000 4 10 40

XC2V1500 4 12 48

XC2V2000 4 14 56

XC2V3000 6 16 96

XC2V4000 6 20 120

XC2V6000 6 24 144

XC2V8000 6 28 168




Total Amount of SelectRAM Memory

Table 19 shows the amount of block SelectRAM memoryavailable for each Virtex-II device. The 18 Kbit SelectRAMblocks are cascadable to implement deeper or wider single- ordual-port memory resources.

18-Bit x 18-Bit Multipliers

Introduction

A Virtex-II multiplier block is an 18-bit by 18-bit 2’s comple-ment signed multiplier. Virtex-II devices incorporate manyembedded multiplier blocks. These multipliers can be asso-ciated with an 18 Kbit block SelectRAM resource or can beused independently. They are optimized for high-speedoperations and have a lower power consumption comparedto an 18-bit x 18-bit multiplier in slices.

Figure 34: Block SelectRAM (2-column, 4-column, and 6-column)

2 C

LB c

olum

ns

2 C

LB c

olum

ns

2 C

LB c

olum

ns

n C

LB c

olum

ns

2 C

LB c

olum

ns

n C

LB c

olum

ns

2 C

LB c

olum

ns

2 C

LB c

olum

ns

2 C

LB c

olum

ns

n C

LB c

olum

ns

n C

LB c

olum

ns

n C

LB c

olum

ns

2 C

LB c

olum

ns

n C

LB c

olum

ns

SelectRAM Blocks

SelectRAM Blocks

ds031_38_101000

2 C

LB c

olum

n

2 C

LB c

olum

ns

SelectRAM Blocks

2 C

LB c

olum

n

2 C

LB c

olum

ns

Table 19: Virtex-II SelectRAM Memory Available

Device

Total SelectRAM Memory

Blocks in Kbits in Bits

XC2V40 4 72 73,728

XC2V80 8 144 147,456

XC2V250 24 432 442,368

XC2V500 32 576 589,824

XC2V1000 40 720 737,280

XC2V1500 48 864 884,736

XC2V2000 56 1,008 1,032,192

XC2V3000 96 1,728 1,769,472

XC2V4000 120 2,160 2,211,840

XC2V6000 144 2,592 2,654,208

XC2V8000 168 3,024 3,096,576

Table 19: Virtex-II SelectRAM Memory Available

Device

Total SelectRAM Memory

Blocks in Kbits in Bits




Each SelectRAM memory and multiplier block is tied to fourswitch matrices, as shown in Figure 35.

Association With Block SelectRAM Memory

The interconnect is designed to allow SelectRAM memoryand multiplier blocks to be used at the same time, but someinterconnect is shared between the SelectRAM and themultiplier. Thus, SelectRAM memory can be used only up to18 bits wide when the multiplier is used, because the multi-plier shares inputs with the upper data bits of theSelectRAM memory.

This sharing of the interconnect is optimized for an18-bit-wide block SelectRAM resource feeding the multi-plier. The use of SelectRAM memory and the multiplier withan accumulator in LUTs allows for implementation of a dig-ital signal processor (DSP) multiplier-accumulator (MAC)function, which is commonly used in finite and infiniteimpulse response (FIR and IIR) digital filters.

ConfigurationThe multiplier block is an 18-bit by 18-bit signed multiplier(2's complement). Both A and B are 18-bit-wide inputs, andthe output is 36 bits. Figure 36 shows a multiplier block.

Locations / Organization

Multiplier organization is identical to the 18 Kbit SelectRAMorganization, because each multiplier is associated with an18 Kbit block SelectRAM resource.

In addition to the built-in multiplier blocks, the CLB elementshave dedicated logic to implement efficient multipliers inlogic. (Refer to Configurable Logic Blocks (CLBs)).

Figure 35: SelectRAM and Multiplier Blocks

SwitchMatrix

SwitchMatrix

18-Kbit blockSelectRAM

18 x

18

Mul

tiplie

r

SwitchMatrix

SwitchMatrix

DS031_33_101000

Figure 36: Multiplier Block

Table 20: Multiplier Floor Plan

Device Columns

Multipliers

Per Column Total

XC2V40 2 2 4

XC2V80 2 4 8

XC2V250 4 6 24

XC2V500 4 8 32

XC2V1000 4 10 40

XC2V1500 4 12 48

XC2V2000 4 14 56

XC2V3000 6 16 96

XC2V4000 6 20 120

XC2V6000 6 24 144

XC2V8000 6 28 168

MULT 18 x 18

A[17:0]

P[35:0]

DS031 - Virtex-II Platform FPGAs: Complete Data Sheetweb.mit.edu/6.111/www/labkit/datasheets/virtex2datasheet.pdf · 2005. 4. 1. · R Virtex-II Platform FPGAs: Introduction and Overview

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