DS LX7309 rev 1.0 - All-Electronics.de · 2015-10-29 · flyback DC-DC controller. The controller has a number of features designed to improve efficiency and reliability: High Voltage

LX7309

PRODUCTION DATASHEET

Microsemi Analog Mixed Signal Group

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 1Copyright © 2011 Rev. 1.0 12/9/2011

SYNCHRONOUS FLYBACK DC/DC CONTROLLER TM

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D E S C R I P T I O N K E Y F E A TU R E S

The LX7309 is a current mode synchronous flyback DC-DC controller. The controller has a number of features designed to improve efficiency and reliability: High Voltage Gate Drivers: The PWM DC-DC controller has two built-in high voltage gate drivers targeted for flyback, direct buck, or forward converter with secondary synchronous rectifier. The gate drivers lower external Power MOSFET power loss while offering a wider MOSFET selection. The gate drivers swing from 0V to VCC.

Peak Current Mode Control: The DC-DC converter employs peak current mode control for better line and load step response. The switching frequency can be set from 100 kHz to 500 kHz, enabling a size and efficiency trade off.

Maximum Duty Cycle is limited to 50% as an aid in reducing the power MOSFET switch. The secondary synchronous MOSFET voltage rating depends on the output voltage and can be higher or lower than the primary side MOSFET switch.

Soft-start circuit: The device includes a soft-start circuit to control the output voltage rise time (user settable) at start up, and to limit the inrush current

Low Voltage Protection Warning and Monitoring: Dual Under Voltage Lock Out (UVLO), which monitors both the bus Input Voltage and VCC, ensures reliable operation during any system disturbances. The VIN UVLO has a programmable threshold and hysteresis to enable tailoring to the desired turn on and turn off voltage. Alternatively, the controller offers Power Fail Warning (PFW) to alert the host processor if bus input power removal occurs.

Over Current Protection with Low Power Dissipation: An internal current sense amplifier with a Kelvin connection allows the use of an extremely low resistor to measure the current sense threshold voltage (200mV) which optimizes efficiency.

Low Power Mode: Low Power Mode operation is provided to improve efficiency under light loads such as when the load is in standby. The user can define at what power level the unit enters low power mode by means of a single resistor value. LX7309 is available in 24-pin, 4x4 exposed pad QFN package.

High Efficiency at Full Load 100kHz to 500kHz Adjustable

DC/DC Switching Frequency DC-DC Frequency Can be

Synchronized to External Clock Supports Low Power Mode

Operation for Higher Efficiency Soft-start Circuit to Control the

Output Voltage Rise Time Support Efficient Synchronous

Rectification VIN UVLO/PFW with Programmable

Threshold and Hysteresis Internal Differential Amplifier

Simplifying Non-isolated Step-down Converter

Over Load and Short Circuit Protection

RoHS Compliant & Pb-Free

APPL ICA TIONS Power Over Ethernet 48V Input Telecom/networks Hot

Swappable Power Supply Automotive 24V Industrial VOIP Phone

IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com

PACKAGE ORDER INFO T H E R M A L D A T A

TA (°C) LQ 4x4mm Plastic QFN 24Pin θJA = 36 °C/W RoHS Compliant / Pb-free THERMAL RESISTANCE-JUNCTION TO AMBIENT

-40 to +85 LX7309ILQ Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. θJA number above is with 4-layer pcb board.

Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX7309ILQ-TR)

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A A B S O L U T E M A X I M U M R A TI N G S PACKAGE P IN OUT

VCC (with respect to GND) ........................................................................ -0.3V to 40V PG, SG (with respect to PGND) ................................................................... -0.3V to 20V VDD (with respect to GND) ........................................................................... -0.3V to 6V VH (with respect to VCC) ................................................................... -0.3V to VCC - 6V All Other Pins (with respect to GND) ............................................. -0.3V to VDD + 0.3V Maximum Operating Junction Temperature ............................................................ 150°C Operating Ambient Temperature ................................................................ -40°C to 85°C Storage Temperature Range ...................................................................... -65°C to 150°C Peak Package Solder Reflow Temp (40 seconds max exposure) ............................. 260°C

Notes: Exceeding these ratings could cause damage to the device. All voltages are with respect to

GND. Currents are positive into, negative out of specified terminal. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” are not implied. Exposure to “Absolute Maximum Ratings” for extended periods may affect device reliability.

LQ PACKAGE (Top View)

xx = Date Code/Lot Code RoHS / Pb-free Matte Tin Pin Finish

E L E C T R I C A L C H A R A C T E R I S T I C S

Unless otherwise specified, the following specifications apply over the operating ambient temperature of -40°C ≤ TA ≤ 85°C except where otherwise noted with the following test conditions: VCC = 7V to 20V; VENABLE = HIGH, Fs = 250 kHz. Production tests performed at 25°C.

Parameters Symbol Test Conditions/Comments MIN TYP MAX Units

VCC

Operating Input Voltage VCC 7 20 V

Shutdown Current ISD VCC < VCC_UVLO or ENABLE = Low 200 µA

Input Current IVCC VCC >VCC_UVLO and ENABLE = High, No Load on PG, SG, VDD, and FSW = 500kHz 3 mA

VCC UVLO Rising Threshold VCCUVLO

VCC rise time (10% to 90%) ≥ 0.5ms 8.85 9.15 9.5 V

VCC UVLO Falling Threshold VCC fall time (90% to 10%) ≤ 5ms 7 7.3 7.6 V

VIN Input UVLO/PFW

UVLO/PFW Threshold VINS Rising or falling (via external resistor divider from VIN to GND). 1.171 1.200 1.229 V

Output High Voltage HYST-VOH ISOURCE = 1mA 2.8 V

Output Low Voltage HYST-VOL ISINK = 3mA 0.4 V

Low Dropout Regulators

+5V Low Dropout Regulator VDD 0 < IL < 5mA, Not including internal consumption 4.75 5 5.25 V

-5V Low Dropout Regulator VH Reference to VCC; for Internal use only -5 V

Soft-start

Soft-start Charging Current IssCHG RFREQ = 33.3kΩ; VSOFTSTART = 0.5V; See Note 2 32 36 40 µA

Soft-start Discharging Current IssDIS VSOFTSTART = 0.5V; 10 % of IssCHG

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Soft-start Done Threshold Vss See Note 1 90 95 %1.2V REF

Soft-start Discharge (by current source) Done Threshold

Vss See Note 1 50 mV

Soft-start Discharge FET On Resistance 50 Ω

Soft-start Discharge FET On Time Specified as switching frequency clock cycle

See Note 1 32 Cycles

Switching Frequency and Synchronization Switching Frequency Adjust Range FFREQ 100 500 kHz

Switching Frequency Set Point Accuracy FFREQ

RFREQ = 33.2k (VRFREQ = 1.2V). 270 300 330 kHz

Synchronization Frequency Range FSYNC FSYNC > 2x FFREQ 200 1000 kHz

Synchronization Voltage High Threshold VSYNC 2.4 V

Synchronization Voltage Low VSYNC 0.8 V Synchronization Minimum Pulse Width PWSYNC 100 ns

Synchronization Maximum Pulse Width Duty cycle of input synch pulse 90 %

Error Amplifier

DC Open Loop Gain1 RLOAD = 100k 70 100 dB

Unity gain bandwidth1 AVUGBW CLOAD = 10pF; Note 1 2 5 MHz

Output Sourcing Current 0.2V ≤ VCOMP ≤ 1.3V 110 620 µA Output Sink Current 0.2V ≤ VCOMP ≤ 1.3V 145 495 µA Input Common Mode Range 0 2 V

Feedback Voltage Accuracy VFB COMP shorted to FB. 1.171 1.200 1.229 V

Output High Clamp VCOMP 1.8 2.1 2.6 V

PWM Comparator Non-Inverting Input Inserted Offset 200 300 mV

RCLP Voltage range RRCLP An external resistor to GND is used to set this voltage. See Note 4. 0 1 V

Low Power Mode ( SKIP PULSE MODE)

Low Power Mode Threshold

VCOMP Rising (as percent of VRCLP). Refer to Figure 3. See Note 1 & 4 95

% VCOMP Falling (as percent of VRCLP). Refer to Figure 3. See Note 1 & 4 90

Current Sense Amplifier and Current Limit

Gain VOS Measure at DC 4.75 5 5.25

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Input Common Mode Range 0 2.0 V

Blanking Time 50 100 ns

Current Limit Threshold VILIM_TH Threshold where PWM pulses are truncated. 1.1 1.2 1.3 V

Current Max Threshold VIMAX_TH Threshold where device goes into hiccup. 1.7 1.8 1.9 v

Differential Amplifier

Gain Measured at DC 6.86 7.0 7.14 V/V

Unity Gain Bandwidth See Note 1 5 MHz

Common Mode Range 0 3.5 V

ENABLE Input Primary Gate (PG) High On Resistance PG RDSON 10 Ω

Primary Gate (PG) Low On Resistance PG RDSON 5 Ω

Secondary Gate (SG) High On Resistance SG RDSON 10 Ω

Secondary Gate (PG) Low On Resistance SG RDSON 10 Ω

Dead Time – PG Low to SG High or SG Low to PG High TDEAD Measured between 10% levels. CLOAD on PG

and SG < 100pF 60 110 190 ns

PG Minimum On Time 120 ns

PG Maximum Duty Cycle 44.5 50 %

Logic (VINS_SELECT pin / ENABLE Pin)

Logic High Threshold 2.0 V

Logic Low Threshold 0.8

Thermal Shutdown

Thermal Shutdown Threshold1 157 ºC

Threshold Hysteresis1 15 30

Notes: 1) Guaranteed by design. Not tested during production. 2) Soft Start Charge Current Equation: Iss_chg = 1.2V/RFREQ 3) Switching Frequency Equation: Freq = 10x109/RFREQ 4) Low Power Mode Clamp Equation: VCLAMP = 0.3 * (RRCLP/RFREQ)

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FUNCTIO N AL P IN DESCRIP T ION Pin

Number Pin Name Description

1 VH 5V High side (VCC reference) internal LDO's Output. Connect a 0.1µF or higher ceramic cap from VH to VCC.

2 VCC Input Supply to the DC-DC Controller. Connect a 4.7µF or higher ceramic capacitor from this pin to PGND. Alternately a parallel combination of 1µF ceramic and an >10µF electrolytic capacitor can be used.

3 ENABLE Logic level Enable input for DC-DC controller. This pin can be tied to VDD (pin 18) so that the enable of this device will depend on VCC UVLO and VINS UVLO.

4 VINS Power input voltage sensing for UVLO. Comparator. Connect to an external resistor divider from input to GND. Threshold is 1.2V reference.

5 NC Not used.

6 HYST Output of the VIN/UVLO comparator. This pin can be used to for VIN UVLO hysteresis programming, or as an output flag for PFW function

7 SYNC External Clock synchronization for the DC-DC controller. Connect an external clock as defined in the EC table to this pin to synchronize the DC-DC converter switching frequency to this clock. PG rising edge is synchronize with the clock rising edge.

8 VINS_SEL UVLO/PFM_SELECT Logic Input. Internally pulled low for VINS PFW operation. Pull to logic high to use as VINS UVLO.

9 RFREQ DC-DC Switching Frequency Setting. Connect a resistor from this pin to GND to set the switching frequency.

10 SS Soft-start: Connect a capacitor from this pin to GND to set the soft-start time of the DC-DC converter. This capacitor is charged with an internal current source to 1.2V.

11 RCLP Low Power Mode Clamp. Connect a resistor from this pin to GND to program the LPM clamping voltage or connect this pin to GND to disable LPM.

12 VSN Differential Amplifier's negative input. Connect this to the junction of the resistor divider from VO- to GND of the Direct Buck converter application.

13 VSP Differential Amplifier's positive input. Connect this to the junction of the resistor divider from Vo+ to GND of the Direct Buck converter application.

14 COMP Error Amplifier Output. Connect to FB via RC compensation networks for Non-Isolated Direct Buck Converter.

15 DAO Differential Amplifier Output. Connect to FB (externally) via a resistor for Non-Isolated Direct Buck Converter.

16 FB Inverting Input of the Error Amplifier. Connect to RC compensation networks for Non-isolated DC-DC.

17 GND This is Analog GND (quiet GND). Connect to a local AGND plane. Soft-start capacitor and the frequency setting resistor return to this local GND plane.

18 VDD 5V (GND reference) internal LDO's Output. Connect a 1µF or higher ceramic cap from VDD to GND.

19 SG Secondary Gate Driver. Leave open (NC) if not used. SG is low when in Skip Mode.

20 PGND This is the Power Ground. Connect to a local PGND plane. Input, VCC decoupling capacitors, PG and SG drivers, Primary current sense resistor return to this PGND.

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FUNCTIO N AL P IN DESCRIP T ION Pin

Number Pin Name Description

21 CSN Negative Input of the Current Sense Amplifier. Kelvin connect to the PGND side of the primary current sense resistor.

22 CSP Negative Input of the Current Sense Amplifier. Kelvin connect to the Non-PGND side of the primary current sense resistor.

23 PG Primary Gate Driver. Connect to the gate of the primary side Power MOSFET, directly or via a resistor.

24 NC Not used.

V I N U V L O O R P F W S E L E C T I O N

VINS_SEL VINS >1.2V Operation Comment

0 No PFW

DC-DC controller is enabled depending on VCC and ENABLE pins. HYST pin is low.

0 Yes DC-DC controller is enabled depending on VCC and ENABLE pins. HYST pin is high.

1 No UVLO

DC-DC controller is not enabled

1 Yes DC-DC controller is enabled depending on VCC and ENABLE pins

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F U N C T I O N A L B L O C K D I A G R A M

Figure 1. LX7309 Functional Block Diagram.

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TYPICAL APPL ICA TION

Figure 2. 12V/4A Output Isolated fly-back with Secondary Synchronous Rectification

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TYPICAL APPLICATION

SYN

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S_S

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Figure 3. 12V/2.1A Output Non-Isolated Direct Buck Application

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T H E O R Y O F O P E R A T I O N / A P P L I C A T I O N I N F O R M A T I O N

OPERATION OVERVIEW The LX7309 is a synchronous flyback controller DC/DC

PWM controller. This PWM DC-DC controller has two built in 0V to VCC gate drivers targeted for flyback or forward converter with secondary synchronous rectifier, or direct buck. The 10V gate drive improves external Power MOSFET power loss while offering wider MOSFET selection. The DC-DC converter employs peak current mode control for better line and load step response. The switching frequency can be set from 100 kHz to 500 kHz allowing size and efficiency trade off.

The maximum duty cycle of the DC-DC controller is limited to 50% to which helps to reduce the power MOSFET switch. The secondary synchronous MOSFET voltage rating depends on the output voltage and can be higher or lower than the primary side MOSFET switch.

Dual Under Voltage Locked Out (VINS and VCC) ensures reliable operation under all systems disturbances. The VINS/HYST UVLO has a programmable threshold and hysteresis to allow tailoring to the desired turn on and turn off voltage. Optionally in lieu of UVLO the LX7309 can be configured (by changing the VINS_SEL pin) to offer the Power Fail Warning (PFW) to alert the system of power is about to go down.

An internal current sense amplifier with Kelvin connection allows the use of an extremely low resistor. This enables the current sense threshold voltage to be approximately set at 200mV to optimize efficiency.

A Low Power Mode operation is provided to improve efficiency under light load such as when the appliance is in standby. The power level (threshold) to enter into low power mode is user programmable.

DC-DC Start-up

As the VCC supply ramps up (VCC < VCC_UVLO) the internal bias voltages will turn on, and VDD will generate 5V when the VCC voltage is sufficiently high.

When VCC > VCC_UVLO and ENABLE = High the startup sequence begins with ramping up of the SS pin from GND to 1.2V. For simplicity of design, the ENABLE signal can be tied to VDD so that the turn on will solely depend on the VCC voltage.

For isolated application the output voltage may reach regulation before SS reaches 1.2V, depending on the output loading condition. The external secondary error amplifier regulates the output voltage and control the peak inductor current via an opto-coupler across the isolation barrier. For non-isolated application the output reaches regulation when SS reaches 1.2V as the internal error amplifier is used to close the regulation loop.

An intentional offset is added to FB, internally, to ensure that COMP will not rail high due to input offset of the amplifier. This offset will be removed (slowly to avoid over shoot) as SS ramps up to its final value.

Low Power Mode is not supported during SS ramp as it is not necessary.

Current Limit and Short Circuit Protection

Whether it is during SS ramp or after SS is done (VSOFTSTART = 0.9 x 1.2V) over current and maximum current is treated in the same manner. If the output of the current sense amplifier detects that the current has exceeded the current limit threshold, the PG pulse will be truncated to the minimum pulse width. This state of exceeding the current limit and truncating the PG pulse can go on indefinitely.

However, if the current sense amplifier detects that the Current Max Threshold has been exceeded, the device will go into hiccup mode. In this mode, the SS capacitor is discharged with a constant current equal to 10% of the charging current during ramp up (note if hiccup occurs during SS ramp, the SS charging will stop, and discharge will start at the voltage SS is at when it entered hiccup mode). This discharge continues until the SS voltage = 50mV where an internal 50Ω MOSFET connected to SS turns on for 32 clock cycles to ensure the SS capacitor is fully discharged. The controller will exit hiccup mode when the over current condition is removed.

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T H E O R Y O F O P E R A T I O N - C O N T I N U E D

Low Power Mode Operation:

The LX7309 offers a pulse skipping operation for light load condition, referred as Low Power Mode (LPM), to improve the efficiency of light load operation by reducing the power dissipation of the circuit from high frequency switching. Using an external resistor from RCLP pin to GND, the user can program the output power when the unit enters pulse skipping; current output of the RCLP pin is 0.25times of the Soft Start Charging current. LPM can be disabled by connecting RCLP to GND. Pulse skip is disabled until SS ramp is done, regardless of the RCLP voltage.

For DCM operation, the clamp established by RCLP voltage equates to a percentage of output power by the following:

. 5 5 1.1

Where:

0.3

Example: Desired power level of clamp = 2W Primary inductance = 19uH Sense resistor = .062Ω Switching Frequency = 200kHz Frequency Setting Resistor, RFREQ = 49.9k

. 5 5 1.1

0.35

0.30.35 49.9

0.3 58.2

Install a 57.6k resistor from RCLP pin to ground.

Input (VIN &VCC) Under Voltage Lock Out and Power Fail Warning:

The LX7309 provides an option (VINS_SEL = high) to have a programmable UVLO by the level of the converters Input Voltage with programmable hysteresis. This feature allows the end user to tailor the controller to any desired systems application’s requirement for turn-on and turn-off time. In addition to the Input Voltage sensing for UVLO, the LX7309 also has VCC UVLO to ensure that the PWM controller is properly powered at all modes of operation for a more robust solution under various systems disturbances.

Setting VINS_SEL = high, the LX7309 functions with VCC UVLO. VCC UVLO is used to shut down the converter when the input line drops below a level programmable by a resistor divider on VINS pin. UVLO Hysteresis can be set by the user by connecting a resistor between HYST and VINS pins.

UVLO threshold and hysteresis resistors can be calculated by (reference Figure 4):

VHYST = HYST Pin Output High (5V typ.)

VH = Desired Hysteresis

VRISING = Upper Voltage Threshold

Set R3 such that (VHYST – 1.2)/R3 ≤ 10uA

R1 = R3 x (VH/VHYST)

R2 = 1/[(VRISING/(1.2 x R1)) – (1/R1) – (1/R3)]

Figure 4. VCC UVLO External Resistors

By setting VINS_SEL = low, the LX7309 functions with a Power Fail Warning (PFW) feature in lieu of VCC UVLO for applications that require PFW. Power Fail Warning senses the input voltage at a threshold level programmable by the user using an external resistor divider (reference Figure 4). The threshold is programmed at a point above the drop out voltage.

R3R2

R1

VCC

VINS

HYST

4

6

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The drop out voltage is defined as the voltage at the input below which the output will drop due to maximum duty cycle limit. This way the warning can let the system know in advance before the output drops out. The warning time depends on the output power, the conversion efficiency, the primary input capacitor, and the detection threshold setting relative to the input drop out voltage, i.e., the difference between the VIN PFW threshold and the drop out voltage (VIN PFW threshold – V drop-out).

The warning time can be calculated by: 1 2 /2

Where: C = DC-DC Input Bulk Capacitance V1 = VIN PFW threshold V2 = drop out voltage PO = the instantaneous output power Example: C= 200µF V1 = 42V V2 = 36V PO = 25W η= 0.87(efficiency) tWARN = 1.63ms.

If the UVLO feature is selected, the DC/DC converter will remain in operation until VCC drops below the threshold level. If PFW feature is selected, the HYST pin is used to indicate a power failure (HYST pin goes low in the event VINS drops below 1.2V). During a PFW event the DC/DC will not shut down.

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P A C K A G E D I M E N S I O N S

LQ 4x4mm Plastic QFN 24 Pin Package

Dim MILLIMETERS INCHES MIN MAX MIN MAX

A 0.80 1.00 0.031 0.039 A1 0 0.05 0 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.011 D 4.00 BSC 0.157 BSC E 4.00 BSC 0.157 BSC e 0.50 BSC 0.019 BSC

D2 2.30 2.55 0.090 0.100 E2 2.30 2.55 0.090 0.100 L 0.30 0.50 0.012 0.020

Note:

1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not include solder coverage.

E

A

D

e

b

E2

D2

L

A3

A1

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NOTES

PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time.

DS LX7309 rev 1.0 - All-Electronics.de · 2015-10-29 · flyback DC-DC controller. The controller has a number of features designed to improve efficiency and reliability: High Voltage

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