Driving Six Sigma at a Microelectronics Supplier

© 2005 Cabot Microelectronics Corporation

1

Driving Six Sigma At A Microelectronics Supplier

Cliff Spiro, VP Research and Development

Bob Launsby, Launsby Consulting

Las Vegas, 2005


2

The Chip: The Basic Build Block of Microelectronics


3

Chemical Mechanical Planarization (CMP) Basics

•Chips Consist of Embedded Transistors Interconnected With Nano-Wires

•Each Wire Is Produced Lithograpically on Planarized (Nano-Polished) Dielectric •CMP Planarizes The Surfaces Using a Polisher, a Slurry and a Pad•Several Materials– Metals, Barriers, and Insulators– Need to

Be Polished Together As Well As Sequentially•Cabot Microelectronics Provides the Consumables For the CMP Process


4

A Wafer is a thin 200-300mm round slice of silicon which is the primary unit of production in semiconductor manufacturing.

Wafer Chip or Die

Scribe Line

The Wafer- Where Chips Come From


5

Precision Wiring is the Key Part of the Chip Design

The smallest wires are 0.0000065 centimeters across– over 1000 times thinner than a human hair!


6This is why we need CMP

Each Layer Needs to Be Polished To Keep The Wiring Flat

Planarized IC productNon-planarized IC product

A Single Void or Short Can Destroy the Chip and Hundreds of Dollars of Value


7

Mostly (90-99%) Pure WaterDispersed, Filtered NanoparticlesCommon, Dilute Acids And BasesPolymers and SoapsBiocides to Keep Mold From Growing in the SlurriesDilute Hydrogen PeroxideCommon and Specialty Salts

Huge Requirement For Performance, Quality and Consistency

Cabot Microelectronics’ Main Product: Polishing Slurries


8

Six Sigma Introduced to Drive Improvement

Brought in Launsby Consulting For Early Training (Late 2003)Hired Spiro (ex-GE-- MBB) to Lead R&DHired Weisman (ex-GE- MBB/Quality Leader to Lead ManufacturingHired Hensel (ex-, MBB) to Lead Quality

Started With DFSS Training For All R&DFollowed By DMAIC Training For All QC and Manufacturing ExemptSix Sigma Awareness for All Non-ExemptQFD and VOC Training For Sales and Marketing1st Wave BB Training CompletedTrain-the-Trainer Completed

Brought in Suppliers For Training and Joint DevelopmentsBrought in Customers For Training and Joint Developments


9

Seeking Early Six-Sigma Wins: Saving Money in the Lab With Test Wafers


10

Sought Early “Wins”: Lab Table Top Test Method

• Test Wafer Consumption Was Running ~$10 Million/Year• Developed A Method To Cut Mini-Wafers Out of Full Wafers• Developed a Mini-Lab Polisher To Test Mini Wafers• Developed Transfer Functions to Correlate Table Top to Production Test• Table Top Response Actual vs. Predicted: R2 = .965

Actual vs Modelled Response Table Top and Cleanroom

02000400060008000

100001200014000

0 1000 2000 3000 4000 5000 6000

Table Top Response - Actual

Cle

anro

om

R

esp

on

se

Actual Model


11

1Q04 2Q04 3Q04 4Q04 1Q05

Six Sigma and Wafer Cost Reduction: Table Top Savings

$


12

Implemented Standard DFSS Processes For New Product Design

• Understand Customer ‘CTQs’, i.e., Cost of Ownership, Yield

• Design in quality, consistency, manufacturability, and cost for new products from the start

• Use Experimental Design to identify transfer functions and manufacturing tolerances

• Rigor, GR&R, Efficiency and Speed

Key Design Breakthrough: DOE’s Yield Custom Tunability


13

Tunability: The Key to Customer Satisfaction

• Divergence of customer needs

• Customer secrecy and access to their wafers

• Impossible to resource one-off product design

• Tunable platforms offer speed and performance

Examples:

Tunable Particles

Tunable Chemistries

Tunable Pads

Tunable Process Conditions

Tunability Comes From The Transfer Functions


14

0

500

1000

1500

2000

0 100 200 300 400 500 600 700

Chemistry

Re

mo

va

l R

ate

(A

/min

) PolyBPSGNitride

Example: DFSS For A Selective Poly Slurry

Simultaneously Polishing Silicon, Doped Silicon Dioxide, and Silicon Nitride With Semi-Independently Tunable Rates


15

A Multi-Dimensional Transfer Function Allows Some Customers to Maximize Rate And Others To Have a Less

Sensitive Polish

Rate


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0

500

1000

1500

2000

2500

3000

0 10 20 30 40 50 60 70 80 90 100

Relative Additive (%)

Re

mo

va

l Ra

te (

A/m

in)

Tungsten Polish Rate

Insulator Polish Rate

Another Example: Tunable Tungsten / Oxide Selectivity


17

One More: Silicon Oxide / Nitride Tunable Selectivity

Unique Compositions

Many options for desired rate and selectivity performance

-3

-2

-1

0

1

2

3

4

5

6

7

ln(S

elec

tivi

ty)

1:1

10:1

100:1

1:10

Oxide to nitride selectivity

Stopping on nitride (STI)

Stopping on oxide (Intel)


18

Manufacturing and QC Add Standard ‘DMAIC’ to Improve Existing Processes

Define

Measure

Analyze

Improve

Control

Systematic way to Improve Quality and Cut Costs


19

Example: Six Sigma With Raw Material SuppliersFumed Metal Oxides: Stochastic / Chaotic / Fractal…

real performance advantages but high variation


20

Observation

Indiv

idual V

alu

e

362333304275246217188159130101

_X=8879057

UCL=16059148

LCL=1698965

Historical Post

1

1

111

1

1

1

1

1

1

1

Run Chart: Key Product Characteristic12 months with 3-Sigma Control Limits by Period

-Improvement

60

45

30

15

0

USL

Overall

Cpm *

Z.Bench 0.669Z.LSL *Z.USL 0.669Ppk 0.223

30

20

10

0

USLOverall

Cpm *

Z.Bench 4.481Z.LSL *Z.USL 4.481Ppk 1.494

Capability Histograms

Historical (Pre-Improvement)

Post Improvement

Historical Capability: 0.67 Sigma

Post-Improvement Capability:4.48 Sigma

Reducing Particle Size Variation at the Supplier

Multivariate Analysis: Jointly Identifying the Source of Variation at the Supplier


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Manufacturing and Six Sigma Supply Assurance

• Implemented “Theory of Constraints” to identify bottlenecks and streamline slurry manufacturing operations

• Employed “Queuing” Software to illustrate impacts of Handoffs, Changeovers, and Overtime

• Reduced Manufacturing Cycle Time 30.7% without changing the process

• Reduced Cycle Time Variation 69.8%

• Reduced Overtime Costs and Improved Supply Assurance for Customers

• Applied same methods to de-bottlenecking QC– Reduced Cycle Time in QC Lab from 76 to 34 hours


22

Six Sigma and Manufacturing Queuing


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Desks Desks

centrifu

ges

D

Samples

Samples

storagePMSHoriba

PC

PC

tensiometer

WB

WBSamplesS

Son

ic

print

PC

MS

PP

PCH3

H4

PC

Wate

rs

HNew

sam

ple

s sam

ple

s

S

PC

ICP

3

microw

ave

MS

En

v

PCPC

A6

A1

samp

les

MF

OD

DD

B

A3

A8

PC

PC

W3

W2

sam

ple

s

P6 P15P13 P8

V7 V6

samples

PC

PC

T3

T1

T5

dilution

cabi

nets

9h

9i9j

9k

LL

L

L

L

F

P

P

1

2

3

4 5

6

7

8

9

10

11

9a9b

9c9d

9e

9f9g

B

B

B

L

files

1

2

2a3

2 splits to500 Main

3a

3b3c

3d

4

5 6

7

To QA storage

PC S LIMS

Spaghetti Maps Identify Opportunities to Increase Speed and Efficiencies in QC

24

Summary and Conclusions

• Six Sigma is Good Science and Engineering

• Demanding Customers Require Rigor and Understanding in This Industry

• Six Sigma Cuts Costs and Increases Speed in the Usual Ways– For R&D, Manufacturing, and QC

• DFSS Means Tunability of New Products is Automatic

• DFSS Affords Quick Response to Performance Drift at Customers

• Six Sigma Applies to New and Existing Products

• It is a Win For Customers and Suppliers Alike

Driving Six Sigma at a Microelectronics Supplier

Documents

sigma wins

sigma awareness

manufacturing queuing

chip design

early training

manufacturing cycle

test wafers

manufacturing exempt