DRC 2009 1 0.37 mS/m In 0.53 Ga 0.47 As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain Uttam Singisetti*, Mark A. Wistey, Greg J. Burek, Ashish K. Baraskar, Joel Cagnon, B. J. Thibeault, S. Stemmer, A.C. Gossard, and M.J.W. Rodwell ECE and Materials Departments University of California, Santa Barbara, CA Eun Ji Kim, Byungha Shin, and Paul C McIntyre Materials Science and Engineering, Stanford University, Stanford, CA Yong-ju Lee Intel Corporation, Santa Clara, CA 2009 Device Research Conference Pennsylvania State University, State College, PA *[email protected]
22
Embed
DRC 2009 1 0.37 mS/ m In 0.53 Ga 0.47 As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain Uttam Singisetti*, Mark A. Wistey, Greg.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
DRC 20091
0.37 mS/m In0.53Ga0.47As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain
Uttam Singisetti*, Mark A. Wistey, Greg J. Burek, Ashish K. Baraskar, Joel Cagnon, B. J. Thibeault, S. Stemmer, A.C. Gossard, and M.J.W. Rodwell
ECE and Materials DepartmentsUniversity of California, Santa Barbara, CA
Eun Ji Kim, Byungha Shin, and Paul C McIntyreMaterials Science and Engineering, Stanford University, Stanford, CA
Yong-ju LeeIntel Corporation, Santa Clara, CA
2009 Device Research ConferencePennsylvania State University, State College, PA
Control of short-channel effects vertical scaling1 nm EOT: thin gate dielectric, surface-channel device5 nm quantum well thickness<5 nm deep source / drain regions
~3 mA/m target drive current low access resistanceself-aligned, low resisitivity source / drain contactsself-aligned N+ source / drain regions with high doping
-4
-3
-2
-1
0
1
2
3
0 50 100 150 200 250
En
erg
y (
eV
)
Y (Ang.)
Al2O
3
InGaAs InAlAs
DRC 20095
22 nm InGaAs MOSFET: source resistance
IBM High-k Metal gate transistorImage Source:EE Times
smi
did Rg
II
1 g
DSsheet
DSg
cs W
L
LWR
2/
/
LgLS/D
• Source access resistance degrades Id and gm
• IC Package density : LS/D ~ Lg =22 nm c must be low
• Need low sheet resistance in thin ~5 nm N+ layer