DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference PIDS Status and Key Issues: 2004 and 2005 ITRS Peter M. Zeitzoff for PIDS Technology.

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

PIDS Status and Key Issues: 2004 and 2005 ITRS

Peter M. Zeitzoff for PIDS Technology Working Group

ITRS Open MeetingJuly 14, 2004

San Francisco

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

PIDS Scope• PIDS = Process Integration, Devices,

and Structures• Main concerns–Process integration and full process flows–MOSFET and passive devices and structures• Device physical and electrical characteristics and

requirements–Broad issues of device and circuit

performance and power dissipation, particularly as they drive overall technology requirements–Reliability

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

PIDS Subcategories• Logic: both high performance and low power logic

– Low power focused on mobile applications• Memory: both DRAM and Non-volatile memory• Reliability

• RF and mixed-signal/analog technology for wireless communications– To be discussed by Margaret Huang in a separate

presentation• Emerging Research Devices: focused on devices

and technologies for 2009 and beyond – To be discussed in a separate presentation by Jim Hutchby

Separate in 2005

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Status

• 2004 PIDS section: only minor updates and corrections from 2003 version

• Beginning preparation for 2005 PIDS

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

• Non-volatile memory (NVM)– Flash (NOR and NAND), FeRAM, SONOS, and MRAM

– Flash issues• Difficult scaling issues for interpoly dielectric and tunneling

dielectric thicknesses

• Does flash F catch up with or even surpass DRAM half pitch?

– Possible transfer of phase change and floating body memory from ERD to PIDS in 2005

• DRAM– 2005 and beyond: scaling of DRAM half pitch, “a” factor,

etc.

– New survey of key DRAM companies to be done

– What was DRAM half pitch in 2003 and 2004

Memory

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Top 5 Near-Term Reliability Challenges

• High k Gate Dielectrics– Dielectric breakdown; Transistor instability

• Metal Gate– Ion drift, VTH stability, oxidation; thermal-mechanical

• Cu/ Low k– Electromigration and voiding; stability of interfaces; TDDB– Impact of porous, weaker, less thermally conductive dielectrics

• Packaging– Solder bumps; fracture; EM in packaging; CTE mismatch

• Design & Test for Reliability– Reliability simulation; Reliability screens

Challenges are NOT listed in priority order

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

• Reliability requirements on a per chip basis are constant– Relative reliability required per transistor becomes more

stringent with scaling– Relative reliability required per meter of interconnect

becomes more stringent with scaling

• Reliability challenges are associated with new materials and structures: high-k/metal gate stack, copper/low-k, elevated S/D, ultra-thin body fully depleted SOI, multiple-gate, etc.– Reliability models, data, and reliability qualification

should predate production start– Detailed report from RTAB of International SEMATECH

on key reliability challenges will be linked

Reliability

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Logic: Scaling Approach and Categories• Simple models capture essential MOSFET physics embedded in

a spreadsheet– Verified vs. MASTAR (sophisticated device model from STM), literature

data, and PIDS member knowledge– Initial choice of scaled MOSFET parameters is made– Using spreadsheet, MOSFET parameters are iteratively varied to meet ITRS

targets• This is one optimal scaling scenario

– 2003 models more comprehensive and accurate than in 2001 ITRS

• Types of Logic– High Performance: target is historical 17%/year transistor performance

increase – Low Power (especially for mobile applications): target is specific, low level

of leakage current• Low Standby Power (LSTP): very low power (i.e., cellphone)• Low Operating Power (LOP): low power, rel. high performance (i.e.,

notebook computer, video camcorder

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Calendar Year

(ps)

0.1

1.0

10.0

2005 2009 2013 2017

HPRequire-ment

LSTP

Calendar Year2005 2009 2013 2017

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

(A

/m

)

HP

LSTP Requirement

DELAY(lower delay = higher speed)

Leakage Current(higher leakage = higher

standby power)

Low Standby Power (LSTP) & High Performance (HP)

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

NMOSFET Performance and Leakage Scaling

0.1

1.0

10.0

2003 2008 2013 2018

Calendar Year

MO

SF

ET

Per

form

ance

(p

s)

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00Isd

,leak (µA/µm

)

Isd,leak: HP

Isd,leak: LOP

Isd,leak: LSTP

, HP

, LSTP, LOP

17%/year performance improvement rate

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Key PIDS Logic Issues for 2005 ITRS

• Overall 1/ and Isd,leak scaling scenarios for high-performance, LSTP, and LOP– Particularly LOP: definition, tradeoff between and fit of

LOP between LSTP and high-performance logic

• Relations between Isd,leak and Jg,limit

– Jg,limit = (Isd,leak/Lg) x ([Temp Factor]/[Stack & Overlap Factor])

– Stack & Overlap Factor = 3—very rough estimate

• More attention to PMOSFETs• Timeline of potential solutions

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Fully Depleted SOI HP

The “CMOS Change Crunch” Multiple, Big Changes Over Next 7 Years

Multi Gate MOSFET HP

2000 2005 2010 2015 2020

HPStrained Si

Metal Gate HP

First Year of “Volume Production”

High k Gate Dielectric

HPLP

LPHP = High Performance Applications

= Low Power Applications

Driver:

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

LSTP: EOT and Gate Leakage Current Density (Jg) Scaling

1.E+03 25

Calendar Year

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

2003 2005 2007 2009 2011 2013 2015 2017

Jg

(A

/cm

2)

0

5

10

15

20

EO

T (A

)

EOT

Jg,max

Jg,sim,SiON

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Key PIDS Logic Issues for 2005 ITRS (con’t.)

• Review modeling– Fringe and overlap capacitance– Scaling of mobility enhancement–Modeling and scaling of enhancements due to

advanced devices (single- and multiple-gate)• MASTAR modeling will be important here

– Quasi-ballistic transport

• With FEP– Improved modeling of S/D: Rsd, S/D lateral

abruptness, xj, and halo

– Poly depletion and quantum effects

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Review Timing of Key Logic Technology Innovations• These lnnovations are required to meet scaling performance

goals • Enhanced mobilitystrained Si

– High-performance (HP): 2004 (90 nm node)– LOP & LSTP: 2008 (57 nm node)

• High-k gate dielectric– LSTP and LOP: 2006 (70 nm node)– HP: 2007 (65 nm node)

• Metal gate electrode: 2007 (65 nm node) for High-Performance, 2008 (57 nm node) for LOP and LSTP

• Advanced MOSFETs: FDSOI, probably followed by double gate or multi gate– 2008 (57 nm node): HP– 2012 (35 nm node): LOP & LSTP

• Enhanced vsat (quasi-ballistic transport)– HP: 2012 (35 nm node) – LOP: 2015 (25 nm node) – LSTP: 2018 (18 nm node)

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

• Timeliness: many major changes in a short time• High-performance logic: performance high leakage• Low power logic: low leakage reduced performance• High-k gate dielectric required initially for low-power logic;

other major changes required first for high-performance logic

• Advanced MOSFET structures needed with scaling (strained Si, UTB-FD SOI, FinFETs, etc.)– To meet Ion versus Ioff

– SOI reduces junction leakage and capacitance– To control short channel effects

Summary of Key Logic Issues