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B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2007Third Semester(Regulation 2004)

Computer Science and Engineering

CS 1202-DIGITAL PRINCIPLES AND SYSTEM DESIGN

(Common to B.E.(Part-Time) Second Semester Regulation 2005)

Time:Three hours Maximum:100 marks

Answer all questions

(PART A-10*2=20 marks)

1.What are error detecting codes?2.Find the components for the following functions (a).F1=xy’+x’y(b).F2=(xy+y’z+xz)x3.Draw the circuit diagram for 3 bit parity generator.4.What are the drawbacks of K-Map method?5.What is logic synthesis in HDL?6.When an overflow condition will encounter in an accumulator register?7.What is gate leveling modeling?8.What are the differences between sequential and combinational logic?9.Draw the logic diagram for D-Type Latch.10.What are the assumptions made for pulse mode circuit?

(PART B-5*16=80 marks)11.(a).Using tabulation method simplify the Boolean functionF(w,x,y,z)=S(2,3,4,6,7,11,12,13,14) which has the don’t care conditions d(1,5,15).or(b).Simplify the Boolean function using Variable Entered Mapping method and implement using gatesF(w,x,y,z)=S(0,2,4,6,8,10,12,14)

12.(a) (i).Design a combinational circuit to convert gray code to BCD. [Marks-12](ii).Design a Full Adder circuit with a Decoder. [Marks-4]or(b).Design a 4-bit magnitude comparator to compare two 4 bit numbers.

13.(a).Implement the Boolean function using 8:1 multiplexerF(A,B,C,D)=AB’D+A’C’D+B’CD’+AC’DOr

(b).Explain the different types of ROM

14.(a).Construct a full subtractor circuit and write a HDL program module for the same (i).Compare synchronous with Asynchronous counters [Mark-8](ii).Explain the behavioral Model with suitable example [Mark-8]or(b).(i).A positive edge triggered flip-flop has two inputs D1 and D2 and a control input that chooses between the two. Write an HDL behavioral description of this flip-flop. [Mark-8](ii).Construct and explain 4 stage Johnson counter. [Mark-8]

15.(a).(i).Explain the need for key debounce circuit [Mark-8](ii).What is the objective of state assignment in asynchronous circuit? Give hazard-free realization for the following Boolean functions [Mark-8]F(A,B,C,D)=SM(0,1,5,6,7,9,11)Or(b).An asynchronous sequential circuit is described by the following excitation and output function B=(A1’B2)B+(A1+B2)C=B(i).Draw the logic diagram of the circuit [Mark-5](ii).Derive the transition table and output map [Mark-6](iii).Describe the behavior of the circuit [Mark-5]

EC1206 Digital Principles and System DesignKings College Of Engineering, Punalkulam1KINGSCOLLEGE OF ENGINEERINGDEPARTMENT OF INFORMATION TECHNOLOGYQUESTION BANKSubject Code& Name : EC1206 Digital Principles and System DesignYear / Sem : II yr/ III semUNIT-1BOOLEAN ALGEBRA AND LOGIC GATESPART – A(2marks)1. What is meant by Digital Systems?2. What is meant by Decimal Systems?3. What is meant by Duality Theorem?4. Convert the number (111111) binary to decimal?5. Convert the number (83) octal to Decimal?6. Convert the number (34891) Decimal to octal?7. Convert the number (6725) octal to binary?8. Convert the number (1011010101) binary to octal ?9. Convert the number (4608) decimal to Hexadecimal ?

10. Convert ABC Binary to Hexadecimal ?11. Define Gray Code?12. Prove that x + x = x?13. Define Associative Law and Distributive law?14. Define Boolean algebra?15. Define Boolean Function?16. Define Min terms?17. Define Max terms?18. List out the Logic gates?19. Draw the Symbol of And gate and OR gate?20. Draw the neither Symbol of NOR, NAND and NOT gate?21. Draw the Symbol of Exclusive OR gate?22. Write the Truth Table of And gate?EC1206 Digital Principles and System DesignKings College Of Engineering, Punalkulam223. Write the Truth Table of Exclusive OR gate?24. Define Demorgan’s Theorem?25. Define Karnaugh Map?26. List out the types of K-Map?PART – B1. a. Explain the various types of K-Map with Examples (12)b. Prove that x + 1 = 1 (2)c. Prove that x + xy = x (2)2. a. Express the Complement of the Following function in sum of Midterms andproduct of MaxtermsF(A,B,C,D) = B’D+A’D + BD (10)b. Express the Complement of the following function in sum of MidtermsF(A,B,C,D) = (0,2,6,11,13,14) (6)3. a. Simply the Boolean Function Using Three Variable K-MapF(X, Y, Z) = (3, 4, 6, 7) (8)b. Simply the Boolean Function Using Four Variable K-MapsF(W,X,Y,Z) = (0,1,2,4,5,6,8,9,12,13,14) (8)4. a. Explain logic operations with NAND Gates? (8)b. Explain Multilevel NAND Gates? (8)5. a. Explain Implementation of NOR Gates ? (8)b. Explain AND- OR Invert Implementation (8)6. a. Explain BCD Code with Examples (6)b. Explain Excess 3 Code with Examples? (6)c. Convert the number (28) Decimal to Excess 3 Code (4)7. a. List out the Procedure for converting Binary to Gray Code (4)b. Convert the number (1011) binary to gray? (4)c. Explain 7 - Bit ASCII Code ? (8)EC1206 Digital Principles and System DesignKings College Of Engineering, Punalkulam3

UNIT –IICOMBINATIONAL LOGICPART – A(2marks)1. What is meant by Combination Circuits?2. Draw the Block Diagram of Combination circuit?3. What is meant by Half – Adder?4. What is meant by Half – Subtractor?5. What is meant by Full – Adder?6. What is meant by Full – Subtractor?7. What are Universal Gates?8. Explain the Hardware Description Language?9. What are the methods are available in HDL?10. What is meant by Netlist?11. What is Difference between Simulation and simulator?12. What is Synthesis tool?13. What is meant by VHDL Language?14. What is meant by Verilog HDL?15. What are elements of Verilog HDL?16. What is Test Bench?PART – B1. a. Explain the Design procedure for Combination Logic Circuits (6)b. Explain the Logic implementation of half–adder and half-subtractor (10)2. a. Explain Logical Implementation of Full – adder and Full – Subtractor (10)b. Draw the Logic Diagram for BCD to Excess 3 code Converter with Explain (6)3. a. Explain the analysis procedure for combinational circuit (6)b. Explain the 4- bit Full adder (4)c. Explain the Block Diagram of BCD Adder (6)4. a. Explain the 4 – Bit Magnitude Comparator (10)b. Explain the Design Procedure for HDL (6)EC1206 Digital Principles and System DesignKings College Of Engineering, Punalkulam45. a. What is meant by model and modeling ? (5)b. Explain the Hardware Simulation (5)c. Explain Hardware Synthesis (6)6. a. Explain the Binary to BCD Convertor (10)b. Explain the Binary Parallel adder (6)7. a. Explain the excess 3 to BCD Code Converter (10)b. Explain the Binary Adder- Subtractor (6)UNIT – IIIDESIGN WITH MSI DEVICESPART – A(2 marks)1. What is meant by Decoder and Encoder?2. What is meant by Multiplexer and Demultiplexer?3. Draw the Logic Diagram of 4:1 mux4. Draw the Logic Diagram of 1:4 Demux

5. What is meant by ROM?6. What are the three types of PLD?7. What are the types of ROM?8. Explain PROM?9. Explain EPROM ?10. Explain EEPROM ?PART- B1. a. Explain the Logic Diagram of 3 to 8 line Decoder (8)b. How to Construct the 4 x 16 Decoder with two 3 x 8 Decoder (8)2. a. Explain the 4 to 1 line Multiplexer (8)b. Explain the 2 to 1 line Multiplexer (8)EC1206 Digital Principles and System DesignKings College Of Engineering, Punalkulam53 a. Explain the Programmable Logic array (8)b. Explain the Programmable array Logic (8)4. a. Comparison between PROM, PLA and PAL (6)b. Realise the function gives using a PLA with 6 Input, 4 Outputs and 10 AND (10)GatesF1(A,B,C,D,E,F) = m(0,1,7,8,9,10,11,15,19,23,27,31,32,33,35,39,40,41,47,63)F2(A,B,C,D,E,F) = m(8,9,10,11,12,14,21,25,27,40,41,42,43,44,46,57,59)5. a. Write a behavioral for 4:1 MUX using Verilog HDL (8)b. Write a behavioral model for 1:4 DeMux using Verilog HDL (8)6. a. Write a structural model for 4:1 Mux and 1:4 DeMux using Verilog HDL (16)UNIT – IVSYNCHRONOUS SEQUENTIAL LOGICPART – A(2 marks)1. What is meant by sequential circuit?2. Draw the Block Diagram of sequential circuit?3. What is Flip Flop?4. What are the types of Flip Flop?5. What is meant by Race around condition?6. What is meant by Edge Triggered Flip Flop?7. What is meant by Set up time?8. What is meant by hold time?9. What is meant by propagation delay?10. What are categories of propagation delay?11. Define Tplh?12. Define Tphl ?13. Draw the Cross coupled inverters ?14. What is meant by Shift Register with types ?15. What is difference between Moore and Mealy Circuit Model?16. What is state diagram?EC1206 Digital Principles and System DesignKings College Of Engineering, Punalkulam6

17. Draw the state diagram for Mealy and Moore Circuit?18. What is meant by state equation?19. What is meant by state reduction ?20. What is meant by state assignment ?21. What is meant by counter ?22. What are the types of counter ?PART – B1. a. Write the verilog code generate for paralled load up / down counter (8)b. Write a verilog code for D Flip Flop and R-S Flip Flop (8)2. Explain R-S Flip Flop and Clocked R-S Flip Flop (16)3 .a. Explain S-R Flip Flop (8)b. Explain D Flip Flop (8)4. a. Explain JK Flip Flop (11)b. Explain T Flip Flop (5)5. a. Explain Master Slave Flip Flop (8)b. Explain the Edge Triggered Flip Flop (8)6. a. Convert it JK Flip Flop in to T Flip Flop (8)b. Convert it JK Flip Flop in to D Flip Flop (8)7. a. Convert it D Flip Flop in to T Flip Flop (8)b. Convert it T Flip Flop in to D Flip Flop (8)8. a. Explain Serial in Serial out Shift Register (8)b. Explain Serial in parallel out Shift Register (8)9. a. Explain parallel in parallel out Shift Register (8)b. Explain parallel in Serial out Shift Register (8)10. Design sequential circuit for a state diagram? (16)1/1 0010000100ac e bdEC1206 Digital Principles and System DesignKings College Of Engineering, Punalkulam7UNIT VASYNCHRONOUS SEQUENTIAL LOGICPART A(2marks)1. What is difference between Synchronous sequential circuit and Asynchronoussequential Circuit?

2. What is meant by secondary variable and Excitation variables?3. Draw a block diagram of Asynchronous Sequential circuits?4. What is meant by Races?5. What is meant by Cycle?6. What are two techniques are available in critical race Free State assignment?7. Draw the transition diagram with race free state assignment?8. What is one hot state assignment?PART – B1. a. Explain the one hot state assignement (8)b. Explain the shared – Row state assignment (8)2. Design an asynchronous sequential circuit that has two input x2 , x1 and one (16)output 2 when x1 = 0 the output 2 is 0. The first change in x2that occur whileX1 is 1 will cause output 2 to be1. The output 2 will remain 1 until x1 returns to0?00100110`10 11110111A0C0B0E0F1D1EC1206 Digital Principles and System DesignKings College Of Engineering, Punalkulam83. Explain the classification of Race- Free State Algorithm? (16)4. a. Explain the Hazards in combinational circuits? (6)b. Explain the Hazards in sequential circuits? (10)

CHAPTER 1 BOOLEAN ALGEBRA AND LOGIC GATES Number Base Conversions : 1. List the different number systems? i) Binary Number system ii) Octal Number system iii) Decimal Number system iv) Hexadecimal Number system 2. Express the following in decimal: a) (10110.0101)2, b) (16.5)16, c) (26.24)8, d) (FAFA.B)16, e) (1010.1010)2 (a) (10110.0101)2 = (1x24) + (0x23) + (1x22) + (1x21) + (0x20) + (0x2-1) + (1x2-2) + (0x2-3) + (1x2-4) = 16 + 4 + 2 + 0.25 +0.0625 = (22.3125)10 (b) (16.5)16 = (1x161) + (6x160) + (5x16-1) = 16 + 6 + (5 (0.0615)) = (22.3125)10 (c) (26.24)8 = (2x81) + (6x80) + (2x8-1) + (4x8-2) = 16 + 6 + 2/8 + 4/64 = (22.3125)10 (d) (FAFA.B)16

= (Fx163) + (Ax162) + (Fx161) + (Ax160) + (Bx16-1) = (15x163) + (10x162) + (15x161) + (10x160) + (11x16-1) = (64,250.6875)10 (e) (1010.1010)2 = (1x23) + (0x22) + (1x21) + (0x20) + (1x2-1) + (0x2-2) + (1x2-3) + (0x2-4) = 8 + 2 + 0.5 +0.125 = (10.625)10 3. Convert the following binary numbers to hexadecimal and to decimal: a) 1.11010, b) 1110.10 Explain why the decimal answer in (b) is 8 times that of (a). To convert from binary to hexadecimal: Each 4 binary digits are equal to 1 hexadecimal digit: a) (0001.11010)2 = (1.D0)16 b) (1110.1000)2 = (E.8)16 To convert from binary to decimal: a) (1.11010)2 = (1x20) + (1x2-1) + (1x2-2) + (0x2-3) + (1x2-4) + (0x2-5) = (1) + (0.5+0.25+0.0625) = (1.8125)10 b) (1110.10)2 = (1x23) + (1x22) + (1x21) + (0x20) + (1x2-1) + (0x2-2) = (8+4+2) + (0.5) = (14.5)10 The decimal answer in (b) is 8 times that of (a) because the binary number in (b) is the same as that in (a) except that the point is shifted to the right 3 digits and this means that it is multiplied by 23. 4. Convert (9B2.1A)H to its decimal equivalent. N = (9 x 162) + (B x 161) + (2 x 160) + (1 x 16-1) + (A (10) x 16-2) = 2304 + 176 + 2 + 0.0625 + 0.039 = (2 4 8 2 . 1 )10

5. Find the decimal equivalent of (346)7. (May, 2004) (346)7. = (3x72) + (4x71) + (6x70) = (181)10. 6. Convert 0.640625 decimal number to its octal equivalent. 0.640625 x 8 = 5.125 5 0.125 x 8 = 1.0 1 (0.640 625)10 =(0.51)8 7. Convert the (153.513)10 to octal. (May, 2010) Integer part:

8 153 8 19 -- 1 2 -- 3 = (231)8 Fractional part: 0.513 x 8 =4.104 4 0.104 x 8 =0.832 0 0.832 x 8 =6.656 6 0.656 x 8 =5.248 5 0.248 x 8 =1.984 1 0.984 x 8 =7.872 7 = (0.406517)8 (approximate) • (153.513)10 = (231. 406517)8 8. Convert 0.1289062 decimal number to its hex equivalent 0.1289062 x 16 = 2.0625 2 0.0625 x 16 = 1.0 1 Ans = (0.21)16

16. What is the range of values that can be represented using n-bit 2’s complement form of representation? What is the corresponding range with n-bit 1’s complement form? (May, 2006) The given number N in the base 2 having n digits. The 2’s complement of N is defined as follows. 2’s complement of N= + (2n-1- 1) to – (2n-1), Where, n is number of digits. The given number N in the base r= 2 having n digits. The (r-1)’s complement of N is defined as follows. 1’s complement of N= + (2n-1- 1) to – (2n-1-1) Where, N= given number or digit 17. Add (1 0 1 0)2 and (0 0 1 1)2 1 0 1 0

(+) 0 0 1 1 --------- 1 1 0 1 --------- Answer = (1 1 0 1)2 18. Substract (0 1 0 1)2 from (1 0 1 1)2 1 0 1 0 (-) 0 1 0 1 -------- 0 1 1 0 -------- Answer = (1 1 0)2 19. Why complementing a number representation is needed? Complementing a number becomes as in digital computer for simplifying the subtraction operation and for logical manipulation complements are used. 20. Obtain the 1’s and 2’s complement of the following binary numbers: a) 11101010 b) 01111110 c)00000001 d) 10000000 e) 00000000

Soln: 1’s complement : change every 1 to 0 and vice versa. 2’s complement: change every 1 to 0 and vice versa, then add (1) to the LSB. a) 11101010 1’s complement:(00010101)2 2’s complement : 0 0 0 1 0 1 0 1 (+) 1 -------------------- (0 0 0 1 0 1 1 0)2 --------------------- b) 01111110 1’s complement:(10000001)2 2’s complement : 10 0 0 0 0 0 1 (+) 1 --------------------- (10 0 0 0 0 1 0)2 --------------------- c)00000001 1’s complement:(01111110)2 2’s complement : 01 1 1 1 1 1 0 (+) 1 ---------------------- (1 1 1 1 1 1 1 1 )2 ----------------------- d) 10000000

1’s complement: (01111111)2 2’s complement : 01 1 1 1 1 1 1 (+) 1 ----------------------- (10 0 0 0 0 0 0 )2 ----------------------- e)00000000 1’s complement:(11111111)2

2’s complement : 01 1 1 1 1 1 1 (+) 1 ----------------------- (10 0 0 0 0 0 0 0 )2 ----------------------- 21. Find 2’s complement of (1 0 1 0 0 0 1 1)2 Soln: 0 1 0 1 1 1 0 0 1 - 1’s Complement (+)0 0 0 0 0 0 1 ---------------------- (0 1 0 1 1 1 0 1 0)2 - 2’s complement. ---------------------- 22. Substract (1 1 1 0 0 1)2 from (1 0 1 0 1 1)2 using 2’s complement method. Soln: 0 0 0 1 1 0 - 1’s Complement of (1 1 1 0 0 1)2 + 0 0 0 0 1 -------------- 0 0 0 1 1 1 - 2’s complement. -------------- 1 0 1 0 1 1 + 0 0 0 1 1 1 - 2’s comp. of (1 1 1 0 0 1)2 --------------- 1 1 0 0 1 0 in 2’s complement form --------------- To get the answer in true form , take the 2’s complement and assign negative number to the answer. Answer in true form - ( 0 0 1 1 1 0 )2 23. Perform subtraction using 1’s complement (11010)2 – (10000)2. 1 1 1 1 1 1 0 1 0

(+) 01 1 1 1 1’s complement of (10000)2 1 0 1 0 0 1 (+) 1 (Add carry to LSB) (0 1 0 1 0)2

  1 1 0 1 1 1 0There is no end carry.Answer is Y - X = - (1's complement of 1101110)= - (0010001)226. What are the different ways to represent a negative number? (Nov, 2006)The different ways of representing a negative number are-i . I nordinary arithmetic, the negative sign is indicated by a minus sign.i i . I nsigned magnitude representation, in which MSB is indicated as ‘0’ torepresent negative number.i i i . I nsigned 1’s complement representation,in which the negative number isindicated by its 1’s complement.i v . I nsigned 2’s complement representation, in which the negative number isindicated by its 2’s complement.Binary Codes :27. Mention the different type of binary codes?The various types of binary codes are,i . BCD code (B ina ry Coded dec ima l ) . i i . Se l f -complemen t ing code . i i i . The exces s -3 (X’ s -3 ) code . i v . G r a y c o d e . v . B i n a r y w e i g h t e d c o d e . v i . A l p h a n u m e r i c c o d e . v i i . T h e A S C I I c o d e . viii. Extended binary-coded decimal interchange code (EBCDIC).ix. Error-detecting and error-correcting code.x . H a m m i n g c o d e .28. State the different classification of binary cod

11. Convert (231.3)4 to base 7. (May, 2005) Convert the given number to decimal, (231.3)4 = (2x42) + (3x41) + (1x40) + (3x4-1)

= 32+ 12+ 1+ 0.75 = (45.75)10 Now, convert this number to base 7. Integer part: 7 45 6 -- 3 = (63)7 Fractional part: 0.75x 7 = 5.25 5 0.25x 7 = 1.75 1 0.75x 7 = 5.25 5 0.25x 7 = 1.75 1 = (0.5151)7 • (231.3)4 = (63.5151)7 12.Convert (634)8 to binary 6 3 4 110 011 100 Ans = (110011100)2 13. Convert the following number from one base to other (Nov, 2006) (a) (354.52)6 = ( )10 (b) (100)10 = ( )16 . (a) (354.52)6 = (3x62) + (5x61) + (4x60) + (5x6-1) + (2x6-2) = 108+ 30+ 4 + 0.8333+ 0.0555 = (142.888)10 • (354.52)6 = (142.888)10

(b) (100)10 16 100 6 -- 4 = (64)7 • (100)10 = (64)16. 14. A hexadecimal counter capable of counting upto atleast (10,000)10 is to be constructed. What is the minimum number of hexadecimal digits that the counter must have? (May, 2004) Soln: • (10,000)10 = (2710)16 Complements : 15. What are the different types of number complements? i) r’s Complement ii) (r-1)’s Complement.

  1 1 0 1 1 1 0There is no end carry.Answer is Y - X = - (1's complement of 1101110)= - (0010001)226. What are the different ways to represent a negative number? (Nov, 2006)The different ways of representing a negative number are-i . I nordinary arithmetic, the negative sign is indicated by a minus sign.i i . I nsigned magnitude representation, in which MSB is indicated as ‘0’ torepresent negative number.i i i . I nsigned 1’s complement representation,in which the negative number isindicated by its 1’s complement.i v . I nsigned 2’s complement representation, in which the negative number isindicated by its 2’s complem 

Binary Codes 27. Mention the different type of binary codes?The various types of binary codes are,i . BCD code (B ina ry Coded dec ima l ) . i i . Se l f -complemen t ing code . i i i . The exces s -3 (X’ s -3 ) code . i v . G r a y c o d e . v . B i n a r y w e i g h t e d c o d e . v i . A l p h a n u m e r i c c o d e . v i i . T h e A S C I I c o d e . viii. Extended binary-coded decimal interchange code (EBCDIC).ix. Error-detecting and error-correcting code.x . H a m m i n g c o d e .28. State the different classification of binary codes  

i i . N o n - w e i g h t e d c o d e s i i i . R e f l e c t i v e c o d e s i v . S e q u e n t i a l c o d e s v . A l p h a n u m e r i c c o d e s vi. Error Detecting and correcting codes.29. What is meant by bit?A binary digit is called bit30 . De f ine by t e?Group of 8 bits.31. State the steps involved in Gray to binary conversion?The MSB of the binary number is the same as the MSB of the gray code number.So write it down. To obtain the next binary digit, perform an exclusive OR operationbetween the bit just written down and the next gray code bit. Write down the result.32. What are error detecting codes? (Nov, 2007)When the digital information in the binary form is transmitted from one circuit or system to another circuit or system an error may occur. To maintain the data integritybetween transmitter and receiver, extra bit or more than one bit is added in the data. Thedata along with the extra bit/bits forms the code. Code which allow only error detectionare called error detecting codes.33. Convert gray code 101011 into its binary equivalent.Gray Code   : 1 0 1 0 1 1Binary Code: 1 1 0 0 1 034. State the abbreviations of ASCII and EBCDIC code?ASCII

-AmericanStandardCode for InformationInterchange.EBCDIC-EtendedBinaryCodedDecima lInformationCode.35. What is advantage of gray codes over binary number sequence?    (May, 2007

  The advantage of gray codes over the binary number is that only one bit in the code group changes when going from one number to the next.The g r ay code i s u sed i n app l i c a t i ons whe re t he no rma l s equence o f b ina ry number may produce an error or ambiguity during the transition from one number tonext.Boolean Algebra & Theorems :36. What are basic properties of Boolean algebra?The basic properties of Boolean algebra are commutative property, associativeproperty and distributive property.37. State the associative property of Boolean algebra.The associative property of Boolean algebra states that the OR ing of severalvariables results in the same regardless of the grouping of the variables.The associative property is stated as follows:A+ (B+C) = (A+B) +C38. State the commutative property of Boolean algebra.The commutative property states that the order in which the variables areOR edmakes no difference.The commutative property is:(A+B) = (B+A)39. State the distributive property of Boolean algebra.The distributive property states thatANDing several variables andOR ing t he result with a single variable is equivalent toOR ing the single variable with each of theseveral variables and thenANDing the sums.The distributive property is:A+BC= (A+B) (A+C)40. State De Morgan's theorem.De Morgan suggested two theorems that form important part of Boolean algebr  They are,1) The complement of a product is equal to the sum of the complements.(A.B)' = A'+B'2) The complement of a sum term is equal to the product of the complements.

(A+B)' = A'.B'41. State the absorption law of Boolean algebra.The absorption law of Boolean algebra is given by,•A+AB=A,•A (A+B) =A.42. Define duality property.Duality property states that, starting with a Boolean relation, you can deriveanother Boolean relation by1. Changing each OR sign to an AND sign2. Changing each AND sign to an OR sign3. Complementing any 0 or 1 appearing in the expressionFor Example:A+ A’= 1isA. A’= 043. Show that A+A’.B = A+B using the theorems of Boolean algebra.(Nov, 2005)LHS= A+A’.B= A+ AB + A’B[ A+AB = A]= A+ B (A+ A’)= A+ B (1)[A+ A’= 1]= A+ BCanonical Form :44. What are minterms? (May, 2008)Each individual term in standard SOP form is called minterms45. What are maxterms?  Each individual term in standard POS form is called maxterms.46. Find the minterms of the logical expression Y= A'B'C' +A'B'C +A'BC +ABC'Y = A'B'C' + A'B'C + A'BC + ABC'= m0 + m1 +m3 +m6= ∑m (0, 1, 3, 6)47. Convert the given expression in canonical SOP form Y = AC + AB + BCY = AC + AB + BC= AC (B + B’) + AB (C + C’) + (A + A') BC= ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC=ABC + ABC' +AB'C + AB'C'[A + A =1]= m7 + m6 +m5 +m4= ∑m (4, 5, 6, 7)48. Convert the following function into sum of product form ( A B + C ) ( B + C ’ D ) . ( M a y , 2 0 0 8 )= (AB.B+ B.C+ AB.C’D+ C.C’D)= AB+ BC+ ABC’D[B. B= 1] [C.C’= 0]AND each product term having missing literals, by ORing the literals and its complement= AB (C+ C’) (D+ D’) + BC (A+ A’) (D+ D’) + ABC’D= (ABC+ ABC’) (D+ D’) + (ABC+ A’BC) (D+ D’) + ABC’D=ABCD+ABCD’+ ABC’D+ ABC’D’+ABCD+ABCD’+ A’BCD+ A’BCD’+ ABC’D=

ABCD+ ABCD’+ ABC’D+ ABC’D’+ A’BCD+ A’BCD’.= m15+ m14+ m13+ m12+ m7+ m6•F(A,B,C,D)= ∑m( 6,7, 12,13,14,15)49. Write the maxterms corresponding to the logical expressionY = (A + B + C’) (A + B' + C') (A' + B' + C)= (A + B + C’) (A + B' + C') (A' + B' + C)=M1.M3.M6= ПM (1, 3, 6)  50. Find the complement of the functions F1= x'yz' + x'y'z and F2= x (y'z' + yz).By applying De-Morgan's theorem.F1' = (x'yz' + x'y'z)'= (x'yz')'(x'y'z)' = (x + y' + z) (x + y +z')F2' = [x (y'z' + yz)]'= x' + (y'z' + yz)'= x' + (y'z')'(yz)'= x' + (y + z) (y' + z')51. Find the complements for the following functions(a) F1= xy’+ x’y.(b) F2= ( x y + y ’ z + x z ) x . ( N o v , 2 0 0 7 ) (a) F1= xy’+ x’yF1’= (xy’+ x’y)’= (xy’)’. (x’y)’= (x’+y) (x+y’)= x’x+ x’y’+ yx+ yy’= x’y’+ xy.(b)F2= (xy + y’z + xz) x.F2’ = ((xy + y’z + xz) x)’= (xy + y’z + xz)’ + x’= [(xy)’ (y’z)’ (xz)’] + x’= [(x’+y’) (y+z’) (x’+z’)] + x’= [(x’y+ x’z’+ 0+ y’z’) ( x’+z’)] + x’= x’x’y+ x’x’z’+ x’y’z’+ x’yz’+ x’z’z’+ y’z’z’+ x’= x ’ y + x ’ z ’ + x ’ y ’ z ’ + x ’ y z ’ + x ’ z ’ + y ’ z ’ + x ’ [ x + x = x ] , [ x . x = x ] = x ’ y + x ’ z ’ + x ’ z ’ ( y ’ + y ) + y ’ z ’ + x ’ [ x + x ’ = 1 ] = x’y+ x’z’+ x’z’ (1) + y’z’+ x’= x’y+ x’z’+ y’z’+ x  = A B C64.Find the minterm of x y + y z + x y ' z ( N o v , 2 0 0 8 )= xy+ yz+ xy’z= xy+ z (y+ xy’)=xy+ z (y+ x)[x+ x’y = x+ y]65.

Simplify the following Boolean expression to a minimum number of literals:A ’ B ’ + A ’ C ’ D ’ + A ’ B ’ D + A ’ B ’ C D ’ ( M a y , 2 0 0 9 )= A’B’ (1+D) + A’C’D’+ A’B’CD’= A’B’ (1) + A’C’D’+ A’B’CD’[1+ x = 1]= A’B’+ A’C’D’+ A’B’CD’= A’B’+ A’B’CD’+ A’C’D’= A’B’ (1+CD’) + A’C’D’= A’B’ (1) + A’C’D’[1+ x = 1]= A’B’+ A’C’D’= A’ (B’+C’D’)Simplification Of Boolean functions using K-map &Tabulation Methods :66. What are the methods adopted to reduce Boolean function?i)  Karnaugh mapii) Tabular method or Quine Mc-Cluskey methodiii) Variable entered map technique.67. What is a Karnaugh map?A Karnaugh map or k map is a pictorial form of truth table, in which the mapd i ag ram i s made up o f squa re s , w i th e ach squa re s r ep re sen t i ng one min t e rm o f t he function.68. What is meant by three variable map  Three variable map have 8 minterms for three variables, hence the map consists of 8 squares, one for each minterm.69. What is a prime implicant?A prime implicant is a product term obtained by combining the maximumpossible number of adjacent squares in the map.70. What is an essential implicant?If a min term is covered by only one prime implicant, the prime implicant is saidto be essential.71. What are called don’t care conditions?In  some  logic  circuits  certain  input  conditions  never  occur,  therefore  thecorresponding output never appears. In such cases the output level is not defined, it canbe either high or low. These output levels are indicated by ‘X’ or‘d’ in the truth tablesand are called don’t care conditions or incompletely specified functions.72.Simplify the following Boolean function by Karnaugh map method:F (A, B, C, D) = ∑m (1, 5, 9, 12, 13, 15) (May, 2009)Therefore,F= ABD+ C’D+ ABC’73. What are the drawbacks of Karnaugh map? (Nov, 2007)The drawbacks of the K-map method arei. Generally it is limited to six variable map (i.e.) more than six variable involvingexpressions are not reduce

6. List out the advantages and disadvantages of Quine Mc-Cluskey method?

The advantages are,i. This is suitable when the number of variables exceed four.ii. Digital computers can be used to obtain the solution fast. iii. Essential prime implicants, which are not evident in K-map, can be clearly seen inthe final results.The disadvantages are,  i . Leng thy p rocedu re t han K-map . ii. Requires several grouping and steps as compared to K-map.i i i . I t i s m u c h s l o w e r . iv. No visual identification of reduction process.v. The Quine Mc-Cluskey method is essentially a computer reduction method.Logic Gates :77. What is a Logic gate?Logic gates are the basic elements that make up a digital system. The electronicgate is a circuit that is able to operate on a number of binary inputs in order to perform aparticular logical function.78. Distinguish between positive logic and negative logic. (Nov, 2003)In binary logic, two voltage levels represent the two binary digits, 1 and 0. If thehigher of the two voltages represents a 1 and the lower voltage represents a 0, the systemis called positive logic system. On the other hand, if the lower voltage represents a 1 andthe higher voltage represents a 0, then it is a negative logic system.79. What are the basic digital logic gates?The three basic logic gates are•AND gate•OR gate•NOT gate80. Which gates are called as the universal gates? What are its advantages?The NAND and NOR gates are called as the universal gates. These gates are usedto perform any type of logic application.81. Bubbled OR gate is equal to--------------NAND gate

  82. Bubbled AND gate is equal to--------------NOR gate83. How will you use a 4 input NOR gate as a 2 input NOR gate? (May, 2003)By connecting unused inputs to logic 0, we can use 4-input NOR gate as a 2 inputNOR gate.84. How will you use a 4 input NAND gate as a 2 input NAND gate? (Nov, 2002)By connecting unused inputs to logic 1, we can use 4-input NAND gate as a 2input NAND gate.85. What is meant by a functionally complete set of logic gates? (May, 2005)A set of logic gates by which we can implement any logic function is calledfunctionally complete set of logic gates.86. Show that a positive logic NAND gate is the same as a negative logic NOR gate.(May, 2003; Nov, 2004)Logic expression for NAND gate is, Y= (A .B)’Y= (A .B)’= A’ +B’

Y= A’ + B’ is the logic expression for negative logic NOR gate. 87. What happens when all the gates is a two level AND-OR gate network arereplaced by NOR gate (May, 2004; Nov, 2004, IT)The output will change. We will get complemented output when all applied inputsare complemented.88. Realize OR gate using NAND gate. (Nov, 2005)

.Define Combinational circuit. (May 2009)A combinational circuit consists of logic gates whose outputs at anytime aredetermined directly from the present combination of inputs, without regard to previousinputs.2 . W h a t i s a h a l f - a d d e r ?Ahalf-adder is a combinational circuit that can be used to add two bits. It has twoinputs that represent the two bits to be added and two outputs, with one producing theSUM output and the other producing the CARRY.

  27. Construct a 4-bit binary to gray code converter circuit and discuss itso p e r a t i o n . ( M a y , 2 0 0 6 )The gray code is often used in digital systems because it has the advantage thatonly bit in the numerical representation changes between successive.28.W h a t i s l o g i c s y n t h e s i s i n H D L ?         ( N o v , 2 0 0 6 ; N o v , 2 0 0 7 )Logic Synthesis is the automatic process of transforming a high level languagedescription such as HDL into an optimized netlist of gates that perform the operationsspecified by the source code.It is the process of deriving a list of components and their interconnections fromthe model of a digital system described in HDL.29.

L i s t t h e i m p o r t a n t f e a t u r e s o f H D L .                   ( N o v , 2 0 0 6 ; M a y 2 0 1 0 )1. It is specifically oriented to describe hardware structures and behaviors.2. It can be used to represent logic diagrams, Boolean expressions and other complex digital circuits.3. It is used to represent and document digital systems in a form that can be readby both humans and computers.30. Mention any two uses of HDL. (May, 2006)1. HDL is a language that describes the hardware of digital systems in textural form.2. It can be used to represent logic diagrams, Boolean expressions and other morecomplex digital circui  3. It is used to represent and document digital systems in a form that can be read byboth humans and computers.4. The language content can be stored and retrieved easily and processed bycomputer software in an efficient manner.CHAPTER 3DESIGN WITH MSI DEVICESDecoders & Encoders1. What do you mean by analyzing a combinational circuit?The reverse process for implementing a Boolean expression is called as analyzinga combinational circuit. (ie) the available logic diagram is analyzed step by step andfinding the Boolean function.2.What is decoder? (May,09)A decoder is a combinational circuit that decodes the binary information on ‘n’input lines to a maximum of 2N unique output lines. The general structure of decoder circuit is –

3.What is encoder? (May,10)An encoder is a combinational circuit that converts binary information from 2

ninput lines to a maximum of ‘n’ unique output lines. The general structure of encoder circuit isList out the applications of decoder?1. Decoders are used in counter system.2. They are used in analog to digital converter.3. Decoder outputs can be used to drive a display system.5.W h a t a r e t h e f u n c t i o n s o f e n c o d e r s a n d d e c o d e r s ? ( N o v , 2006)An encoder is a combinational circuit that converts binary information from 2ninput lines to a maximum of ‘n’ unique output lines.A decoder is a combinational circuit that decodes the binary information on ‘n’input lines to a maximum of 2nunique output lines. 6. Distinguish between decoder and encoder