download instant at · 2015. 2. 28. · download instant at 24 From Modelsim Command Prompt VSIM11> force ck '0' 1 ns, '1' 2 ns -repeat 2 ns VSIM12> force k '1' 1 ns , '0' 10 ns

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Chapter 4: Modeling Behavior

1. Construct a VHDL model of a parity generator for 7-bit words. The parity bit is

generated to create an even number of bits in the word with a value of 1. Do not

prescribe propagation delays to any of the components. Simulate the model and

check for functional correctness.

library ieee; use ieee.std_logic_1164.all; entity parity_generator7bit is port( input: in std_logic_vector(6 downto 0); z: out std_logic_vector(7 downto 0)); end parity_generator7bit; architecture behavioral of parity_generator7bit is begin parity_gen : process(input) is variable index: integer:=0; variable ones: integer:=0; begin for index in 0 to 6 loop if input(index) = '1' then ones := ones+1; end if; end loop; if (ones mod 2) = 0 then z(0) <= '0'; else z(0) <= '1'; end if; z(7 downto 1) <= input(6 downto 0); end process parity_gen; end architecture behavioral;


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From Modelsim Command Prompt

VSIM11> force input "1111000" 5 ns, "0000000" 10 ns, "0001000" 15 ns VSIM12> run 20 ns

2. Explain why you cannot have both a sensitivity list and wait statements within a

process.

Sensitivity list is the list of signals to which the process is sensitive. Any event on

any of the signals in the sensitivity list causes the process to be executed once. The

same is achieved by placing a wait statement at the beginning of the process. Wait

statements in general cause a process to be halted and executed from the statement

following the wait statement. It is possible to wait on one signal and be sensitive to

another leading to a deadlocked situation in which the process will never execute.

3. Construct and test a model of a negative edge-triggered JK flip-flop.

library ieee;


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use ieee.std_logic_1164.all; entity jkff is port( j,k,ck: in std_logic; q,qbar: out std_logic); end entity jkff; architecture behavioral of jkff is begin output : process(ck) is variable qtemp : std_logic := '1'; variable qbartemp : std_logic := '0'; begin if falling_edge(ck) then qtemp:= ((j and qbartemp) or ((not k) and qtemp)); qbartemp:= (((not j) or not (qbartemp)) and (k or qbartemp)); q<= qtemp; qbar<= qbartemp; end if; end process output; end architecture behavioral;


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VSIM11> force ck '0' 1 ns, '1' 2 ns -repeat 2 ns VSIM12> force k '1' 1 ns , '0' 10 ns VSIM13> force j '0' 1 ns, '1' 4 ns VSIM14> run 20 ns

4. Consider the construction of a register file with 8 registers, where each register is 32

bits. Implement the model with two processes. One process reads the register file,

while another writes the register file. You can implement the registers as signals

declared within the architecture and therefore visible to each process.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity regfile is


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port (ck, reset : in std_logic; reg : in std_logic_vector(2 downto 0); in_data : in std_logic_vector(31 downto 0); out_data : out std_logic_vector(31 downto 0); r_w : in std_logic); end regfile; architecture behavioral of regfile is type reg_file is array (0 to 7) of std_logic_vector(31 downto 0); signal reg_data : reg_file; begin read_process: process (ck, reset, r_w) begin if reset = '1' then -- asynchronous reset (active high) out_data <= (others => '0'); elsif (rising_edge(ck) and r_w = '1') then out_data <= reg_data(conv_integer(reg)); end if; end process read_process; write_process: process (ck, reset, r_w) begin -- process write_process if reset = '1' then -- asynchronous reset (active high) for index in 0 to 7 loop reg_data(index) <= (others => '0'); end loop; elsif (rising_edge(ck) and r_w = '0') then reg_data(conv_integer(reg)) <= in_data; end if; end process write_process; end behavioral;


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VSIM11> force reset '1' 0 ns, '0' 1 ns VSIM12> force ck '0' 2 ns, '1' 4 ns -repeat 4 ns VSIM13> force r_w '1' 1 ns, '0' 6 ns, '1' 10 ns VSIM14> force in_data "11111111111111111111111111111111" 5 ns VSIM15> force reg "110" 1 ns VSIM16> run 15 ns

5. Implement a 32-bit ALU with support for the following operations: add, sub, and,

or, and complement. The ALU should also produce an output signal that is asserted

when the ALU output is 0. This signal may be used to implement branch

instructions in a processor datapath.

library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity ALU32bit is port (


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in_A,in_B : in std_logic_vector(31 downto 0); out_data : out std_logic_vector(31 downto 0); opcode : in std_logic_vector(2 downto 0); out_zeros : out std_logic); end entity ALU32bit; architecture behavioral of ALU32bit is type reg_file is array (0 to 7) of std_logic_vector(31 downto 0); begin operation : process(opcode,in_A,in_B) is variable outd : std_logic_vector(31 downto 0); begin case opcode is when "000" => outd:= in_A + in_B; when "001" => outd := in_A - in_B; when "010" => outd := in_A and in_B; when "011" => outd := in_A or in_B; when "100" => outd := not(in_A); when others => outd:= (others => '0'); end case; if outd = x"00000000" then out_zeros <= '1'; else out_zeros <= '0'; end if; out_data <= outd; end process operation; end architecture behavioral;


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VSIM11> force opcode "000" 1 ns, "001" 4 ns, "010" 7 ns , "011" 10 ns, "100" 13 ns , "101" 16 ns VSIM12> force in_A 16#0000000F 1 ns VSIM13> force in_B 16#00000001 1 ns VSIM14> run 20 ns

6. Show an example of VHDL code that transforms an input periodic clock signal to

an output signal at half the frequency.

library ieee; use ieee.std_logic_1164.all; entity freq_divider is port (ck_in, reset : in std_logic; ck_out : out std_logic); end entity freq_divider; architecture behavioral of freq_divider is signal temp : std_logic; begin


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divide_freq : process (ck_in, reset) begin if reset = '1' then temp <= '0'; elsif rising_edge(ck_in) then -- rising clock edge temp <= not(temp); end if; end process divide_freq; ck_out <= temp; end architecture behavioral;


VSIM11> force reset '1' ,'0' 2 ns VSIM12> force ck_in '0' 1 ns, '1' 2 ns -repeat 2 ns


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7. Construct a VHDL model for generating four-phase non-overlapping clock signals.

Pick your own parameters for pulse width and pulse separation intervals. library ieee; use ieee.std_logic_1164.all; entity four_phase_clock is port (clk1,clk2,clk3,clk4 : out std_logic); end entity four_phase_clock; architecture behavioral of four_phase_clock is signal ck1,ck2,ck3,ck4 : std_logic; begin clock1 : process is begin ck1<= '1' after 1 ns , '0' after 2 ns ; wait for 5 ns; end process clock1; clock2 : process is begin ck2<= '1' after 2 ns, '0' after 3 ns ; wait for 5 ns; end process clock2; clock3 : process is begin ck3<= '1' after 3 ns , '0' after 4 ns ; wait for 5 ns; end process clock3; clock4 : process is begin ck4<= '1' after 4 ns , '0' after 5 ns ; wait for 5 ns; end process clock4; clk1<= ck1; clk2<= ck2; clk3<= ck3; clk4<= ck4; end architecture behavioral;


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VSIM11> run 30 ns

8. Implement and test a 16-bit up–down counter.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter is port ( reset, up_down,ck: in std_logic; count : out std_logic_vector(3 downto 0)); end entity counter; architecture behavioral of counter is signal upcnt,downcnt: std_logic_vector(3 downto 0); begin upcount : process(ck,reset,up_down) is begin if reset = '1' then upcnt <= "0000"; elsif (rising_edge(ck)and up_down = '1' ) then


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if upcnt = "1111" then upcnt <= "0000"; else upcnt <= upcnt + 1; end if; end if; end process upcount; downcount : process(ck,reset,up_down) is begin if reset = '1' then downcnt <= "0000"; elsif (rising_edge(ck) and up_down = '0') then if downcnt = "0000" then downcnt <= "1111"; else downcnt <= downcnt - 1; end if; end if; end process downcount; count <= upcnt when up_down = '1' else downcnt when up_down = '0'; end architecture behavioral;


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VSIM11> force up_down '1' ,'0' 20 ns VSIM12> force reset '1' 0 ns, '0' 1 ns VSIM13> force ck '0' 1 ns, '1' 2 ns -repeat 2 ns VSIM14> run 40 ns

9. Implement and test a VHDL model for the state machine for a traffic-light

controller [4] shown in Figure 4-26.

library ieee; use ieee.std_logic_1164.all; entity trafficlight is port(ck, reset : in std_logic; input : in std_logic; z : out std_logic_vector(1 downto 0)); end trafficlight; architecture behavioral of trafficlight is signal current_state, next_state : std_logic_vector(1 downto 0); begin current: process (ck, reset) begin if reset = '1' then current_state <= "00"; elsif rising_edge(ck) then current_state <= next_state; end if; end process current; determine_nextstate: process (current_state, input) begin case current_state is when "00" => if input = '0' then next_state <= "01"; else next_state <= "10"; end if; when "01" => if input = '0' then next_state <= "00"; else next_state <= "10"; end if; when "10" => if input = '0' then


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next_state <= "00"; else next_state <= "10"; end if; when others => next_state <= "00"; end case; end process determine_nextstate; output: process (current_state, input) begin -- process out_logic case current_state is when "00" => if input = '0' then z <= "10"; else z <= "00"; end if; when "01" => if input = '0' then z <= "01"; else z <= "00"; end if; when "10" => if input = '0' then z <= "01"; else z <= "00"; end if; when others => z <= "00"; end case; end process output; end behavioral;


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VSIM11> force ck '0' 1 ns, '1' 2 ns -repeat 2 ns VSIM12> force reset '1' 0 ns, '0' 1 ns VSIM12> run 15 ns

10. Consider a variant of Simulation Exercise 4.3 where we are interested in the occur-

rence of six 1’s in the bit stream. After six 1’s have been detected, the output

remains asserted until the state machine is reset. Construct and test this model.


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0/10

0/01

0/011/00 1/00

1/00

0 1

2

State machine for a traffic-light controller library ieee; use ieee.std_logic_1164.all; entity sequence_detector is port(ck, reset : in std_logic; input : in std_logic; z : out std_logic); end sequence_detector; architecture behavioral of sequence_detector is type statetype is (state0,state1,state2,state3,state4,state5,state6); signal current_state, next_state : statetype:=state0; begin updatestate : process (ck, reset) begin if reset = '1' then current_state <= state0; elsif rising_edge(ck) then current_state <= next_state; end if; end process updatestate; determine_nextstate: process (current_state, input) begin case current_state is when state0 => if input = '1' then next_state <= state1; else next_state <= state0; end if; when state1 => if input = '1' then next_state <= state2; else next_state <= state0; end if; when state2 =>


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if input = '1' then next_state <= state3; else next_state <= state0; end if; when state3 => if input = '1' then next_state <= state4; else next_state <= state0; end if; when state4 => if input = '1' then next_state <= state5; else next_state <= state0; end if; when state5 => if input = '1' then next_state <= state6; else next_state <= state0; end if; when state6 => next_state <= state6; when others => next_state <= state0; end case; end process determine_nextstate; output: process (current_state, input) begin case current_state is when state6 => z<= '1'; when others => z<='0'; end case; end process output; end behavioral;


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VSIM11> force ck '0' 1 ns, '1' 2 ns -repeat 2 ns VSIM12> force VSIM13> force input '0', '1' 4 ns,'0' 6 ns, '1' 8 ns, '0' 22 ns VSIM14> run 27 ns

11. Consider the following code sequence. At time 100 the process is activated due to

an event (0 to 1) on signal x. At this time the values of signals sig_s1, sig_s2, y, and

z are 0, 1, 1, and 0 respectively. What is the value of signal res2 scheduled for time

10 ns?.

proc2: process (x, y, z) -- Process 2

begin

L1: sig_s1 <= (x and y) after 10 ns;

L2: sig_s2 <= (sig_s1 xor z) after 10 ns;

L3: res2 <= (sig_s1 nand sig_s2) after 10 ns;

end process;


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res2 is scheduled to be the value ‘1’ after 10ns. This is so because the present

values of sig_s1 and sig_s2 are ‘0’. Only during the next event will the res2 signal

schedule the changes that were affected on sig_s1 and s-g_s2 due to the event on x.

12. Write a VHDL model for detecting equality between two four bit numbers.

library ieee; use ieee.std_logic_1164.all; entity equality_detector is Port ( A,B: in std_logic_vector(3 downto 0); z : out std_logic ); end entity equality_detector ; architecture behavioral of equality_detector is begin test: process(A,B) is begin if A=B then z<= '1'; else z<='0'; end if; end process test; end architecture behavioral;


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VSIM11> force A "0111" 0 ns, "1000" 3 ns VSIM12> force B "1000" VSIM13> run 10 ns

13. Write a VHDL model for a BCD counter(Binary Coded Decimal is the straight

binary values of decimal equivalents i.e values from 0000 to 1001 only since

decimals range only from 0 to 9 )

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_UNSIGNED.all; entity bcd_counter is Port ( clk : in std_logic;-- count input reset : in std_logic;-- resets count to 0 carry : out std_logic;-- Overflow (from 9) z : out std_logic_vector(3 downto 0) ); end bcd_counter; architecture behavioral of bcd_counter is signal c : std_logic_vector(3 downto 0); begin cnt: process(clk,reset) is


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begin if (reset = '1') then c <= "0000"; carry <= '0'; elsif rising_edge(clk) then if ( c = 9) then c <= "0000"; carry <= '1'; else c <= c + 1; carry <= '0'; end if; end if; end process cnt; z <= c; end behavioral;


VSIM11> force reset '1' 0 ns, '0' 1 ns VSIM12> force clk '0' 1 ns, '1' 2 ns -repeat 2 ns VSIM13> run 40 ns

download instant at · 2015. 2. 28. · download instant at 24 From Modelsim Command Prompt VSIM11> force ck '0' 1 ns, '1' 2 ns -repeat 2 ns VSIM12> force k '1' 1 ns , '0' 10 ns

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