doc-3 PHASE VOLTAGE or CURRENT DATA ACQUISITION.pdf

1

“3- PHASE VOLTAGE / CURRENT DATA

ACQUSITION USING EZDSPF2812”

Major Project report submitted in partial fulfillment of the requirements

For the award of the degree of

BACHELOR OF TECHNOLOGY

IN

ELECTRICAL AND ELECTRONICS ENGINEERING

By

AKHILA.S (08241A0257)

HARINI.M (08241A0268)

KIMEERA.T (08241A0270)

NEHA.P (08241A0278)

SAI PRATYUSHA.A (08241A0293)

Department of Electrical and Electronics Engineering

GOKARAJU RANGARAJU INSTITUTE OF

ENGINEERING& TECHNOLOGY, BACHUPALLY, HYDERABAD-72

2008 – 2012

2

GOKARAJU RANGARAJU INSTITUTE OF

ENGINEERING & TECHNOLOGY, BACHUPALLY, HYDERABAD-72

2008 – 2012

DEPARTMENT OF ELECTRICAL & ELECTRONICS

ENGINEERING

CERTIFICATE

This is to certify that the major project report entitled 3 - PHASE

VOLTAGE/CURRENT DATA ACQUSITION USING EZDSP F2812

that is being submitted by AKHILA.S, HARINI.M, KIMEERA.T, NEHA.P AND SAI

PRATYUSHA.A in partial fulfillment for the award of the Degree of Bachelor of

Technology in Electrical and Electronics Engineering to the Jawaharlal

Nehru Technological University is a record of bonafide work carried out by them under

my guidance and supervision. The results embodied in this project report have not been

submitted to any other University or Institute for the award of any Graduation degree.

Mr. P. M. Sharma Mr. M. Chakravarthy External

Examiner

HOD, EEE Associate Professor

GRIET Dept. of EEE

Hyderabad GRIET

3

ACKNOWLEDGEMENT

This is to place on record my appreciation and deep gratitude to the persons

without whose support this project would never have seen the light of day.

I wish to express my propound sense of gratitude to Mr. P. S. Raju, Director,

G.R.I.E.T for his guidance, encouragement, and for all the facilities to complete this

project.

I also express my sincere thanks to Mr. P. M. Sarma, Head of the Department,

G.R.I.E.T for extending his help.

I have immense pleasure in expressing my thanks and deep sense of gratitude to

my guide Mr. M. Chakravarthy, Associate Professor, Department of Electrical and

Electronics Engineering, G.R.I.E.T for his guidance throughout this project.

Finally, I express my sincere gratitude to all the members of faculty and friends

who contributed through their valuable advice and helped in completing the project

successfully.

AKHILA. S(08241A0257)

HARINI. M (08241A0268)

KIMEERA.T (08241A0270)

NEHA. P (08241A0278)

SAI PRATYUSHA. A (08241A0293)

4

ABSTRACT

With the increasing use of computers the usage of and need for digital signal

processing has increased. To use an analog signal on a computer, it must be digitized

with an analog-to-digital converter. Therefore, the first stage in many DSP systems is to

convert the real world smooth analog signals into digital form. This project deals with

sensing these analog signals (3-phase voltages and currents) and displaying them on the

virtual scope of the DSP.

The voltages and currents are sensed by using the voltage transformers and

current transformers. Since the Analog-to-Digital Converter of the DSP can only work on

DC voltage of magnitude 0-3 V, the analog signals thus given to the DSP must be in this

range. For this purpose, the secondary voltages of these transformers (i.e., sinusoidal

voltages of 3V RMS) are given to the op-amp through a potential divider circuit. A DC

offset is also given to the op-amp such that the output has the lowest peak of 0 V.

The voltages and currents sensed can be used for various applications like closed loop

DC buck-boost convertor, speed control of 3-phase induction motor, energy meter etc.

5

CONTENTS

LIST OF TABLES 8

LIST OF FIGURES 8

CHAPTER 1 10

INTRODUCTION 10

CHAPTER 2 11-17

ARCHTECTURE OVERVIEW OF eZdsp F2812

2.1 Introduction 11

2.2 Features of DSP 11

2.3 Block diagram 11

2.4 C28X CPU 12

2.5 TMS320C28X internal bussing 13

2.6 Memory 14

2.6.1 Memory map

2.7 eZdsp F2812 hardware 16

2.8 eZdsp F2812 connector/header pin diagram 17

CHAPTER 3 18-26

ANALOG TO DIGITAL CONVERTERS

3.1 Introduction 18

3.2 ADC module 18

3.3 ADC registers 20

6

3.3.1 ADC control registers

3.3.2 Maximum conversion channel registers

3.3.3 ADC channel select sequencing control register

3.3.4 ADC conversion result buffer registers

3.4 Analog interface 25

CHAPTER 4 27-31

CIRCUIT DESCRIPTION

4.1 Circuit 27

4.2 Circuit diagram 29

4.3 Simulation 29

CHAPTER 5 32-39

HARDWARE DESCRIPTION

5.1 Components used 32

5.1.1 Transformers 32

5.1.2 Potential divider 33

5.1.3 Diodes 33

5.1.4 Operational amplifier 33

5.1.5 Regulated DC supply 34

5.1.6 Load 34

5.1.7 DSP 35

5.1.8 Printed circuit board 35

5.2 Schematic and Board 36

5.3 Output 38

7

CHAPTER 6 40-41

RESULTS AND CONCLUSIONS

6.1 Work done in this project 40

6.2 Difficulties encountered during the project 40

6.3 Future scope 41

REFERENCES 42

APPENDIX A 43-46

APPENDIX B 47-54

APPENDIX C 55-56

APPENDIX D 57-60

APPENDIX E 61-62

8

LIST OF TABLES

Table 1: eZdsp F2812 connectors 17

Table 2: Electrical characteristics of LM1458N 61

Table 3: Absolute maximum ratings of 1N4007 62

Table 4: Thermal characteristics of 1N4007 62

Table 5: Electrical characteristics of 1N4007 62

LIST OF FIGURES

Fig.2.1: Architecture of eZdsp F2812 12

Fig.2.2: C28X CPU 13

Fig.2.3: Internal bussing 14

Fig.2.4: Memory mapping 15

Fig.2.5: eZdsp hardware 16

Fig.2.6: eZdsp F2812 connector 17

Fig.3.1 ADC module block diagram (dual sequencer mode) 19

Fig.3.2: ADC module block diagram (cascaded mode) 20

Fig.3.3: ADCTRL1 21

Fig.3.4: ADCTRL2 22

9

Fig.3.5: ADCTRL3 23

Fig.3.6: ADCMAXCONV 24

Fig.3.7: ADCCHSELSEQ 24

Fig.3.8: ADC Conversion result buffer 25

Fig.3.9: Analog pins 26

Fig.4.1: Block Diagram for sensing voltage signals 28

Fig.4.2: Block Diagram for sensing current signals 28

Fig.4.3: Circuit Diagram 29

Fig.4.4: Circuit in Multisim software 30

Fig.4.5: Simulation output 31

Fig.5.1 Potential transformer 32

Fig.5.2: Pin diagram of LM1458N dual OpAmp 33

Fig.5.3 Regulated DC power supply 34

Fig.5.4: eZdspF2812 35

Fig.5.5: Printed Circuit Board 36

Fig.5.6: Schematic in Eagle 37

Fig.5.7: Board 38

Fig.5.8: Currents in two phases 39

Fig.5.9: Voltages in two phases 39

10

Chapter 1

INTRODUCTION

“Digital Signal Processing” has become a very widely-used technology because

of the ease of implementation and advantages over analog signal processing. Analog

signal processing uses resistors, capacitors, inductors and amplifiers to perform

operations like filtering. These analog circuits, though cheap and easy to assemble, are

difficult to calibrate and modify. This difficulty also increases as the complexity of the

circuit increases. In the case of a Digital Signal Processor, the working of the circuit is

based on the software program that is loaded into the DSP. Any required modifications

can be easily done by changing the program. Higher order circuits can also be realized

easily by changing the software code, without any changes in the hardware. This greatly

helps in reducing the complexity of the circuits. Accuracy is another advantage with

using Digital Signal Processing. DSP involves operations on binary data that involves

only „1‟s and „0‟s, thus making it easier to analyze the systems.

The multitude of advantages associated with the use of Digital Signal Processors

has led to extensive research and development of advanced processors that have many

industrial applications. eZdspF2812 is one such Digital Signal Processor. This DSP

works only for inputs that have a range of 0V to 3V. Thus, modifying the signals into a

form that is acceptable by the DSP is an essential task.

Our project deals with this modification of signals so as to be given as inputs to

the DSP. It includes sensing the signals, limiting their magnitudes and removing any

zero-crossing present in the signals. The DSP is then programmed to accept and display

the signals. The programming of DSP can be done using MATLAB software, but it

involves problems related to interfacing the DSP with MATLAB. Using the Code

Composer Studio software to directly program the DSP is a better alternative.

11

ARCHITECTURE OVERVIEW OF eZdsp F2812

2.1 INTRODUCTION:

This architecture overview introduces the basic architecture of the TMS320C28x

(C28x) series of Digital Signal Processors. The C28x is ideal for applications combining

DSP, standard microcontroller processing, efficient C code execution, or operating

system tasks.

2.2 FEATURES OF DSP:

High performance 32-bit DSP

32 x 32 bit or dual 16 x 16 bit MAC

Atomic read-modify-write instructions

8-stage fully protected pipeline

Fast interrupt response manager

128Kw on-chip flash memory

Code security module (CSM)

Two event managers

12-bit ADC module

56 shared GPIO pins

Watchdog timer

Communications peripherals

2.3 BLOCK DIAGRAM:

The TMS320C28x is a 32-bit fixed point DSP that specializes in high performance

control applications such as, robotics, industrial automation, mass storage devices, lighting,

optical networking, power supplies, and other control applications needing a single processor to

solve a high performance application.

The C28x architecture can be divided into 3 functional blocks:

• CPU and busing

12

• Memory

• Peripherals

Fig.2.1 : Architecture of eZdsp F2812

2.4 C28x CPU:

The C28x is a highly integrated, high performance solution for demanding control

applications. The C28x is a cross between a general microcontroller and a digital signal

processor, balancing the code density of a RISC chip and the execution speed of a DSP with the

architecture, firmware, and development tools of a microcontroller.

13

Fig.2.2 C28X CPU

The C28x design supports an efficient C engine with hardware that allows the C compiler to

generate compact code. Multiple busses and an internal register bus allow an efficient and

flexible way to operate on the data. The architecture is also supported by powerful addressing

modes, which allow the compiler as well as the assembly programmer to generate compact code

that is almost one to one corresponded to the C code.

The C28x is as efficient in DSP math tasks as it is in system control tasks that

typically are handled by microcontroller devices. This efficiency removes the need for a second

processor in many systems.

2.5 TMS320C28x Internal Bussing :

As with many DSP type devices, multiple busses are used to move data between the memories

and peripherals and the CPU. The C28x memory bus architecture contains:

14

• A program read bus (22 bit address line and 32 bit data line)

• A data read bus (32 bit address line and 32 bit data line)

• A data write bus (32 bit address line and 32 bit data line)

Fig.2.3: Internal bussing

2.6 MEMORY:

The memory space on the C28x is divided into program and data space. There are different types

of memory available that can be used as both program or data space. They include

Flash memory

Single access RAM (SARAM), expanded SARAM

Boot ROM which is factory programmed with boot software routines or standard tables

used in math related algorithm.

2.6.1 MEMORY MAP:

The C28x CPU contains no memory, but can access memory both on and off the

chip. The C28x uses 32-bit data addresses and 22-bit program addresses. This allows for a total

15

address reach of 4G words (1 word = 16 bits) in data space and 4M words in program space.

Memory blocks on all C28x designs are uniformly mapped to both program and data space.

This memory map shows the different blocks of memory available to the program and

data space.

Fig.2.4: Memory mapping

16

2.7 eZdsp F2812 HARDWARE:

Fig.2.5: eZdsp hardware

17

2.8 eZdsp F2812 CONNECTOR/HEADER PIN DIAGRAM:

Fig.2.6: eZdsp F2812 connector

Table 1: eZdsp F2812 connectors

In this project we mainly focus on the P5/P9, the analog interface. Interfacing of the external

analog input and the DSP is done through these pins.

18

ANALOG TO DIGITAL CONVERTER

3.1 INTRODUCTION

The eZdspF2812 consists of a 12-bit analog-to-digital converter with 16 analog

input channels. The analog input channels have a range from 0 to 3 volts. Two input

analog multiplexers are used, each supporting 8 analog input channels. Each multiplexer

has its own dedicated sample and hold circuit. Therefore, sequential, as well as

simultaneous sampling is supported. Also, the ADC system features programmable auto

sequence conversions with 16 results registers. Start of conversion (SOC) can be

performed by an external trigger, software, or an Event Manager event.

3.2 ADC MODULE

The ADC module in the DSP F2812 consists of a 12-bit core. It has 16 analog

input pins which can be given inputs from 0V to 3V. These input channels are given

through two input multiplexers having 8 analog input channels each. There are two

sample/hold units for each input multiplexer. These sample/hold units enable the

operation of the ADC in simultaneous sampling or sequential sampling modes.

The autosequencer supports 16 conversions without the intervention of CPU.

When the sequencer is operated as two independent 8-state sequencers, the operation is

called dual-sequencer operation. When it is operated as one large 16-state sequencer, it is

said to be in the cascaded mode of operation. There are 16 individually addressable result

registers for storing the converted values. The different trigger sources for the start of

conversion are:

External triggers

Software commands

Event managers

The block diagram of a dual-sequencer mode ADC module is shown in Fig.3.1.

19

Fig.3.1 ADC module block diagram (dual sequencer mode)

20

The block diagram of the ADC module in cascaded mode is shown in Fig.3.2.

Fig.3.2 ADC module block diagram (cascaded mode)

3.3 ADC REGISTERS

3.3.1 ADC control registers

There are two control registers ADCTRL1, ADCTRL2 and ADCTRL3, all of

which are 16-bit registers. The addresses of the registers are 0X007100, 0X007101 and

0X007118 respectively. The bit descriptions of ADC control register ADCTRL1 are

shown in Fig.3.3.

21

Upper byte

Lower byte

Fig.3.3 ADCTRL1

The control register ADCTRL2 is explained in Fig.3.4.

22

Upper byte

Lower byte

Fig.3.4 ADCTRL2

23

The control register ADCTRL3 is shown in Fig.3.5.

Fig.3.5 ADCTRL3

3.3.2 Maximum conversion channels register

This register is used to specify the number of analog-to-digital conversions to be

done by the ADC. The value entered into this register is (the total number of conversions

needed – 1). The ADCMAXCONV register is shown in Fig.3.6.

24

Fig.3.6 ADCMAXCONV

3.3.3 ADC channel select sequencing control register

There are four channel select sequencing control registers, each having 16 bits.

There are 16 channels for conversion – CONV00 to CONV15. Each channel select

sequencing register controls four conversion channels as shown in Fig.3.7.

Fig.3.7 ADCCHSELSEQ

25

3.3.4 ADC conversion result buffer registers

There are 16 result buffer registers, which are used to store the converted values.

Fig.3.8 ADC conversion result buffer register

3.4 ANALOG INTERFACE

The pins of the ADC are shown in Fig.3.9.

26

Fig.3.9 Analog pins

27

CIRCUIT DESCRIPTION

4.1 CIRCUIT DESCRIPTION:

The circuit is designed so that it can modify the rated 3-phase voltages and

currents (obtained from the supply – 415V, 50Hz) in such a way that they can be given to

the DSP. The DSP works only with inputs with values less than 3V. Also, the signals

given as inputs to the DSP must be entirely positive, i.e., there should not be any zero-

crossing in the signal waveform. The offset given is then removed using software

programming, i.e., after signals have been acquired by the DSP.

The 3-phase voltages are first sensed using 230V/3V potential transformers and

the 3-phase currents by using 5A/0.038A current transformers. The currents thus sensed

are converted to voltage signals using a 100 ohm resistor in each phase. The loads used in

the current sensing circuits are lamp loads, each of 200W. Four lamps are used in each

phase. This gives a voltage signal of approximately 3V, corresponding to a primary

current of 3.68A.

Sinusoidal signals of RMS value 3V are thus obtained from the current and

potential transformers. Each signal is given to a potential divider made of three 1 Kohm

resistors connected in series, thus giving a drop of 1V (RMS) across each resistor.

1N4007 diodes having cutoff voltage of 0.7V are used to generate a DC offset.

Two diodes are used in series to give a total offset of 1.4V. This DC offset and the

sinusoidal signal of 1V are given as inputs to the inverting terminal of an opamp. The

opamp is used as an adder so the output is an inverted sum of the inputs. If „A‟ and „B‟

are the inputs to the inverting terminal of the opamp, then the output when the opamp is

used as an adder is given by – (A+B). This output signal is inverted using another opamp.

In this project, the dual opamp LM1458N has been used to perform both addition and

inversion. The final output is thus a DC sinusoidal signal that has a peak to peak value of

approximately 2.4V.

28

The block diagram for sensing one voltage signal is shown in fig. 4.1

Fig. 4.1: Block Diagram for sensing voltage signals

The block diagram for sensing one current signal is shown in Fig. 4.2.

Fig. 4.2: Block Diagram for sensing current signals

29

4.2 CIRCUIT DIAGRAM:

The circuit diagram for sensing one signal is shown in Fig.4.3.

Fig.4.3 Circuit Diagram

4.3 SIMULATION:

The circuit shown above gives a DC sinusoidal output which has a peak-to-peak

value of approximately 2.3V. The circuit can be simulated in Multisim software and the

output can be verified. The circuit, when connected in the Multisim software, looks as

shown in Fig.4.4.

30

Fig.4.4 Circuit in Multisim software

The output of the simulation done in the Multisim software is shown in Fig.4.5.

31

Fig.4.5 Simulation output

The screen of the virtual oscilloscope shows both input and output waveforms.

The sinusoidal waveform in yellow is the input waveform, and the one in blue is the

output waveform. It can be seen that the output is offset from the input to make it a

positive waveform.

32

HARDWARE DESCRIPTION

5.1 COMPONENTS USED:

5.1.1 Transformers:

The rating of the supply voltage is 230V, 50Hz. This voltage is stepped down to a

value agreeable to the circuit used. Similarly, the current signals sensed are converted to

voltage signals of magnitude agreeable to the circuit used. In order to achieve this,

potential and current transformers are used.

The transformation ratio of potential transformers used is 230V/3V and the

current rating is 1A. Two such transformers are used in two phases and the voltage of the

third phase is obtained from these two signals.

The rating of the current transformers used is 5A/0.038A. A 1W, 100 ohm

resistor is connected across the secondary terminals in order to convert the current signal

into a voltage signal. The same circuitry used for voltage signal sensing can now be used

for sensing current signals also. A potential transformer is shown in Fig.5.1.

Fig.5.1 Potential Transformer

33

5.1.2 Potential divider:

The 3V AC voltage signal is given to a potential divider and an AC voltage of 1V

is taken from it. The potential divider is made of three 1 Kohm resistors. The output is

taken across one resistor, so 1V is obtained.

5.1.3 Diodes:

The diodes used in the circuit are 1N4007. These diodes are used to produce a DC

offset voltage. The cutoff voltage for a 1N4007 diode is 0.7V. Using two diodes in series,

an offset of 1.4V is generated. The diodes are connected to a DC voltage of 12V. In order

to limit the current to its maximum value, a resistance of 100 ohms is used in series with

the diodes.

5.1.4 Operational Amplifier:

The dual opamp LM1458N is used for summation and inversion. The data sheet is

provided in the appendix E.

Fig.5.2: Pin diagram of LM1458N dual OpAmp

34

The dual opamp LM1458N is chosen as both summation and inversion operations are

required. The two inputs, i.e., the sinusoidal input and the DC offset are given to pin 2,

the inverting input of opamp A. The output of this opamp obtained at pin 1 is an inverted

sum of the two inputs. This is then given as an input to the inverting input terminal (pin

6) of opamp B. The final output obtained at pin 7 is the required DC sinusoidal signal.

The dual opamp HA17458 can also be used in the place of LM1458N.

5.1.5 Regulated DC supply:

The DC supplies of +12V and -12V required for the operation of LM1458N, are

given with the help of a regulated DC supply. The regulated DC power supply used in

this project is shown in Fig.5.3.

Fig.5.3 Regulated DC power supply

5.1.6 Load:

To sense the 3-phase supply currents, loads must be connected in each phase. The

loads used in this project are lamp loads. Four lamps of 200W each are placed in each

phase. The current sensed by this load is 2.4A.

35

5.1.7 DSP:

The Digital Signal Processor circuit used is F2812, which contains the processor

TMS320C28x. The DSP is shown in Fig.5.4.

Fig.5.4 eZdspF2812

5.1.8 Printed Circuit Board:

The PCB designed for sensing the 3-phase currents and voltages on the basis of

the circuit in Fig.4.3 in shown in Fig.5.5. This PCB consists of six sensing circuits, so all

the voltages and currents can be sensed simultaneously.

36

Fig.5.5 Printed Circuit Board

5.2 SCHEMATIC AND BOARD:

The circuit used to limit the input AC signal to a range of 0-3 V has been tested on the

general purpose board. After obtaining satisfactory results, a PCB has been designed.

Eagle software is used to design the Printed Circuit Boards. The schematic diagram shows

the connections between different components. It contains circuits for sensing 3 phase

voltages and currents.

The schematic connected in Eagle is shown in the figure below:

37

Fig.5.6 Schematic in Eagle

The board is obtained from this schematic. Board option in the Eagle allows the user to

switch from the schematic to the board where connections are present based on the

schematic. The board layout shows the placement of components on the Printed Circuit

Board. Eagle allows us to place the components so that they occupy optimum space. We can

also select the type of routing (its thickness, number of routing layers, etc). The components

are to be placed on the board in such a way that the routing is possible without any

overlap. Double-layer routing is used in this Project. The PCB is then manufactured on the

basis of this board layout. The board is shown in the figure below:

38

Fig.5.7 Board

5.3 OUTPUT

The outputs obtained from the PCB are given to the input pins of the ADC of the

DSP. The ADC is programmed using the Code Composer Studio software to accept the

inputs and convert them into digital values. The code is written to send the inputs into the

input channels of the ADC, subtract the offset given to the signals, place the converted

values in the output buffers and display the acquired signals in the virtual scope. It can be

seen in the virtual scope that the phase difference between two phase voltages or currents

is 1200.

The signals displayed in the virtual scope are shown in Fig.5.6 and 5.7.

39

Fig.5.8 Currents in two phases

Fig.5.9 Voltages in two phases

40

RESULTS AND CONCLUSIONS

6.1 WORK DONE IN THIS PROJECT:

The analog pins of ADC of the DSP have a range of 0V to 3V. So, a circuit is

designed to modify the input signals. The dual opamp LM1458N is used for this

purpose. The PCB is designed using eagle software.

Thorough study on the eZdsp F2812 is carried out. Since acquiring the

current/voltage signals requires interfacing through the ADC pins, stress has been

laid on this part. The various registers required for the programming purpose are

also studied.

Program development is done. The program is written in C language using Code

Composer Studio 3.1 software. The method of building the program and

executing it is also studied.

The current/voltage signals thus obtained can be used for various applications like energy

meter, speed control of 3-phase induction motor, closed loop buck-boost convertor.

The current/voltage signals have not only been displayed but Clarke transformation for

the conversion of 3-phase signals to 2-phase signals has also been done.

6.2 DIFFICULTIES ENCOUNTERED DURING THE

PROJECT:

Initially, zener diode was used for the generation of offset but the voltage drop

across this zener diode was not sufficient to obtain the sinusoidal voltage with its

lowest peak at 0V. Then,diodes in anti-parallel were connected to obtain the

required value but in vain. Finally, by discussing and analyzing with our project

team, diodes were connected in series to obtain the required offset of 1.4V.

The PCB designing was also a difficult task as it contains 6 circuits. Hence,

routing in double-layer has been done.

41

As the CCS 3.1 is an alien software to us, the loading and executing the program

was also a challenging job. It was overcome with the help of our project guide.

Loads which gave an output of 2.4A in the secondary of the transformer were also

difficult to obtain. Initially, a 0.5HP 3-phase induction motor was used but due to

insufficient secondary current, it has been replaced by four lamp loads of 200W in

each phase with the help of the faculty.

6.3 FUTURE SCOPE

Digital Signal Processors are mainly used in closed-loop systems having

feedback, like the vector control of Induction Motors, buck-boost converters, etc.. The

basic requirement for these applications is to feed the output back into the DSP for

processing and eliminating the error. DSP‟s are also used in open-loop control, though

the systems that use open-loop control are very few. For all these applications, the inputs

given to the DSP have certain restrictions. In this project, a circuit has been designed to

make the inputs comply with the restrictions of the DSP. Hence, it becomes the basis for

all the applications that involve the control of a system using DSP.

In the current project, the supply voltges and currents have been sensed and

acquired into the DSP. These signals can now be used to calculate power and energy of

the supply circuit. It can therefore be used in energy meters.

It can be used in the vector speed control of AC Induction Motors, where the

voltages and currents of the IM are fed back to the DSP.

Whatever the application in which DSP is used, the data acquisition is done in the

same way as is done in this project. Hence, this becomes the foundation for for most of

the DSP-based applications.

42

REFERENCES

Websites:

[1].http://www.kanecomputing.co.uk/ezdsp_f2812.htm

[2].http://www.kanecomputing.co.uk/code_composer_studio_v3.3.htm

[3].http://cnx.org/content/m11686/latest/

[4].http://c2000.spectrumdigital.com/ezf2812/docs/ezf2812_techref.pdf

Textbooks :

[1] R. Lyons, "Understanding Digital Signal Processing ", 2nd, Prentice Hall PTR.,

2004.

[2] S. W. Smith, "The Scientist and Engineer's Guide to Digital Signal Processing",

2nd, California Technical Publishing, 1999.

43

APPENDIX A

Program:

Watch Variables:

Voltage1[256] Last 10 ADCRESULT0 values

Voltage2[256] Last 10 ADCRESULT1 values

voltage3[256] Last 10 ADCRESULT2 values

current2[256] Last 10 ADCRESULT4 values

current3[256] Last 10 ADCRESULT5 values

ConversionCount Current result number 0-255

LoopCount Idle loop counter

Program:

#include "DSP281x_Device.h"

#include "DSP281x_Examples.h"

#include "IQmathLib.h"

#define offset 0x07FF

interrupt void adc_isr(void);

Uint16 LoopCount;

Uint16 ConversionCount;

int16 Gain;

int16 Voltage1[256];

int16 Voltage2[256];

int16 Voltage3[256];

int16 current1[256];

int16 current2[256];

int16 current3[256];

int16 Vas[256];

44

int16 Vbs[256];

int16 power[256];

main()

{

InitSysCtrl();

SysCtrlRegs.HISPCP.all = 0x3;

EDIS;

DINT;

InitPieCtrl();

IER = 0x0000;

IFR = 0x0000;

InitPieVectTable();

EALLOW;

PieVectTable.ADCINT = &adc_isr;

EDIS;

InitAdc();

PieCtrlRegs.PIEIER1.bit.INTx6 = 1;

IER |= M_INT1;

EINT;

ERTM;

LoopCount = 0;

ConversionCount = 0;

AdcRegs.ADCMAXCONV.all = 0x0005;

AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;

AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;

AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2;

AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3;

AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4;

45

AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5;

AdcRegs.ADCTRL2.bit.EVA_SOC_SEQ1 = 1;

AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1= 1;

EvaRegs.T1CMPR = 0x0080;

EvaRegs.T1PR = 0xFFFF;

EvaRegs.GPTCONA.bit.T1TOADC = 1;

EvaRegs.T1CON.all = 0x1042;

while(1)

{

LoopCount++;

}

}

interrupt void adc_isr(void)

{

Voltage1[ConversionCount] = (AdcRegs.ADCRESULT0 >>4) - offset;

Voltage3[ConversionCount] = (AdcRegs.ADCRESULT2 >>4) - offset;

Voltage2[ConversionCount] = - Voltage1[ConversionCount] - Voltage3[ConversionCount];

current1[ConversionCount] = (AdcRegs.ADCRESULT3 >>4) - offset;

current2[ConversionCount] = (AdcRegs.ADCRESULT4 >>4) - offset;

current3[ConversionCount] = - current1[ConversionCount] - current2[ConversionCount];

power[ConversionCount] =-( _IQmpy(Voltage1[ConversionCount],current1[ConversionCount]) +

_IQmpy(Voltage2[ConversionCount],current2[ConversionCount]) +

_IQmpy(Voltage3[ConversionCount],current3[ConversionCount]));

if(ConversionCount == 255)

{

ConversionCount = 0;

}

46

else ConversionCount++;

Vas[ConversionCount] = Voltage1[ConversionCount];

Vbs[ConversionCount] = _IQmpy((Voltage1[ConversionCount] +

_IQmpy(_IQ(2),Voltage3[ConversionCount])),_IQ(0.57735026918963));

AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;

AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

return;

}

47

APPENDIX B

CODE COMPOSER STUDIO

Code Composer Studio™ (CCStudio) Integrated Development Environment (IDE) is a

key element of the eXpressDSP Software and Development Tools strategy from Texas

Instruments. CCStudio delivers all of the host tools and runtime software support for

TMS320 DSP and OMAP based real–time embedded applications. CCStudio‟s easy to

use IDE allows DSP designers of all experience levels to move quickly through each

phase of the application development process including design, code and build, debug,

analyze and tune. The familiar tools and interfaces allow users to get started faster and

become productive immediately. The IDE includes DSP/BIOS support, real-time analysis

capabilities, debugger and optimization tools, C/C++ Compiler, Assembler, Linker,

integrated CodeWright editor, visual project manager and a variety of simulators and

emulation drivers. The developer can take advantage of time–saving, stress relieving

productivity tools that get their applications to market quicker and take advantage of

sophisticated debug tooling allowing them to find and fix real time issues.

The tuning and optimization features enable developers to produce highly

efficient applications taking full advantage of the device capabilities. Expected extension

of a source file is .ASM for assembly and .C for C programs. The concept of COFF tools

is to allow modular development of software independent of hardware concerns. An

individual assembly language file is written to perform a single task and may be linked

with several other tasks to achieve a more complex total system. Writing code in modular

form permits code to be developed by several people working in parallel so the

development cycle is shortened. Debugging and upgrading code is faster, since

components of the system, rather than the entire system, is being operated upon. Also,

new systems may be developed more rapidly if previously developed modules can be

used in them.

Code developed independently of hardware concerns increases the benefits of

modularity by allowing the programmer to focus on the code and not waste time

48

managing memory and moving code as other code components grow or shrink. A linker

is invoked to allocate systems hardware to the modules desired to build a system.

Changes in any or all modules, when re-linked, create a new hardware allocation,

avoiding the possibility of memory resource conflicts.

Projects

Code Composer works with a project paradigm. Essentially, within CCS a project for

each executable program is created. Projects store all the information required to build

the executable. For example, it lists things like: the source files, the header files, the

target system‟s memory-map, and program build options

49

The project information is stored in a .PJT file, which is created and maintained by CCS.

To create a new project, select the Project:New… menu item.

Along with the main Project menu, we can also manage open projects using the right-

click popup menu. Either of these menus allows to Add Files… to a project. We can also

drag-n-drop files onto the project from Windows Explorer

Procedure to create a new Project

1. Double click on the Code Composer Studio icon on the desktop. Maximize Code

Composer Studio to fill the screen. The menu bar (at the top) lists File ... HelpNote the

horizontal tool bar below the menu bar and the vertical tool bar on the left-hand side

2. A project is all the files needed to develop an executable output file which can be run

on the DSP hardware. To create a new project for a lab. On the menu bar click Project.

Source files (by reference)

Source (C, assembly)

LibrariesLibraries

DSP/configurationDSP/BIOS configuration

Linker filesLinker command files

Project settings:

Build Options (compiler and assembler)

Build configurationsBuild configurations

DSP/BIOSDSP/BIOS

Linker

50

Type Lab2 in the project name field and make sure the save in location is:

C:\C28x\LABS\LAB2. This will create a .pjtfile which will invoke all the necessary tools

(compiler, assembler, linker) to build the project. It will also create a debug folder that

will hold immediate output files.

3. Project Add Files to Project in the same lab exercise. Change the “files of type” to

view C source files (*.c) and select Lab2.c and click OPEN. This will add the file Lab2.c

to the newly created project.

4. Add Lab2a.cmd to the project using the same procedure. This file will be edited during

the lab exercise.

5. Next, add the compiler run-time support library. To the

project(C:\ti\c2000\cgtools\lib\rts2800_ml.lib).

6. In the project window on the left click the plus sign (+) to the left of Project. Now,click

on the plus sign next to Lab2.pjt. The Lab2a.cmd file is listed.Click on Source to see the

current source file list (i.e. Lab2.c).

Project Build Options

7. There are numerous build options in the project. The default option settings are

sufficient for getting started.

Click: Project Build

Options…

8. Select the Linker tab. The .out and .map files are created. The .out file is the

executable code that will be loaded into the DSP. The .map file will contain a linker

report showing memory usage and section addresses in memory.

9. Set the Stack Size to 0x200. Select OK and then close the Build Options window.

Edit the Linker Command File - Lab2a.cmd

10. To open and edit Lab2a.cmd, double click on the filename in the project window.

11. Edit the Memory{} declaration by describing the system memory shown on the

“Lab2a: Linker Command File” slide

12. In the sections{} area, a section called .reset has already been

allocated. The .reset section is part of the rts2800_ml.lib, and is not needed. By

51

putting the TYPE = DSECT modifier after its allocation, the linker will ignore

this section and not allocate it.

13.Place the sections defined on the slide into the appropriate memories via the

Sections{}area.

Build and Load the Project

14. The top four buttons on the horizontal toolbar control code generation.

15. Code Composer Studio can automatically load the output file after a successful build.

On the menu bar click: Option Customize… and select the “Program Load Options”

tab, check “Load Program After Build”, then click OK.

16. Click the “Build” button and watch the tools run in the build window. Check for

errors. When an error occurs, scroll the build window at the bottom of the Code

Composer Studio screen until the error message (in red) is seen, and double-click the

error message. The editor will automatically open the source file containing the error, and

position the mouse cursor at the correct code line.

17. Fix the error by adding a semicolon at the end of the "z = x + y" statement. For future

knowledge, realize that a single code error can sometimes generate multiple error messages at

build time.

18. Rebuild the project (there should be no errors this time). The output file should automatically

load. The Program Counter should be pointing to _c_int00 in the Disassembly Window.

19. Under Debug on the menu bar click “Go Main”. This will run through the C-environment

initialization routine in the rts2800_ml.lib and stop at main() in Lab2.c.

Debug Environment Windows

It is standard debug practice to watch local and global variables while debugging code. There are

various methods for doing this in Code Composer Studio.

Two of them are: memory windows, and watch windows.

20. Open the memory window to view the global variable “z”.

Click: View Memory on the menu bar.

Code Composer Studio is case sensitive.

52

Set the properties format to “Hex – TI style.” This will give more viewable data in the

window. Click OK to close the window property selection screen. The memory window

will now open. You can change the contents of any address in the memory window by

double-clicking on its value. This is useful during debug.

21. Open the watch window to view the local variables x and y.

Click: View Watch Window on the menu bar.

Click the “Watch Locals” tab and the local variables x and y are already present. The

watch window will always contain the local variables for the code function currently

being executed.

(Note that local variables actually live on the stack. You can also view local variables in a

memory window by setting the address to “SP” after the code function has been entered).

22. We can also add global variables to the watch window if desired. To add the global

variable “z”, click the “Watch 1" tab at the bottom of the watch window. In the empty

box in the "Name" column, type “z”. No ampersand is used here. Check that the watch

window and memory window both report the same value for “z”. Changing the value in

one window also changes the value in the other window.

53

The define The CCS Watch Window using #define

54

The Structures The CCS Watch Window using

Structures

55

APPENDIX C

SOFTWARE USED – EAGLE

EAGLE is an EDA program by CadSoft for creating printed circuit boards. The name is

an acronym formed from Easy Applicable Graphical Layout Editor. CadSoft Eagle and

the company in September 2009, Premier Farnellsells, a supplier of electronic

components. The software consists of several components: Layout Editor, Schematic

Editor, Auto router and an extensible component database. It is available for the

platforms Microsoft Windows, Linux and MacOSX.

56

It exists for non-commercial use; a free version on a schematic sheet, half Euro card

mm × 80 mm and two signal layers is limited to 100.

The schematic editor can be used by a special component library for programming a

MicroSPS.

57

APPENDIX D

SOFTWARE USED - MULTISIM

NI Multisim is an easy-to-use schematic capture and simulation environment that

engineers, students, and professors can use to define and simulate circuits. This article

shows you how to capture and simulate a simple circuit in Multisim.

This tutorial takes less than 30 minutes to complete and consists of 50 short steps.

The example circuit in the article is an amplifier circuit. This noninverting operational

amplifier configuration consists of one active component (the operational amplifier) and

two passive resistor components that will be used to complete the feedback network to

provide gain in this circuit.

step 1: Open Multisim

58

2.placing the components

59

3.Placing the measuring instruments:

5.Run a simulation :

60

61

APPENDIX E

DATA SHEETS:

DATA SHEET OF LM1458N:

Table 2: Electrical characteristics of LM1458N

62

DATA SHEET OF 1N4007:

Table 3

Table 4

Table 5