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Rise Time < 30 ms At No/Full Load, 115 Vac & 230 Vac
Start-up Time < 1 .5 s 90 ~ 264 Vac and 0 ~ 2 A
Over Shoot < 6.4 V At 1 m USB Cable End
Transient Response 4.5 ~ 5.5 V 0.1−1.9 A, 0.25 A/�s, 10 ms Cycle
Circuit DescriptionThis design note describes a 10.6 W, universal AC input,
isolated Quasi-Resonant flyback converter for smart phone,tablet charger and smart socket power supply etc.
The featured power supply is a primary side constantvoltage and current regulation utilizing ON Semiconductor’snew NCP1360 current mode controller which is in TSOP−6package. This design note provides the complete circuitschematic details, layout, test data and BOM for 5.3 V, 2 Apower supply.
Both NCP1360BBCC and NCP1360BCCC are all testedin this design, it has almost same performance exceptstandby power and dynamic response.
1. Input Circuit:Rectifier, filter and EMC circuit formed by D1,C1, C1, L1, NTC is 2.5 � negative temperaturecoefficient resistor to provide inrush protection,FR1 provides short-circuit protection when largeAC input current occurs.
2. NCP1360 Control Circuit:R8 and R9 consists of voltage simple network toset output voltage, C12 is a delayed capacitor todelay switching on to valley.R12 and R13 is a current sensing resistor to decidehow much current can be set, R10 and CS pinparasitic capacitor consists of a filter to filtercurrent spike. R19, C11 and C9 consist of a type IIcompensation network to provide voltage feedback
control loop compensation.R5 and R11 is start-up resistor, two 7.5 M� areused in series to reduce power loss, R4, D6 and C4consist of VCC supply circuit, R4 can adjust VCCvoltage and also prevent D6 from an inrushcurrent. An RCD−R clamp consisting of D5, R3,R6, and C7 limits drain voltage spikes caused byleakage inductance, resistor R6 has a relativelylarge value to prevent any excessive ringing on thedrain voltage waveform and R3 can limit thereverse recovery current through D5.
3. Output Rectification and Filter:The transformer (T1) secondary is rectified by D2,a Schottky barrier-type diode (chosen for higherefficiency), and filtered by C3, C5 and C8. In thisapplication, C3 and C5 have sufficiently low ESRcharacteristics to allow meeting the output voltageripple requirement without adding an LC postfilter. C6 and R7 are snubber network of D2 toeliminate excessive ringing on secondary voltagewaveform. R14 is a dummy load to prevent outputvoltage rising at no load.
Key Features• Primary Side Regulation (PSR) CC/CV Control
• Quasi-Resonant Current Mode Control with ValleySwitching
• Valley Lockout Avoids Audible Noise at ValleyJumping Operation
• Built in 4 ms Soft Start
• 110 kHz Maximum Clamp Frequency Operation
• Adjustable Voltage Control Loop Compensation
• 300 mV Cable Drop Compensation
• Wide Operation VCC Range (Up to 30 V)
• Cycle by Cycle Current Limit
• Support External 1500 �F Capacitive Load Start-up
• Built in VCC OVP (Typical 26 V)
• Built in Output UVP in CC Mode (3 V ±6.7%)
• Output OCP, SCP, OVP and Controller OTP Function
AX/KSH106M400T1Z5H1CK Rubycon/TEAPO 10 �F,400 V 10 mm (Die.) ×12.5 mm(Hight)
Size,10 × 12.5 mm
35 2 C3 C5 ElectrolyticSolid
Capacitor
PCH477M6R3S1AGE08K TEAPO 470 �F,6.3 V 6.3 mm (Die.)× 8mm (Hight)
Aluminum SolidCapacitor, size,6.3 × 8 mm
References[1] DON Semiconductor datasheet for NCP1360/5
CC/CV primary side PWM current mode controller.
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