S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 1 DMB DMB Production Production 8-layer PC Board, 2 Ball-Grid Array FPGA’s, 718 Components/Board 550 Production Boards
Jan 30, 2016
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 1
DMBDMB Production Production DMBDMB Production Production
8-layer PC Board, 2 Ball-Grid Array FPGA’s, 718 Components/Board
550 Production Boards
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 2
DMBDMB Production Boards Production BoardsDMBDMB Production Boards Production Boards
- 411/550 boards delivered/tested- 70 boards required repair
Board are being boxed and storeduntil needed at Ohio State
Jan Feb M ar Apr M ay Jun Jul Aug Sep Oct Nov Dec
DMB 350 450 550TMB-RAT 10* 30 150 270 390 510 540CCB 10 20 40 60 70MPC 10 20 40 60 70LVRB 10 20 40 60 70Backplane 4* 10 20 40 60 70Controller 10 20 40 60 70
2005
Production Schedule
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 3
New Crate Controller DevelopmentNew Crate Controller DevelopmentNew Crate Controller DevelopmentNew Crate Controller Development
A VMEbus Controller with Gigabit Ethernet – A custom board designed and
developed at OSU– Based on XILINX Virtex-II Pro– Custom firmware.– Optical transceiver (for Gbit Ethernet) – Communicates with stand-alone PC
(in USC55) via Gigabit Ethernet
It’s Alive !
Measured: Continuous Read/WriteVME Transfers at 120 Mbit/s
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 4
Dest Addr | SRC Addr | PktLen PktType | NVME Cntrl | VME Addr | Data Cntrl | VME Addr Cntrl | VME Delay
Gigabit-VME Ethernet ProtocolGigabit-VME Ethernet ProtocolGigabit-VME Ethernet ProtocolGigabit-VME Ethernet Protocol
Utilize Commercial Software (Drivers)
Ethernet Raw Socket Layer (requires setuid();)
Packet to Controller:
Ethernet Header Private Protocol Header VME Write 1 VME Read 2 VME Delay 3 VME Write 4
14 bytes 4 bytes 8 bytes 6 bytes 4 bytes 8 bytes
Packet from Controller:
Ethernet Header Private Rcv. Header Data from VME …
Dest Addr | SRC Addr | PktLen PktType | RSVD | NWrds Data Data Data Data Data DataData Data Data Data
14 bytes 6 bytes 2 bytes 2 bytes …
Cntrl | VME Addr | Data
Note: Jumbo Packet Support 9000 bytes
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 5
Controller Production ScheduleController Production ScheduleController Production ScheduleController Production Schedule
New Controller has Run in DDU/DCC Crate for 1 Month - Very Stable, No Bus Hangs or Resets Needed Yet! - 2nd prototype/preproduction board TBD (some changed components, layout fixes, and form factor change) - Radiation Tests Need to be PerformedFirmware Additions Needed: - Storage of MAC Address in Flash RAM - Controller Handshake for Overflow Protection - JTAG interface for reprogramming PROM via ethernet
Jan Feb M ar Apr M ay Jun Jul Aug Sep Oct Nov Dec
DMB 350 450 550TMB-RAT 10* 30 150 270 390 510 540CCB 10 20 40 60 70MPC 10 20 40 60 70LVRB 10 20 40 60 70Backplane 4* 10 20 40 60 70Controller 10 20 40 60 70
2005
Production Schedule
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 6
DDU PrototypeDDU PrototypeDDU PrototypeDDU Prototype• Functions
– Merge data from 13 DMBs– Perform error checking
and status monitoring (CRC, word count,
L1 number, BXN, overflow, link status)
– Communicates w/FMM
• Large Buffer Capacity– 2.5 MB buffer – Average DDU data volume
estimated to be 0.4kB per L1A at LHC (@1034 lumi)
– Buffer can hold over 6000 events
• TTC signals from DCC • Slow control via VME
SLINK Mezz Board
Optical Fiber
Input (15)
GbE To Local
DAQ
Input FIFOs
Input FPGA
GbE FIFO
Main FPGA
VME FPGA
FMM output
port
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 7
DCC PrototypeDCC PrototypeDCC PrototypeDCC Prototype
• Data Concentration– Merge data from 9 DDUs– send merged data to
central DAQ via 1 or 2 SLINKs
– Has two optional GbE spy data path
• Fast Control– Receive TTC fiber
signals using TTCrx, – Fanout L1A, LHC_clock
and other TTC signals to DDUs
– Has optional FMM interfaceJ1 backplane
SLINK
TTCrx
SLINK
ControlFPGA
Output FIFOs
Input FIFOs
Input FPGAs
VME
DDU data
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 8
DDU/DCC PrototypeDDU/DCC PrototypeDDU/DCC PrototypeDDU/DCC Prototype
DDU/DCC TestBeam 2004 - very successful, no problem for > 10x LHC rate
Both DDU/DCC Passed ESR Nov. 2004
DDR FIFO bit errors – bad chip used on DDU/DCC/Controller (72T40/20 family)
FIFOLFSRparity
Q[39:20]
Q[19:0]
Din[19:0]
D[19:0]
D[39:20]
COMP
Errorreport
FIFOWrite/read
Qout[19:0]
Qout[39:20] • IDT72T40118, 40-bit 0.5MByte, DDR FIFO bit errors, esp. bit 21
• Detailed test on test board
• Error shown on DDU and VME_controller (DDR FIFO)
• Still working with IDT
• Replacement:
TI SN74V3690
IDT 72V36110
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005 9
DDU/DCC ProductionDDU/DCC ProductionDDU/DCC ProductionDDU/DCC Production
Relayout Both DDU and DCC
Jan Feb M ar Apr M ay Jun Jul Aug Sep Oct Nov Dec
DDU 10* 30 50DCC 2* 6 10Backplane 1 4 5Controller 1 4 5
2005
( * : pre-production boards)Production Schedule
optionalbaseline
CONTROLLER
DDU
DCC
DDU
DDU
DDU
DDU
DDU
DDU
DCC
DDU
DDU
Detector Dependent Unit (DDU)9/crate, 50 will be built
Data Concentration Card (DCC)1 or 2/crate, 10 will be built