Dma

Direct memory access

Direct memory access (DMA) is a process in which an external device takesover the control of system bus from the CPU.

DMA is for high-speed data transfer from/to mass storage peripherals, e.g. harddisk drive, magnetic tape, CD-ROM, and sometimes video controllers.

For example, a hard disk may boasts a transfer rate of 5 M bytes per second, i.e.1 byte transmission every 200 ns. To make such data transfer via the CPU isboth undesirable and unnecessary.

The basic idea of DMA is to transfer blocks of data directly between memory andperipherals. The data don’t go through the microprocessor but the data bus isoccupied.

“Normal” transfer of one data byte takes up to 29 clock cycles. The DMA transferrequires only 5 clock cycles.

Nowadays, DMA can transfer data as fast as 60 M byte per second. The transferrate is limited by the speed of memory and peripheral devices.

Basic process of DMA

For 8088 in maximum mode:The RQ/GT1 and RQ/GT0 pins are used to issue DMA request and receiveacknowledge signals.Sequence of events of a typical DMA process1) Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0

(RQ/GT0 has higher priority)2) 8088 completes its current bus cycle and enters into a HOLD state3) 8088 grants the right of bus control by asserting a grant signal via the same

pin as the request signal.4) DMA operation starts5) Upon completion of the DMA operation, the peripheral asserts the

request/grant pin again to relinquish bus control.

For 8088 in minimum mode:The HOLD and HLDA pins are used instead to receive and acknowledge thehold request respectively.Normally the CPU has full control of the system bus. In a DMA operation, theperipheral takes over bus control temporarily.

DMA controller

A DMA controller interfaces with several peripherals that may request DMA.

The controller decides the priority of simultaneous DMA requests communicates with the peripheral and the CPU, and provides memory addresses for data transfer.

DMA controller commonly used with 8088 is the 8237 programmable device.

The 8237 is in fact a special-purpose microprocessor.Normally it appears as part of the system controller chip-sets.

The 8237 is a 4-channel device. Each channel is dedicated to a specific peripheral device and capable of addressing 64 K bytes section of memory.

HRQHLDA

DRQDACK PI/E

Controler DMA Dispozitiv Periferic

Memoria

principala

HOLD

U C P MA

MD

MC

HOLDA

Magistrala de adrese

Magistrala de date

Magistrala de comenzi

A0-A15 BUSEN

HOLD

HOLDA

CLOCKRESETMEMR#

MEMW#IOR#

IOW#

D0-D7

CLKRESETMEMR# MEMW# IOR# IOW#

HRQ

HLDA

AEN A0-A3 A4-A7 CS/ ADSTB

DB0-DB7

DREQ0-3

DACK0-3CPU

I8237A

OE#

STB

8 BIT

LATCH

Address buss A0-A15

Sistem data buss

Control buss

ADSTB

AENEOP#

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HRQ

HLDA

A0

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CLK

READY

RESET

A7

DB0

DB7I8237A

11

12

369

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3029282726232221

3412

6

13

10

7

25241415

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DIRI8286

LDAT0-7

12 13 14 15 1617 18 19

18 7 6 5 4 3 2

9

11

PCLKCSDMA#

3233343537383940

1213141516171819

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I8286

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8765

I8286

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373

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D7

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Q7

CK

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DMAHLDADMARDY

RESET

ADR8-ADR15

ADR16-ADR19

ADR0-ADR7

SP#/EN#

DRQ0-3

911

MEMR#MEMW#

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A0

B0

A7

B7

3233

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A0 CS#

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CLK

READYRESET

A7

DB0

DB7

I8237A

3233

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AEN

EOP#

DRQ0DRQ1DRQ2DRQ3

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A0 CS#

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CLK

READYRESET

A7

DB0

DB7

I8237A

XA1-XA7

XD0-XD7

XA8-XA1574LS573

C

OE#

MASTER#

XA9-XA1674LS573

C

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T/C

XA8

HRQHLDA

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CLK

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