Digital-to-Analog ConverterAnalog Converter

Digital to Analog ConverterDigital-to-Analog Converter

General ConsiderationsD-to-A

111...111111...110

REF'm' digitsD to A

conversionEx) for 3bit DAC,

000->0 001 >(1/8)REF

000...000000...001

steps001->(1/8)REF

110->(6/8)REF

m2

000 0000 111->(7/8)REF

m

DREFA2

=

Formats of Digital InputDecimal 0 1 2 3

Thermometer

Binary 00 01 10 11

0 0 0 10 0 1 10 1 1 1

1-of-n

0 1 1 10 0 0 1 0 0 1 00 1 0 0o 0 1 0 01 0 0 0

Metrics-1

Analog output

INL

DNL + 1LSB

θ gain error = ideal slope -tan θ

Digital input

Offset

Integral nonlinearity (INL) : maximum deviation of transfer characteristic from straight line

Differential nonlinearity (DNL) : maximum deviation of step size from 1 LSBDifferential nonlinearity (DNL) : maximum deviation of step size from 1 LSB

Gain error : deviation of the slope of line from its ideal value (usually unity)

Off i l i f h i h li h di i l i i 0Offset : vertical intercept of the straight line when digital input is 0

Metrics-2Cl k

Digital Input

Clock

glitch impulse areaerror less than 1 LSB

p

Analog

settling time

gOutput

S f f ( S )

latency

Settling time : time required for output to settle within a specified error (< 1LSB)

Glitch impulse area : maximum glitch area after input changes

Latency : delay from the time digital input changes to the time analog output has settled

Signal-to-’noise+distortion’ ratio (SNDR) : ratio of signal power to noise and harmonic power t V t h i t i di it l i idat Vout when input is a digital sinusoid

Voltage DivisionN resistors for 'm' bit resolution

VREF

R

VREF

R/2

N resistors for m bit resolution

R

R1−NV

V

R1−NV

2−NV

R

2−NV

2V R2V

1V

mN 2= to switchesfor analog output

R0V

1V R0V

1

R/2

balanced conversion

Resistor Mismatch (Example Analysis : Linear Gradient)VREF VREF

1−NVR+(N 2)∆R

R+(N-1)∆R1−NV2−NV

∆R<0

2−NV

2V

R+(N-2)∆R

V

∆R>0

∆R=0

R+∆R

RV

2

1V0V

2V1V

Index0 1 N 2 N 1

j

RjjjRRkR ∆−

+∆+∑−

2)1()(

1

0V

- Max INL : center point- Max DNL : at point 1 and N-1

(max. deviation in slope at 1, and N-1)

0 1 N-2 N-1

REFREFN

k

kj V

RNNNRV

RkRV

∆−

+=

∆+=

∑−

=

=

2)1(

2

)(1

0

0(max. deviation in slope at 1, and N 1)

)( ∆N

VRRNj

NVVVDNL REFREF

jjj∆−

−≈−−= + )2

1(1

REFjREFj VNR

RNR

jNjVVNjINL

22

1)( ∆

∆−

+

−=−= 1−= NDNLDNL

REFREF V

RR

NV

RRN

2)

21( ∆

≈∆−

≈

Assuming R >> (N-1)∆R/2

)8/(2/ RRNVINLINL REFN ∆==RNR 22

Assuming R >> (N-1)∆R/2, large N

Random Resistor Mismatchrandom variation

Assuming Gaussian PDF for resistance

random variationVREF VREF

REFVRR

NINL ∆

=41

g

increase N

if ∆R/R is constant, INL decreases as N increases.

linear gradientVREF VREF

Recall from linear gradient case)8/( RRNVINL REF ∆=

increase N

if ∆R/R is constant, INL increases proportionally as N increases.

Why ?

Current-Steering ArraySegmented Current-Steering Array Binary Current-Steering Array

D1 D2 DN

Iout

D1 D2 Dm

IoutSegmented Current Steering Array Binary Current Steering Array

D1 D2 DN D1 D2 Dm

Im 12 −I2II I I

D : thermometer code D : binary codemonotonocity guaranteed

R R

Circuit Implementation

D1D1

RVout+

R

D2D2 D3D3

Vout-

D1D1 D2D2 D3D3

VB1 VB1 VB1

VB2 VB2 VB2

Current Switching

Iout

D : full swingM2 : fully off/on switchLarge swing on X => slow response

D

VB IREFM1

M2

X

21 RonroRout +=

Iout Iout D : small swing

DD M3M2

gM2, M3 : differential switching Small swing on X => fast response

122 rorogmRout ⋅⋅=X

VB IREFM1

21 RonroRout +=If M2,M3 operate in linear region,

Current Manipulation

I I I4I I2I

Uniform Division Binary Weighted Division

I I I

VBVB

IREFIREF

Replication

IREF IREF IREF IREF

Replication

Current-to-Voltage ConversionTransimpedance

R

RResistor amplifier

Current Steering

IoutVout

Current Steering

Iout Vout-

+

Current-Steering Array

Current-Steering Array

Iout varies by finite output resistance Iout flows from virtual groundIout varies by finite output resistance of current source

Output voltage swing limitedPoor linearityF li d

Iout flows from virtual groundGood linearitySlow operationHigh resolution

Fast settling speed

ID

1/(out resistance)( )

VDS

Current Source Mismatch2)(1

THGSOXD VVWCI −= µ )(2 THGSOXD VV

LCI µ

22 )(21)()(

21

THGSOXTHGSOXD VVLWCVV

LWCI −

∆+−∆=∆ µµ

TR Sizing

THTHGSOXTHGSOX VVVLWCVV

LLWC ∆−−−

∆− ))(2(

21)(

21 2

2 µµ

VLWCI ∆∆∆∆∆ 2)( : Larger W & L helps matchingTHGS

TH

OX

OX

D

D

VVV

LL

WW

CC

II

−∆

−∆

−∆

+∆

=∆ 2)(

µµ

I1 I2I2 I1

I3slope=1/Rs

I4I4I

VDD

I

Source Degeneration

I3

VBdesired current Rs Rscurrent level for I1

Matching improved by source degeneration

THV∆VB

Rs shoud be comparable with 1/gm.Better to use with BJT

Current-Steering DAC (OP amp Implementation)Switch at VREF

VREF Switch at VREF

I1=VREF/R

RoR 2R R12 −n

1/2(I1) (I1) 12/1 −n VREFDIDIo == )2(1

X MSB LSB

I1 VREF/R

VoutA0-

+

/ ( ) ( )2/1

Io RoIoVoutR

IIo nn

⋅−=

− )(2

12 1

large swing on X

VREF Switch at Ground

I1=VREF/R

RoR 2R R12 −n

1/2(I1) (I1) 12/1 −n

VoutA0-

+Io

+

Faster solution

Current-Steering DAC (R-2R Ladder)

No big Rs !VREF

I1

No big Rs !

2RR R R R2I1

2n1n

I1 22 −nI1 12 −n

Ro2R 2R 2R2R

2I1 I1 I1 22 −nI1 12 −n

VoutA0-

+Io

Charge Division

CNDN

CN CN

Cj+1Dj+1

Cj+1 Cj+1

Cj VoutDj

Cj Vout Cj VoutVREF

C1D1

C1 C1

VREF

VREF

Discharge EvaluationDischarge Evaluation

If C1=C2=..=CN=CVout = (j/N)VREFVout (j/N)VREFsame as resistor divider

Capacitor ArraysDm

D

CDN

D

Cm 12 −

Dm-1C

DN-1Cm 22 −

CD1

Vout

CD1

-+ Vout

-+

VREF VREF

Binary weighted capacitor array Segmented capacitor arrayPoor matching between

small cap. and big cap.Thermometer decoder needed

Capacitor Mismatch

In case of random variations, INL improves as the number of capacitors increases.

OX

OX

tWLC ε

=OX

OX

tt

LL

WW

CC ∆

−∆

+∆

=∆

In case of random variations, INL improves as the number of capacitors increases.- Integration averages out random errors. => similar to resistor divider

Common Centroid Layout

1 22

34 45

56

6

1 24

3

5

44

35

4

5 5 5 5

5

5dummy cap.

1

1

1

2 2

3

3

3

44 5

5 6

6

4

3

4 3

4

5

5

55 5

5 4

2 5

5

binary array segmented array

Less sensitive to linear gradient of process variation

Switch Junction Capacitor (Cj)

Capacitor Non-idealities

mj VCoC

)/1( Φ=

CojV

Cozero-bias capacitancereverse bias voltage across junction

Switch Junction Capacitor (Cj)

mj

j V )/1( Φ+j

Φm

jV

g jbuilt-in potentialempirical parameter 0.3~0.5

Top Plate Parasitic Cap. (CP)

DN

jCCN

CN 1DN-1

REFP

VCNC

jCVout+

=

VjC=CN-1

C VoutD1

REFP

V

NCCNC )1( +

=

P VCj )1( −≈ CNCif >>

VREF

C1 VoutCP

REFVNCN

)1( −≈ PCNCif >>

VREF

While junction cap. of the switch introduces nonlinearity, top plate parasitic causes gain error.

VREF VREF VREF3

D3D2D1

Resistor Ladder DACs

R

R/2

D1D2

D13

R

RD2

D1D3

D1

ode

er

R

R

D1

D1 VoutD2

Vout

mom

eter

co

Vout

-8 d

ecod

e

R

RD3

D1

D1

D2

ther

m

3-to

R

R/2

D1

D2D1

R/2

1-of-n code 1-of-n code

Binary input Thermometer code input Using a decoder

Three switches in series => slow settling due to RC

Single Switch to VoutLarge cap. on Vout

Single Switch to VoutLarge cap. on VoutDecoder needed

Resistor Ladder DAC with Switched Subdivider

Architecture Implementation

Number of resistors reduced : 2/222 mm ⋅>−

Long initial settling time when subdivider moves to a new sector.Current bypass to the second stage should be negligible.

u be o es s o s educed

Nonlinearity by Switch Resistance

increment by 1 LSB

21 uu RRAssume <<

DNL error )(on VVR≈

Monotonocity still guaranteed

DNL error )(22 1

2nn

uk

on

VVRR

−+

≈ +

Switched Subdivider with Analog Buffers

-+

-+

Effect of Ron of first stage is eliminated.Two amps should be well matched. (equal offset voltage)

Intermeshed Resistor Ladder DACOne-Level Intermesh Two-Level IntermeshOne Level Intermesh(one switch to Vout)

Two Level Intermesh(two switches to Vout, Cj reduced to 1/ )k2

switches turn onk2

t it hdecoder 1

to switchesdecoder 2

k bitj bit

decoder

bit

m bits

k bitsj bitsm bits

Current-Steering DAC with R-2R Ladder

Using BJT current source with emitter degeneration

aII =0

equivalent circuit

g

aa IIII 201 =+=

Area for resistors reduced

aa IIII 201 +

equivalent circuit

aa IIIII 4012 =++=

R-2R Ladder with Current Sources

Norton equivalent circuit

Norton equivalent circuit

Area for both transistors and resistors are reduced.

RIIIVout )42

( 123 ++=

Glitch Impulse in R-2R Ladder DAC

Deglitching (sample and hold) needed

Segmented Current-Steering DAC

- No glitch problem when code changes by 1M t- Monotonous

- Large number of devices- Decoder needed

Matrix Implementation of SegmentationD3 D2 D1

Column Decoder

D3 D2 D11 0 1

thermometer code

D40

0 0 1 1 1 1 1

0 0 0 0 0 0 0 0r

D41

0

0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 Efficient routing

Serious coupling of control signal to Vout

w D

ecod

er

D51 0

0

0 0 1 1 1 1 1 1

0 0 0 0 0 0 0 0

control signal to Vout

Large cap. on Vout

Row

D6 1

1

1 1 1 1 1 1 1 1

0 0 1 1 1 1 1 1

01

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

Vout

local decoder

Partially Segmented Current-Steering DAC(1)Implementation of higher resolutionp g

4 LSBs6 MSB

M t it t t d

4 LSBs6 MSBs

Assumption : Since current sources in 4-bit binary Monotonocity not guaranteedA

p yarray are usually implemented by replication of unit current source, binary array itself is monotonous.

If one of I1 to I63 happens to be less than (15/16)Io

D

Partially Segmented Current-Steering DAC(2)

- Monotonous- Weak in low voltage operation : stacking of circuits

Higher Resolution with Reduced C Ratio (1)DAC with R and C Arrays

VREFD12

VREF

DAC with R and C Arrays

R1

D12

D11

128Creset switch

R2

R3

D11

V t-

64C Cf

R15C

D5

Vout+

R16 C

4 LSB bits 8 MSB bits

Both R and C used for reduction of maximum capacitor ratio.Area reduced

Higher Resolution with Reduced C Ratio (2)DAC with R and C Arrays

VREFD8

DAC with R and C Arrays

R1

R2

D8

D7

128Creset switch

R2

R3

D7

V t-

64C Cf

R15 CD1

Vout+

R16 C

4 MSB bits 8 LSB bits

Higher Resolution with Reduced C Ratio (3)DAC with C Scaling

D12128C reset

switch

VREF

DAC with C Scaling

-

64C CfD11

8 MSB bits

CVout

+

D51 0C equivalent

8CD4

Cx=1.067C1.0C equivalent

16C equivalent

4CD3

4 LSB bits Series of 1.067C and 16C = 1.0C

CD1

C

Higher Resolution with Reduced C Ratio (4)DAC with C Scaling

D12128C reset

switch

VREF

DAC with C Scaling

-

64C CfD11

8 MSB bits

CVout

+

D5(15/16)C equivalent

8CD4

1C(15/16)C equivalent: one LSB step

4CD3

4 LSB bitsREF REF

CD1

stepsm2 -1 stepsm2

0 0

Serial DAC with Two Capacitors

VREF

D*Sample

LSB first inN cycles for N-bit conversionD Sample

Vout

Eval

y

C CD*Sample ResetVout(k) = 0.5[Vout(k-1) + VREF*D(k)]

VREFVout(1101)Vout(1101)

TimeS E S E S E S EReset

cycle 1 cycle 2 cycle 3 cycle 4D=1 D=0 D=1 D=1

LSB MSB