Digital System Design using VHDL.pdf

Digital System Design

using VHDL on Xilinx

FPGA kit

Outline

Evolution of PLDs

PLDs Overview

VHDL Basics

Study of Spartan-3e kit

Hands-on FPGA kit

Combinational Design

Sequential Design

Finite State Machines

7/3/2013AICTE Approved STTP Program on VLSI and Embedded Systems

Discrete devices ~1940s-50s

Discrete logic gates ~1950s-60s

Integrated circuits (IC) eg. TTL series 74LSxx, ~1960s-... 100s of different devices

simple programmable logic devices ~1970s-...

2 levels of logic (SPLD)

mask-programmable gate arrays ~1970s-...

used to implement application-specific integrated circuits (ASICs)

large programmable logic devices ~1980s-...

multiple SPLDs on a chip (CPLD)

programmable array of logic cells + programmable interconnect (FPGA)

trend toward higher levels

of integration allows to

implement larger designs

with fewer components


Evolution of PLDs

PLD OverviewTwo basic ways of programmability

mask-programmable PLDs (MPLDs)

programmed by the manufacturer (like MPGA)

field-programmable PLDs (FPLDs)

completely prefabricated, tested, and packaged devices programmed

by the user shorter time-to-market

there exist also re-programmable variants

from now on: PLD means field-programmable PLD !

PLD types PLD

ROM PLA PAL

SPLD CPLD FPGA


Our Concern

Pre-fabricated device with

array of transistors or simple logic gates / sequential elements

wiring channels, but no pre-fabricated wires

I/O blocks

Customization through wiring at the manufacturer

masks for wires and viasmask-programmable gate array

Design

use library of elements

tools for automatic mapping to the device (place and route)

combinational and sequential logic

I/O blocks

wiring channels

Mask Programmable Gate Array

ROM (Read-only Memory)

A ROM can be viewed as AND-OR programmable array

n inputs, 2n not-programmable product terms (all minterms) m outputs, each with all 2n product terms

memory with n address lines and m outputs

(2n x m) bit memory

ROM when used for computation can compute

Can compute any set of m logic functions of the n inputs

Useful only for complex functions with sufficiently small n

e.g

code conversions

complex mathematical functions


PLA (Programmable Logic Array)

Programmable AND plane followed by programmable OR

plane

more compact and flexible than ROM because

AND gates can compute any product term (not just minterms)

AND plane does not compute all 2n product terms

PLAs were the first devices built for programmable logic

implementation introduced ~1970s by Philips

PLAs were commercially not successful due to the two

levels programmable logic manufacturing was expensive

devices had poor speed

PAL (Programmable Array Logic)

smaller and faster than PLA

Programmable AND plane followed by fixed OR plane

PALs are commercially very

successful introduced by MMI

(AMD) that exist in different number

of inputs and outputs can be

registered to implement sequential

circuits

example


SPLDs (simple PLDs)

are AND-OR programmable arrays with

ROM: fixed AND plane, programmable OR plane

PLA: programmable AND plane, programmable OR plane

PAL: programmable AND plane, fixed OR plane

SPLDs are used to implement designs with up to ~200 gates

for larger designs (more complex functions, more inputs)

AND planes grow too large

multi-level logic might be more efficient than 2-level logic

Two approaches for larger PLDs CPLD: multiple SPLDs plus programmable interconnect

FPGA: programmable array of logic cells + programmable interconnect

combines concepts of "field-programmable" and "gate array"

Field-Programmable Gate Array


Simple PLDs


Complex Programmable Logic Devices(CPLD)

CPLDs consists of

a number of SPLD-like blocks(macro-cells)

I/O blocks

A more or less complex programmable interconnect between

the macro cells and the I/O blocks

Commercial CPLDs

introduced by Altera

Now it exists in different variants like Altera,

AMD,Lattice,Cypress,Xilinx,.

FPGAs consist of three components

array of programmable logic blocks with look-up tables (LUTs), registers,

multiplexers

programmable interconnect

I/O blocks around the perimeter

FPGA (Field-Programmable Gate Array)


The logic block configuration

is given by the contents of the LUT memory and the MUX control signal

4-LUT with 16 configuration bits

multiplexor with 1 configuration bit 7/3/2013AICTE Approved STTP Program on VLSI and Embedded Systems

FPGA A Simple Logic Block

VHDL Basics

ChipThis chip is a Black Box which is

reconfigurable.



VHDL Background

VHDL stands for VHSIC Hardware Description Language

Funded by US Dept. of Defense in 80s led to creation of VHDL

It was a first language standardized by IEEE through IEEE 1076

standards.

Used for both circuit synthesis and circuit simulation

Applications of VHDL are in PLDs CPLD,FPGA and ASIC


Design Flow

1. Start a design by writing a VHDL code which

is saved with an extension .vhd and name is

entity name.

2. This source code is to be synthesized .

3. The first step of synthesis is compilation where

a source code is converted to net list at RTL

i.e. in gate level.

4. Second step is optimization which is

performed on the gate-level net list for speed

and area.

5. This stage is for design can be simulated.

6. Finally a place and route (PAR) software will

generate the physical layout for PLD or build a

mask for ASIC.

VHDL structure

Library

List of all the libraries to be used in the design.

Entity

Specifies I/O pins of the circuit(Interface)

Architecture

Implementation, function

Note: VHDL is case insensitive


VHDL - Library

Include library

library IEEE;

Define the library package used

use IEEE.STD_LOGIC_1164.all;

Define the library file used

For example, STD_LOGIC_1164 defines 1 as logic high and 0

as logic low

output

Entity

Define inputs and outputs

Example:

Entity test is

Port( A,B,C,D: in std_logic;

E: out std_logic);

End test;

Inputs and Outputs

Chip

A

B

C

D

E

Architecture

Define functionality of the chip

X

Exercise: Implementing a simple NAND Gate

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NAND_1 is

Port ( X : in std_logic;

Y : in std_logic;

F : out std_logic);

end NAND_1;

architecture Behavioral of NAND_1 is

begin

F

Writing a testbench-- Stimulus process

signal_a : process

begin

a

Assignment1

Write a VHDL code to implement EXOR gate

Hint:

Data Types bit values: '0', '1' boolean values: TRUE, FALSE

integer values: -(231) to +(231 - 1)

std_logic values: 'U','X','1','0','Z','W','H','L','-'

U' = uninitialized'X' = unknown'W' = weak 'X

'Z' = floating'H'/'L' = weak '1'/'0'-' = don't care

Std_logic_vector (n downto 0); Std_logic_vector (0 upto n);


Use of Spartan 3E FPGA Kit


XC3S500E -5 FG 320 C


Study of Spartan 3e kitThe key features of the Spartan-3E Starter Kit board are:

Xilinx XC3S500E Spartan-3E FPGA

Up to 232 user-I/O pins

320-pin FBGA package

Over 10,000 logic cells

Xilinx 4 Mbit Platform Flash configuration PROM

Xilinx 64-macrocell XC2C64A CoolRunner CPLD

64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz

16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)

FPGA configuration storage

2-line, 16-character LCD screen

PS/2 mouse or keyboard port

VGA display port

10/100 Ethernet PHY (requires Ethernet MAC in FPGA)

Two 9-pin RS-232 ports (DTE- and DCE-style)

On-board USB-based FPGA/CPLD download/debug interface

50 MHz clock oscillator

Four-output, SPI-based Digital-to-Analog Converter (DAC)


Study of Spartan 3e kit (contd)

Slide Switches and LEDs

Push Button and Rotary switch

Clock sources

Design Tool Flow

Standard Design flow has 3 major steps

Design Entry and Synthesis HDL Editor, XST, Simulator

Design Implementation Translate, Map, Place and Route(PAR)

Design Verification iMPACT Configuration Tool

Design Tool Flow(contd)


Exercise: Full adder Implementation

Write a VHDL code on Full adder by Algorithmic behavioral modeling

Write a VHDL code on Full adder by Dataflow

Write a VHDL code on Full adder by structural modeling


Behavioral Modelling Algorithmic

library IEEE;




entity fulladder_behv is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

s : out STD_LOGIC;

cout : out STD_LOGIC);

end fulladder_behv;

architecture Behavioral of fulladder_behv is

begin

s

Structural Modellingentity fulladder_struct is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

s : out STD_LOGIC;

cout : out STD_LOGIC);

end fulladder_struct;

architecture structural of fulladder_struct is

component ha

port (a,b:in std_logic;

s,c: out std_logic);

end component;

Two components

component or21

port (a,b: in std_logic;

y: out std_logic);

end component;

signal t1,t2,t3 : std_logic;

begin Association of all the components

h1: ha port map (a,b,t2,t1);

h2: ha port map (t2,cin,s,t3);

h3: or21 port map (t1,t3,cout);

end structural;


a

b

s

t2

t1

t3

cout

ha ha

cin

Writing a UCF

UCF is an association of software to hardware

Right Click the device and click New Souce and select Implementation

Constraints File from New source wizard and name the file.

Depending on the input and outputs define them with associated I/Os of the kit.

A simple example is given below for a two input gate.

NET "a" LOC = "L13" ;

NET "b" LOC = "L14" ;

NET "c" LOC = "F11" ;

Assignment 2

Implement a 2:1 MUX using all types of modeling techniques.

Hint:


Exercise: Implementation of ALU


Hint:

MSB bit decides to perform

arithmetic/logical

There are many solutions one such hint is given below

Sequential Design in VHDL The PROCESSES , FUNCTIONS and PROCEDURES are the

codes that executed sequentially

The PROCESS is a sequential section of the VHDL code.

It is characterized by the presence of IF,WAIT,CASE or LOOP and by a sensitivity list(except when the wait is used).

Syntax is:

[label:] PROCESS (sensitivity list)

[ VARIABLE name type[range] [:= initial_value;]]

begin

(sequential code)

END PROCESS[label];

Optional


Sequential Statements


Data manipulation within processes using sequential statements, so called

because they are executed in sequence.

Controlling actions within a model, hence they are often called control

structures. The control structures are if,case,when,while and for .

The syntax rule for an if statement is

if_statement

[ if_label : ]

if boolean_expression then

{ sequential_statement }

{ elsif boolean_expression then

{ sequential_statement } }

else

{ sequential_statement } ]

end if [ if_label ] ;

Sequential Statements(contd) If we have a model in which the behavior is to depend on the value

of a single expression,

we can use a case statement. The syntax rules are as follows:

case_statement

[ case_label : ]

case expression is

( when choices => { sequential_statement } )

{ }

end case [ case_label ] ;


Exercise: To design D F/F using asynchronous resetlibrary IEEE;




entity dff is

Port ( d : in STD_LOGIC;

clk : in STD_LOGIC;

rst : in STD_LOGIC;

q : out STD_LOGIC);

end dff;

architecture Behavioral of dff is

begin

process ( clk, rst )

begin

if (rst = '1') then

q

Exercise : To design a JK F/F


architecture Behavioral of jk_ff is

signal qtemp,qnottemp : std_logic := 0;

signal slow_clk : std_logic;

signal clk_divider : std_logic_vector (23 downto 0 ) := x"000000";

begin

clk_division : process(clk,clk_divider)

begin

if ( clk 'event and clk='1') then

clk_divider

JK Flip Flop(contd)

The clock is tied to 50MHz and the clock divider signal is 24 bits then the

slow clock will operate at less than 3Hz and the counter will increment

every 0.3 sec.

Mathematically,

fslow_clk = 50MHz / (22)

= 12.5MHz i.e. 80ns (This is much fast)

fslow_clk = 50MHz / (224)

= 2.98MHz i.e. 0.34s ( the changes can be

on the LEDs clearly)


Assignment3

Write a VHDL code to implement decade counter with asynchronous

reset and pause.


Spartan 3e Kit


FSM BackgroundThere are two basic ways to design clocked sequential circuits. These are using:

1. Mealy Machine

2. Moore Machine.

Mealy Machine

In a Mealy machine, the outputs are a function

of the present state and the value of the inputs.

Accordingly, the outputs may change

asynchronously in response to any change

in the inputs.


FSM Background(contd)Moore Machine

In a Moore machine the outputs depend only on the present state

A combinational logic block maps the inputs and the current state into the

necessary flip-flop inputs to store the appropriate next state just like Mealy

machine.

However, the outputs are computed by

a combinational logic block whose inputs

are only the flip-flops state outputs.

The outputs change synchronously

with the state transition triggered by

the active clock edge.


Sequence detector


LCD with counter

The project requires 3 state machines

1. Power on initialization sequence

2. Transmit commands and data to LCD

3. Start the power on initialization sequence, configure and write to the LCD


Digital System Design using VHDL.pdf

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