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08.408 Digital System Design Lab
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DIGITAL SYSTEM DESIGN LAB MANUAL
FOR
IV SEMESTER B.TECH (CSE)
VALIYA KOONAMBAYIKULATHAMMA COLLEGE
OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
DECEMBER, 2013
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List of Experiments
Expt.
No. Name of expt.
1 Study of digital IC and trainer kit
2 Realization of Logic Circuits using basic gates.
3 Half adder and full adder using gates and ICs
4 Flip-Flops using gates
5 Shift Registers
6 Multiplexers and Demultiplexers using gates and ICs
7 Realization of combinational circuits using
multiplexer/demultiplexer ICs
8 Asynchronous counters using flip flops and ICs
9 Synchronous counter
10 Ring counters and Johnson counter using flip flops and
ICs
11 Four-bit magnitude comparator
12 BCD to Decimal and BCD to 7-segment decoder & display
13 Astable and monostable multivibrators using ICs
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EXPT. NO. 1: STUDY OF TRAINER KIT AND DIGITAL ICS
AIM: a) To familiarize digital IC trainer kit
b) To familiarize basic logic gates and universal gate ICs, and
verify its truth table
COMPONENTS & EQUIPMENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. Multimeter 1 No.
5. ICs 7404, 7408, 7432, 7400, 7402, 7486 and 7410 (1 No.
each)
THEORY:
IC Trainer Kit
Digital IC Trainer has been designed with the idea of providing
basic facilities essential for
conducting simple experiments in the laboratory. Using these
facilities one can get oneself familiarized
with the various digital ICs and circuits. The system is
suitable for conducting experiments on TTL as
well as CMOS ICs.
Different sections in trainer kit are shown the figure 1 (left
page).
Figure. 1. Block diagram of trainer kit
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Picture. 1. Trainer kit (make: Kitek)
The features and functions of different sections in the kit
are:
1. Bread board: For connecting circuit diagram
2. Seven segment display: Four 7-segment displays can be used
with the experiments involving
displays. Each display has individual segment control.
3. Logic level indicator: 10-LEDs for indicating output. The
Logic high is indicating by LED
glowing, where the logic low is indicated by LED is not glowing.
Logic level output is given in
2mm banana socket provided on-board.
4. Potentiometer bank: Three pots of 1k, 10k and 100k variable
resistors.
5. Function generator: Sine, triangular and square wave output
with varying frequency up to
30kHz. Varying amplitude for sine and triangular waves and fixed
amplitude for square wave.
Also have different fixed frequency range 20Hz, 200Hz, 2 kHz, 20
kHz, 200 kHz and 1 MHz.
6. Logic level input: Ten push key switches to generate ten
logic inputs. When the switch is in
normal mode, logic level high will generated and when the switch
is in push mode, logic level
Low will be generated on the 2mm banana socket provided on the
kit. There are 10 Bi-Color
LEDs used to indicate the logic input generated by each Push Key
switch. The logic high is
indicated by the corresponding LED glowing as RED where the
Logic low is indicated by the
LED glowing as GREEN.
7. Manual pulser: Generates a manual clock, whenever the push
button switch is pressed and
released. The pulse can be tapped from 2mm terminals marked as
H-L-H Transition & L-H-L
Transition for ve edge and +ve edge clock pulse
respectively.
8. AC power supply: 15V-0-15V ac power supply
9. Fixed power supply: +12V, -12V and +5V dc power supply
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10. Varying power supply: -1.2V to -15V, +1.2V to +15V varying
dc power supply
11. Fixed clock: Generate clock pulse of 1Hz, 10Hz, 100Hz, 1kHz,
10kHz, 100kHz and 1MHz fixed
frequencies
12. Logic probe: Logics in the circuits can test by this probe.
Logic high by Red LED and logic low
by Green LED
Logic gates:
Logic gates process signals which represent true or false. Gates
have one or more inputs and one
output. Logic gates are available on special ICs (chips) which
usually contain several gates of the
same type. There are several families of logic ICs and they can
be split into two groups: TTL family
74xx series and CMOS family 40xx series. In the lab 74xx series
ICs are using.
Basic logic gate are:
1. NOT gate (inverter)
The output Y is true when the input A is NOT true, the output is
the inverse of the input: = . A
NOT gate is also called an inverter. The symbol, pinout diagram,
pin functions and truth table of the
NOT gate IC 7404 are shown in figure 2.
Figure. 2. NOT gate symbol, IC 7404 Pinout Diagram and Truth
Table
2. AND gate
The output Y is true if input A and B are both true: Q = A.B. An
AND gate can have two or more
inputs, its output is true if all inputs are true. The symbol,
pinout diagram, pin functions and truth
table of the 2-input AND gate IC 7408 are shown in figure 3.
Figure. 3. AND gate symbol, IC 7408 Pinout Diagram and Truth
Table
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3. OR gate
The output Y is true if either input A or input B is true, or
both of them are true: Y = A + B. An OR
gate can have two or more inputs, its output is true if at least
one input is true. The symbol, pinout
diagram, pin functions and truth table of the 2-input OR gate IC
7432 are shown in figure 4.
Figure. 4. OR gate symbol, IC 7432 Pinout Diagram and Truth
Table
4. NAND gate
This is an AND gate with the output inverted. The output of NAND
is true if any one input is not
true: = . . A NAND gate can have two or more inputs; its output
is true if NOT all inputs are
true. The symbol, pinout diagram, pin functions and truth table
of the 2-input NAND gate IC 7400 are
shown in figure 5.
Figure. 5. NAND gate symbol, IC 7400 Pinout Diagram and Truth
Table
The symbol, pinout diagram, pin functions and truth table of the
3-input NAND gate IC 7410 are
shown in figure 6.
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Figure. 6. Three input NAND gate symbol, IC 7410 Pinout Diagram
and Truth Table
5. NOR gate
This is an OR gate with the output inverted. The output Y is
true inputs A and B are false:
= + . A NOR gate can have two or more inputs, its output is true
if no inputs are true. The
symbol, pinout diagram, pin functions and truth table of the
2-input NOR gate IC 7400 are shown in
figure 7.
Figure. 7. NOR gate symbol, IC 7402 Pinout Diagram and Truth
Table
6. X-OR (EXclusive-OR) gate
The output Y is true if either input A is true OR input B is
true, but not when both of them are true:
= . This is like an OR gate but excluding both inputs being
true. The output is true if
inputs A and B are different. X-OR gates can only have 2 inputs.
The symbol, pinout diagram, pin
functions and truth table of the 2-input X-OR gate IC 7486 are
shown in figure 8.
Figure. 8. XOR gate symbol, IC 7486 Pinout Diagram and Truth
Table
PROCEDURE:
1. Place the IC on trainer kit.
2. Wire the circuit diagram
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of
LEDs.
RESULT:
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EXPT. NO. 2: REALIZATION OF LOGIC CIRCUITS USING BASIC GATES
AIM:
a) To realize basic gates using universal gates.
b) To verify Demorgans theorem.
c) To verify a SOP & POS expression using universal
gates.
COMPONENTS & EQUIPMENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. Multimeter
5. ICs
a) 7400 - 2 Nos.
b) 7402 2 Nos.
THEORY:
The universal property of NAND and NOR gates:
NAND and NOR gates is said to be universal gates because any
digital circuit can be
implemented using only one of these gates. Digital circuits are
frequently constructed with only NAND or
NOR gates; because these gates are easier to fabricate with
electronic components. Because of the
importance of NAND and NOR in the design of digital circuits,
rules and procedures have been
developed for the conversion from Boolean functions in terms of
AND, OR and NOT into equivalent
NAND or NOR logic diagrams .
1) Implementing inverter using NAND gate:
If all NAND input pins connect to the input signal X gives an
output . One NAND input pin is
connected to the input signal x while all other input pins are
connected to logic 1, the output will be . ie,
. = . The circuit of inverter using NAND is shown in figure
1.
Figure. 1. Inverter using NAND and truth table
2) Implementing AND using NAND gates:
An AND gate can be replaced by NAND gates as shown in the figure
2. The AND is replaced by
a NAND gate with its output complemented by a NAND gate
inverter. ie, . = .
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Figure. 2. AND using NAND and truth table
3) Implementing OR using NAND gates:
An OR gate can be replaced by NAND gates as shown in the figure
3. The OR gate is replaced by
a NAND gate with all its inputs complemented by NAND gate
inverters. ie . = + = + (By
DeMorgans law)
Figure. 3. OR using NAND and truth table
4) Implementing NOR using NAND gate:
A NOR gate can be replaced by NAND gates as shown in the figure
4. The NOR gate is replaced
by a NAND gate with all its inputs complemented by NAND gate
inverters and complementing its output
by NAND inverter. ie, . = . = + (By DeMorgans law)
Figure. 4. NOR using NAND and truth table
5) Implementing XOR using NAND gate:
An XOR gate can be replaced by NAND gates as shown in the figure
5. We know, =
= + = + + + = + + = +
= + = + = ( ) . ( ) (By DeMorgans law)
This can be implemented by four NAND gates.
Figure. 5. XOR using minimum number NAND gates and truth
table
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6) Implementing inverter using NOR gate:
If all NOR input pins connect to the input signal X gives an
output . One NOR input pin is
connected to the input signal x while all other input pins are
connected to logic 0, the output will be . ie,
+ = . The circuit of inverter using NOR is shown in figure
6.
Figure. 6. Inverter using NOR and truth table
7) Implementing AND using NOR gate:
An AND gate can be replaced by NOR gates as shown in the figure
7. The AND gate is replaced
by a NOR gate with all its inputs complemented by NOR gate
inverters. ie + = (by DeMorgans
law)
Figure. 7. AND using NOR and truth table
8) Implementing OR using NOR gate:
An OR gate can be replaced by NOR gates as shown in the figure
8. The OR is replaced by a
NOR gate with its output complemented by a NOR gate inverter.
ie, + = +
Figure. 8. OR using NOR and truth table
DeMorgans theorem:
It is used to simplify boolean equations. The theorems are:
1. + = .
2. = +
The circuit diagram to prove these theorems are shown in figure
9 and figure 10.
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Figure. 9. Circuit for DeMorgans Theorem 1 and truth table.
Figure. 10. Circuit for DeMorgans Theorem 2 and truth table.
Sum of Product (SOP) expression:
Each product term in the SOP expression is called minterm. SOP
expression can be economically
realized by universal NAND gates. Consider a two variable SOP
expression, = + . By
DeMorgans theorem, = + = .
. This expression can be economically implemented by 5
NAND gates as shown in figure 11.
Figure. 11. SOP implementation using NAND and truth table.
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Product of Sum (POS) expression:
Each sum term in the POS expression is called maxterm. POS
expression can be economically
realized by universal NOR gates. Consider a two variable POS
expression, = + . ( + ). By
DeMorgans theorem, = + . ( + ) = ( + ) + ( + )
. This expression can be economically
implemented by 5 NOR gates as shown in figure 12.
PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULTS:
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EXPT. NO. 3: ARITHMETIC CIRCUITS USING GATES AND ICs
AIM:
a) To design and setup the half adder using basic gates and
universal gates.
b) To design and setup full adder using basic gates and
universal gates.
c) To design and setup 4-bit adder/subtractor using IC-7483
d) To design and setup single digit BCD adder using IC-7483
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. Multimeter
5. ICs
a) 7400 3 Nos.
b) 7408 1 No.
c) 7432 1 N0.
d) 7486 2 Nos.
e) 7483 2 Nos.
THEORY:
Half-Adder:
A combinational logic circuit that performs the addition of two
data bits A and B is called half-
adder. Addition will result in two output bits; one of which is
the sum bit S, and the other is the carry bit
C. The Boolean functions describing the half adder are:
=
= .
The symbol, truth table, K-Maps and circuit diagrams for
half-adder is shown in figure 1.
Figure. 1. Half-adder symbol, truth table, K-Maps and circuit
diagrams.
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Full-Adder:
The half-adder does not take the carry bit from its previous
stage into account. This carry bit from
its previous stage is called carry-in bit. A combinational logic
circuit that adds two data bits A and B, and
a carry-in bit Cin is called a full-adder. Addition in this
adder will result in two output bits; one of which is
the sum S, and the other is the carry out Cout. The Boolean
functions describing for full-adder are:
=
= + +
or
= ( ) +
The second expression for Cout can be realized by minimum number
of gates. The Cout is high only either
Cin is high AND, A and B are different OR A AND B is high.
The symbol, truth table, K-Maps and circuit diagrams for
full-adder is shown in figure 2.
Figure. 2.a Symbol, truth table and K-Maps for full-adder
Figure. 2.b. Circuit diagram using basic gates for
full-adder
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Figure. 2.c. Circuit diagram using NAND gates for full-adder
Four-bit adder/subtractor using IC-7483:
IC-7483 is adder/subtractor IC used to perform arithmetic
operation. The pinout diagram and pin
functions of IC-7483 is shown in figure 3.a.
Figure. 3.a. Pinout diagram and pin functions of IC-7483
The adder/subtractor circuit using IC-7483 is shown in figure
3.b. Here XOR gates are used as
controlled buffer or inverter. Binary numbers can be subtract by
taking 2s complement of subtrahend. To
add 4-bit numbers A3A2A1A0 and B3B2B1B0, the XOR gates behaves
as buffer by making SUB as 0. To
subtract 4-bit numbers, the XOR gates behaves as inverter by
making SUB as 1 and B3B2B1B0 is
complemented and added with 1 by Cin.
Figure.3.b. 4-bit adder/subtractor using IC-7483
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Observed results:
Single digit BCD adder using IC-7483:
In BCD addition, if the sum exceeds 9, the result must be added
to the 6 to convert the result into
BCD number. For this two 7483 ICs are required: one for binary
addition and other for the addition of a
combinational circuit set up which generate 6, if output of
first adder is more than 9 and the sum from the
first. The truth table and K-Map to design BCD adder is shown in
figure 4.a. The X bit can be used to
generate 6 (0110)2. The circuit diagram is shown in figure
4.b.
Figure.4.a. Truth table and K-Map for single digit BCD adder
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Figure.4.b. Single digit BCD adder
Observed results:
PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULTS:
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EXPT. NO. 4: FLIP FLOPS USING GATES AND ICs
AIM:
To realize SR, D, T, JK and master-slave JK flip flops using
gates and ICs.
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. Multimeter
5. ICs
a) 7400 3 Nos.
b) 7410 2 Nos.
c) 7404 1 No.
d) 7476 1 No.
e) 7474 1 No.
THEORY:
Latches and flip-flops are the basic elements for storing
information. One latch or flip-flop can
store one bit of information. The main difference between
latches and flip-flops is that for latches, their
outputs are changed according to the input. But in flip-flops,
the output changes only either at the rising or
falling edge of the clock signal.
There are basically four main types of latches and flip-flops:
SR, D, T and JK. The major
differences in these flip-flop types are the number of inputs
they have and how they change state.
SR latch:
The symbol, circuit diagram and truth table with states of SR
latch with enable input E is shown
in figure 1.
Figure.1. Symbol, circuit diagram and truth table of SR latch
with enable input.
Here the output is disabling when enable input E is 0. The
output remains previous state which
depends on its S (Set) and R (Reset) inputs. The latch is
enabled by setting E as 1. When input S is 0 and
input R is 1, latch goes to reset state. Then the present output
Qn+1 goes to 0. When S input is 1 and R
input is 0, latch goes to set state and the present output Qn+1
goes to 1. When both input S and R are 0,
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latch goes to hold state and present output +1 = , where Qn is
previous output. When both input S
and R are 1, latch goes to invalid state, output and its
complement output is 1, ie +1 = +1 = 1.
SR flip flop:
The symbol, circuit diagram and truth table with states of +ve
edge triggered SR flip flop is
shown in figure 2.
Figure.2. Symbol, circuit diagram and truth table of +ve edge
triggered SR flip flop
The operation of SR flip flop is same as SR latch, but the
difference is output changes only during
the +ve edge of clock input signal CLK.
The characteristics equation of SR flip flop is +1 = +
JK flip flop:
The symbol, circuit diagram and truth table with states of +ve
edge triggered JK flip flop is
shown in figure 3.
Figure.3. Symbol, circuit diagram and truth table of JK flip
flop using gates
This flip flop is similar to SR flip flop, but the invalid state
of SR flip flop is avoided here. J is set
input similar to S and K is reset input similar to R. The
invalid state is eliminated by feedback
arrangement of and to input K and J inputs respectively by
3-input NAND gates. When clock pulse
CLK is 0, the flip flop hold the previous state. When J is 0 and
K is 1, the flip flop goes to reset state
during +ve edge of clock pulse. Then present output Qn+1 goes to
0. When J is 1 and K is 0, the flip flop
goes to its set state during +ve edge of clock pulse and the
present output Qn+1 becomes 1. When both J
and K are 0, flip flop goes to the hold state during +ve edge of
clock and the present output Qn+1 = Qn,
When both input J and K are 1, flip flop goes to toggle state
during +ve edge of clock, ie +1 = .
The characteristics equation of JK flip flop is +1 = +
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D flip flop
The symbol, circuit diagram and truth table with states of +ve
edge triggered D flip flop using
gates is shown in figure 4.
Figure.4. Symbol, circuit diagram and truth table of D flip flop
using gates.
D flip flop or Data flip flop uses SR flip flop, but the hold
and invalid states are avoided. Here the
reset and set states are used to store input and transfer it to
the output during the edge of clock pulse.
When clock pulse is 0, flip flop goes to hold state. When D is
0, the flip flop goes to its reset state and
output Q becomes 0 during the +ve edge of clock pulse. When D is
1, the flip flop goes to its set state and
output Q becomes 1 during the ve edge of clock pulse.
The characteristics equation of D flip flop is +1 =
T flip flop:
The symbol, circuit diagram and truth table with states of +ve
edge triggered T flip flop using
gates is shown in figure 5.
Figure.5. Symbol, circuit diagram and truth table of T flip flop
using gates
T flip flop or Toggle flip flop uses JK flip flop, but the set
and reset states are avoided. When
clock pulse is 0, flip flop goes to hold state. When T input is
0, flip flop goes to hold state during the +ve
edge of clock pulse and the present output +1 = . When T input
is 1, flip flop goes to toggle state
during the +ve edge of clock pulse and the present output +1 =
.
The characteristics equation of T flip flop is +1 =
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Master-slave JK flip flop:
The circuit diagram and truth table of master-slave JK flip flop
using gates are shown in figure 6.
Figure.6. Master-slave JK flip flop using gates
The master slave flip flop is used as a solution to the race
around problem in flip flops. In the JK
latch, the output is feedback to the input, and therefore
changes in the output results change in the input.
Due to this in the positive half of the clock pulse if J and K
are both high then output toggles
continuously. This condition is known as race around
condition.
To avoid race around condition, different methods are:
1. Keep clock pulse smaller than the propagation delay.
2. Using master-slave flip flop.
3. Using positive or negative edge triggering.
The master-slave JK flip flop consists of two flip flops: one is
called master which is enabled by
clock pulse first and other is called slave enabled by inverted
clock pulse. During +ve edge of clock,
master is active and slave is disable. Then masters state
depends on J and K input and slave goes to hold
state. During the ve edge of clock, master is disable and slave
is active. Then master hold previous
output, which transferred to slave input and its state depends
on master output.
Flip flops using ICs:
JK flip flop IC:
The pinout diagram, pin functions of dual, -ve edge triggered JK
flip flop IC-7476 is shown in
figure 4.a.
Figure.4.a. Pinout diagram and pin functions of IC-7476
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Figure.4.b. Circuit diagram and truth table of JK flip flop
using IC-7476
D flip flop:
The pinout diagram, pin functions of dual, +ve edge triggered D
flip flop IC 7474 is shown in
figure 6.a.
Figure 6.a. Pinout diagram and pin functions of IC-7474
The circuit and its truth table is shown if figure 6.b.
Figure.6.b. Circuit diagram and truth table of D flip flop using
IC-7474
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T flip flop:
The circuit diagram and truth table of T flip flop using JK flip
flop IC-7476 is shown in figure 7.
Figure.7. Circuit diagram and truth table of T flip flop using
IC 7476
PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULT:
Viva questions:
1. Differentiate latches and flip flops.(2 marks)
2. Draw the SR latch and flip flop using NOR gates. (2
marks)
3. Construct SR flip flop using JK flip flop (1 mark)
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EXPT. No. 5: SHIFT REGISTERS
AIM:
To realize different shift registers.
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. ICs
a) 7474 2 Nos.
b) 7432 1 No.
THEORY:
Shift register is a type of sequential logic circuit that is
used for the storage or transfer of data in
the form of binary numbers. It shifts the data out once every
clock cycle, hence the name shift register. It
basically consists of several single bit D flip flops, one for
each bit (0 or 1) connected together in a serial
or daisy-chain arrangement so that the output from one flip flop
becomes the input of the next latch and
so on.
The number of individual D flip flops required to make up a
single shift register is determined by
the number of bits to be stored. In general, n-bit can be stored
by individual data flip flops.
Shift registers are used for data storage or data movement and
are used in computers. Usually to
convert the data from either a serial to parallel or parallel to
serial format. The individual D flip flops that
make up a single shift register are all driven by a common clock
signal CLK, making them synchronous
devices.
Generally, shift registers operate in one of four different
modes. They are:
a. Serial-In Serial-Out (SISO)
b. Serial-In Parallel-Out (SIPO)
c. Parallel-In Serial-Out (PISO)
d. Parallel-In Parallel-Out (PIPO)
SISO shift register:
The circuit diagram of serial-in serial-out shift register is
shown in figure 1.a.
Figure.1.a. Four bit-Serial-In Serial-Out Shift Register using D
flip flop IC 7474
Each D flip flop store one bit, hence require four flip flops
for 4-bit shift register. The output of
one flip flop is connected to input to the next and for each
clock the input state is shifted to the output.
Then for +ve edge of each clock pulse: Q3 = D3, Q2 = Q3, Q1 = Q2
and Q0 = Q1. If we connect serial input
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Sin as D3 and take serial output Sout from Q0, the circuit out
serial data in to serial out for each clock pulse.
These arrangements are for left shift and for right shift,
organize the bits in opposite direction. The truth
table of serial-in serial-out shift register is shown in figure
1.b.
Figure.1.b. Truth table of Serial-In Serial-Out shift
register.
Observed results: (In left page)
Serial input data Sin = 1011
SIPO shift register:
The circuit diagram of serial-in parallel-out shift register is
shown in figure 2.a.
Figure.2.a. Four-bit Serial-In Parallel-Out Shift Register using
D flip flop IC 7474
The circuit is similar to SISO, but the parallel output is
obtained from the output of each flip flop.
So during the fourth clock pulse the parallel data is available
at Q3Q2Q1Q0. The truth table of serial-in
parallel-out is shown in figure 2.b.
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Figure.2.b. Truth table of Serial-In Parallel-Out shift
register
Observed results: (In left page)
Serial input data Sin = 1010
PISO shift register:
The circuit diagram of serial-in parallel-out shift register is
shown in figure 3.a.
Figure.3.a. Four-bit Parallel-In Serial-Out shift register using
D flip flop IC 7474
Here 4-bit parallel inputs P3 to P0 are loaded to each flip flop
through OR gate initially. After
loading input to each flip flop, all inputs are set as 0. The
output state of each flip flop is fed to input of
next stage by ORing with the parallel input. The truth table of
parallel-in serial-out shift register is shown
in figure 3.b.
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Figure.3.b. Truth table of Parallel-In Serial-Out shift
register
Observed results: (In left page)
Parallel input data P = 1010
PIPO shift register:
The circuit diagram of parallel-in parallel-out shift register
is shown in figure 4.a.
Figure.4.a. Parallel-In Parallel-Out shift register using D flip
flop IC 7474
Here 4-bit parallel inputs P3 to P0 are directly connected to
the input of flip flops. For the clock
input each input bit are shifted to output and are taken as
parallel output bits Q3 to Q0. The truth table for
parallel-in parallel-out shift register is shown in figure
4.b.
Figure.4.b. Truth table of Parallel-In Parallel-Out shift
register
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Observed results: (In left page)
Parallel input data i) P = 1101
ii) P = 0110
PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULT:
Viva questions:
1. Draw the circuit diagram of 4-bit serial-in serial-out shift
register with left shift operation. (1
mark)
2. Draw the circuit diagram of 4-bit parallel-in serial-out
shift register with load/shift input. (2
marks)
3. Compare different shift registers. (1/2 mark)
4. Obtain 4-bit parallel-in serial-out shift register using JK
flip flops (1 mark)
5. List out different applications of shift registers. (1/2
mark)
(Hint for Q2)
The general block diagram:
Where X is control circuit, FF is flip flop, P is parallel
input, D is flip flop input and Q is output.
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Design of control circuit: M is mode control or load/shift
input. If M=0, shift operation otherwise it is
load operation. During shift operation, D3 = P3, D2 = Q3, D1 =
Q2 and D0 = Q1. During load operation,
D3 = P3, D2 = P2, D1 = P1 and D0 = P0.
Develop truth table for X3, X2, X1 and X0.
Draw K-map for each truth table and obtain Boolean expression
for D3, D2, D1 and D0.
Complete the X3, X2, X1 and X0 circuits with logic gates.
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EXPT. No. 6: MULTIPLEXERS AND DEMULTIPLEXERS USING GATES AND
ICs
AIM:
a) To realize multiplexer and demultiplexer using basic
gates
b) To realize multiplexer and demultiplexer using ICs 74151 and
74138 respectively.
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. ICs
a) 7404 2 Nos.
b) 7411 2 No.
c) 7432 1 No.
d) 74151 1 No.
e) 74138 1 No.
THEORY:
Multiplexer
A multiplexer is a combinational circuit that selects binary
information from one of many input
lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of
selection lines. Normally there are 2n
input lines and n selection lines whose bit combination
determine
which input is selected. The symbol and condensed truth table of
4x1 multiplexer are shown in figure 1.a.
Figure.1.a. Symbol and condensed truth table of 4 x 1
multiplexer
Design of 4x1 multiplexer using basic gates
From the condensed truth table, we can obtain the following
Boolean expression for 4 x 1
multiplexer.
Y = D0S 1S 0 + D1S 1S0 + D2S1S 0 + D3S1S0
To implement this Boolean expression, 3 input AND gate is
required. The pinout diagram of 3
input AND gate IC 7411 is shown in figure 1.b.
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Figure.1.b. Pinout diagram of IC 7411
The circuit diagram of 4 x 1 multiplexer using basic gates is
shown in figure 1.c.
Figure 1.c. Circuit diagram of 4 x 1 multiplexer using gates
Observed results: (In left page)
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8 x 1 Multiplexer using IC 74151
The pinout diagram, functions of pins and truth table of 8 x 1
multiplexer IC 74151 are shown in
figure 1.d.
Figure.1.d. Pinout diagram, functions of pins and condensed
truth table for IC 74151
Observed results: (In left page)
Demultiplexer:
Demultiplexer is a counter part of multiplexer and has one input
and more than one output. It is
used to send an input signal to one of many output lines
according to the combination of selection lines.
This is similar to a decoder, but a decoder is used to select
among many outputs, while a demultiplexer is
used to send a signal among many outputs. Normally there are 2n
output lines and n selection lines whose
bits combination determines which output is selected. The symbol
and condensed truth table of 1 x 4
demultiplexer are shown in figure 2.a.
Figure.2.a. Symbol and condensed truth table of 1 x 4
demultiplexer
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Design of 1 x 4 demultiplexer using basic gates
From the condensed truth table, the Boolean expressions for
outputs are:
0 = 1 0
1 = 1 0
2 = 1 0
2 = 10
The circuit diagram of 1 x 4 demultiplexer using basic gates is
shown in figure 2.b.
Figure 2.b. Circuit diagram of 1 x 4 demultiplexer using
gates
Observed results: (In left page)
1 x 8 Demultiplexer using IC 74138
The pinout diagram, functions of pins and truth table of 1 x 8
decoder/demultiplexer IC 74138 are
shown in figure 2.c.
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Figure 2.c. Pinout diagram, functions of pins and truth table of
IC 74138
The circuit diagram for 1 x 8 demultiplexer using IC 74138 is
shown in figure 2.d. Here the active
high enable input is using as data input.
Figure.2.d. Circuit diagram for 1 x 8 multiplexer using IC
74138
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Observed results: (In left page)
PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULT:
Viva questions:
1. Implement 8 x 1 multiplexer using 4 x 1 multiplexers. (2
marks)
2. Differentiate multiplexers and encoders. (1 mark)
3. How many select lines are required for 16 x 1 multiplexers
and 1 x 32 demultiplexers. (1mark)
4. Why multiplexers are called data selectors? (1 mark)
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EXPT. No. 7: REALIZATION OF COMBINATIONAL CIRCUITS USING
MULTIPLEXER/DEMULTIPLEXER ICs
AIM:
To realize combinational circuits using multiplexer and
demultiplexer ICs.
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. ICs
a) 7404 1 No.
b) 74151 1 No.
c) 74138 1 No.
d) 7420 1 No.
THEORY:
Combinational circuits using multiplexer ICs
Any Boolean function of n-variables can be implemented using a
multiplexer with n-1 selection
lines. For that, the first n-1 input variables of the function
will be connected to the selection lines and the
nth input variable is evaluated according to the value of the
minterms of the function. These evaluated
values are connected to the data input lines. The implementation
of a Boolean function
, , , = (1, 3, 4, 11, 12, 13, 14, 15) using 8 x 1 multiplexer
IC- 74151 is shown in figure 1.
Figure 1.a. Truth table for the given Boolean function to
implement by multiplexer
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Figure 1.b. Circuit diagram for the given Boolean function using
multiplexer IC 74151
Observed Truth Table: (In left page)
Combinational circuits using demultiplexer ICs
A decoder/demultiplexer provides 2n minterms of n input
variables (select lines). Each output is
asserted by a unique pattern of input variables. Any Boolean
function can be expressed in SOP form and a
decoder that generates the minterms of the function, together
with external OR gates can produce the
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required Boolean functions. This way, any combinational circuit
with n inputs and m outputs can be
implemented by 1 x 2n demultiplexer (n x 2
n decoder) and m OR gates (if demultiplexer has active low
output, use NAND gates).
The implementation of full adder using demultiplexer IC 74138 is
shown in figure 2.
Figure.2.a. Truth table and Boolean functions of full adder
Sum S is obtained by ORing Y1, Y2, Y4 and Y7; carry out Cout is
obtained by ORing Y3, Y5, Y6
and Y7. In case of demultiplexer of active low output, use NAND
gate instead of OR.
The pin out diagram of IC 7420, circuit of full adder using
demultiplexer IC 74138 and 7420 is
shown in figure 2.b.
Figure.2.b. Pinout diagram of IC 7420 and circuit diagram of
full adder using IC 74138 and 7420
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Observed Truth Table: (In left page)
PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULT:
Viva questions:
1. Design the following Boolean expressions using 8 x 1
multiplexer.
i. , , , = (, ,, , )
ii. , , , = (, , , , )
(2 marks)
2. Design a full subtractor using 1 x 8 demultiplexer. (2
marks)
3. Design a 3-bit binary to gray code converter by 1 x 8
demultiplexer. (1 marks)
Note: You can also expect basic questions from experiment no.1
to 6
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EXPT. No. 8: ASYNCHRONOUS COUNTERS USING FLIP-FLOPS AND ICs
AIM:
To realize asynchronous counters (ripple counter) using flip
flops and ICs.
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. ICs
a) 7476 2 Nos.
b) 7493 1 No.
c) 7486 1 No.
d) 7408 1 No.
THEORY
Asynchronous counter using flip-flops
Counter is a sequential circuit to produce a prescribed sequence
of states according to the input
pulses. The input pulse is clock pulse and the sequence of
states follows binary number sequences or any
other sequence. A counter that follow binary number sequences is
called binary counter and an n-bit
binary counter consists of n flip-flops and can count in binary
from 0 to 2n 1 and such a counter is called
Modulo-N (Mod-N) counter, where N is the number of states and N
= 2n.
The binary counter with forward counting is called up-counter
and reverse counting is called
down-counter.
One type of binary counter is ripple counter or asynchronous
counter. In this the clock input is
applied only to the first flip-flop and all subsequent
flip-flops are clocked by the output of the preceding
flip-flop. Due this rippling of flip-flops by clock pulses, the
counter is called ripple counter.
The circuit diagram and truth table of 2-bit asynchronous
up-counter (Mod-4 counter) using JK
flip-flop IC 7476 is shown in figure 1.
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Figure. 1. Two-bit asynchronous up-counter circuit and truth
table using JK flip-flop
Here the JK flip-flop is using as T flip-flop by keeping its
toggle state. For up-counting the output
Q of first flip-flop is connected to clock input of next
flip-flop. So the output of each flip-flop changes
only during the ve edge of the clock pulse.
The circuit diagram and truth table of 2-bit asynchronous
down-counter (Mod-4 counter) using
JK flip-flop IC 7476 is shown in figure 2.
Figure. 2. Two-bit asynchronous down-counter circuit and truth
table using JK flip-flop
For down-counting the complement output Q of first flip-flop is
connected to clock input of next
flip-flop. So the output of next stage flip-flop change only
during the +ve edge of the clock pulse and
hence down-counting takes place.
The circuit diagram and truth table of 2-bit asynchronous
up/down-counter using JK flip-flop is
shown in figure 3.
Figure.3. Two-bit asynchronous up/down-counter circuit and truth
table using JK flip-flop
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For up-counter, keep / signal as 0, then XOR gate behaves as a
buffer for clock pulse of
next stage. For down-counter, keep / signal is 1, then XOR gate
behaves as inverter and
complement the clock pulse to next stage.
The advantage of the ripple counter is easy to implement, but
the disadvantage is propagation
delay depends on number of flip-flops. It is because of the
rippling of clock from one stage to other.
Asynchronous counter using ICs
The pinout diagram and functions of pins 4-bit binary ripple
counter IC 7493 is shown in figure
4.a.
Figure.4.a. Pinout diagram and pin functions of 4-bit binary
counter IC 7493
The circuit diagram of 4-bit asynchronous binary up-counter
(Mod-16 counter) using IC 7493 is
shown in figure 4.b.
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Figure.4.b. Circuit diagram of 4-bit asynchronous counter using
IC 7493
Here the output Q0 (first flip-flop output) is connected to
clock input of second flip-flop 1. The
clock input for the other flip-flops are internally connected in
the IC. For counting, any one of the master
reset MR1 and MR2 is set to 0.
Design of mod-10 up-counter
Given that N = 10. We have N = 2n, where n is the number of
bits/flip-flops in the counter.
ie, 2n = 10. Then =
ln 10
ln 2= 3.3
Therefore counter require more than 3 bit, and choose next
integer 4. So we can choose 4-bit binary
counter.
The state diagram of mod-10 up-counter is shown in figure
5.a.
Figure 5.a. State diagram of mod-10 up-counter
Consider the truth table of the 4-bit counter with master reset
MR1 as output and Q3-Q0 as input to reset
counter from its 9th state to 0
th state. The truth table and K-map for MR1 is shown in figure
5.b.
Figure.5.b. Truth table for mod-10 up-counter and K-map for
MR1
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Then the Boolean expression for MR1 = Q3Q1.
The circuit diagram and truth table for mod-10 up-counter using
IC 7493 is shown in figure 5.c.
Figure.5.c. Circuit diagram and truth table of mod-10 up-counter
using IC 7493
PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULT:
Viva questions:
1. Draw the circuit diagram of 4-bit ripple up-counter using
flip-flops. (1 mark)
2. What is the propagation delay of n-bit ripple counter, if the
delay of T flip-flops is d. (1mark)
3. Draw the pinout diagram of IC-7493 and identify the pin
functions. (1 mark)
4. Design a mod-6 asynchronous down-counter. (2 marks)
Note: You can also expect basic questions from experiment no.1
to 7, pinout diagram and pin
functions of ICs used in the lab so far.
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Department of ECE, VKCET Page 45
EXPT. No. 9: SYNCHRONOUS COUNTERS USING FLIP-FLOPS AND ICs
AIM:
To realize synchronous counters using flip flops and ICs.
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. ICs
a) 7476 2 Nos.
b) 7408 1 No.
c) 7486 1 No.
d) 74193 1 No.
THEORY:
Synchronous counter using flip-flops
This is another type of binary counter. In this the clock input
is applied to all flip-flops, due to
this all states change under the control of single clock. The
operation of this counter is same as
asynchronous counter, but this is faster one because all states
are changed by a single clock.
Design of 3-bit synchronous up-counter using flip-flops:
For 3-bit counter, there are 23 = 8 states, hence it is also
called mod-8 counter. The circuit require
3 flip-flops (prefer T). The state diagram, present and next
state of truth tables along with the input of
flip-flops and K-Maps for each T input is shown in figure 1.a.
Here the T input for each flip-flop is
obtained according to the present and next state of the
flip-flop. It may be either toggle state (T=1) or hold
state (T=0).
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Figure 1.a. State diagram, truth table and K-maps for 3-bit
(mod-8) synchronous up counter.
The circuit diagram and truth table of 3-bit synchronous
up-counter using flip-flops is shown in
figure 1.b.
Figure 1.b. Circuit diagram and truth table of 3-bit synchronous
up-counter using flip-flops
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Design of 3-bit synchronous down-counter using flip-flops:
The state diagram, present and next state of truth tables along
with the input of flip-flops and K-
Maps for each T input is shown in figure 2.a
Figure.2.a. State diagram, truth table and K-maps for 3-bit
(mod-8) synchronous down-counter.
The circuit diagram and truth table of 3-bit synchronous
up-counter using flip-flops is shown in
figure 2.b. and 2.c.
Figure.2.b. Circuit diagram of 3-bit synchronous down-counter
using flip-flops
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Figure.2.c. Truth table of 3-bit synchronous down-counter using
flip-flops
Design of 2-bit synchronous up/down-counter using
flip-flops:
The state diagram, present and next state of truth tables along
with the input of flip-flops and K-
Maps for each T input is shown in figure 3.a. Here an input M is
used for up/down count action. If M = 0,
up counting, else down counting is performed by the counter.
Figure.3.a. State diagram, truth table and K-maps for 2-bit
(mod-4) synchronous up/down-counter.
The circuit diagram and truth table of 2-bit synchronous
up/down-counter using flip-flops is
shown in figure 3.b.
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Figure.3.b. Circuit diagram and truth table of 2-bit synchronous
up/down-counter using flip-flops
Synchronous counter using ICs
The pinout diagram and functions of pins 4-bit (Mod-16) binary
synchronous counter IC 74193 is
shown in figure 4.a.
Figure 4.a. Pinout diagram and pin functions of 4-bit binary
synchronous counter IC-74193
The circuit diagram and truth table of 4-bit (Mod-16)
synchronous up-counter using IC-74193 is
shown in figure 4.b.
Figure 4.b. Circuit diagram and truth table of 4-bit synchronous
up-counter using IC-74193
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PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULT:
Viva questions:
1. Design mod-14 synchronous up/down counter using flip-flops.
(2 marks)
2. Construct a circuit to divide a clock signal frequency of f
by 4. (2 marks)
3. Design mod-16 counter using mod-4 counters. (1 mark)
Note: Prepare all ICs pinout diagram and functions of each
pins.
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EXPT. No. 10: RING COUNTER AND JOHNSON COUNTER USING
FLIPFLOPS
AIM:
To realize ring counter and Johnson counter using flip
flops.
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. IC 7474 2 Nos.
THEORY
Ring counter
A ring counter is a circular shift register with only one
flip-flop being set at any particular time;
all others are cleared. The single bit is shifted from one
flip-flop to the next to produce the sequence of
timing signals. Therefore an n-bit ring counter has n-states and
requires n D flip-flops to hold the state.
Design of 3-bit ring counter
The state diagram, state table along with K-map for each D
flip-flop input of 3-bit ring counter is
shown figure 1.a.
Figure 1.a. State diagram, state table and K-maps for 3-bit ring
counter
The circuit diagram and truth table of 3-bit ring counter using
D flip-flop IC 7474 is shown in
figure 1.b.
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Figure.1.b. Circuit diagram and truth table of ring counter
using D flip-flop IC 7474
Johnson counter
An n-bit ring counter circulates a single bit among the
flip-flops to provide n distinguishable
states. Johnson counter is an n-bit switch-tail ring counter
with 2n states. The switch-tail ring counter is a
circular shift register with the complemented output of the last
flip-flop connected to the input of the first
flip-flop.
Design of 3-bit Johnson counter
The state diagram, state table along with K-map for each D
flip-flop input of 3-bit Johnson
counter is shown figure 2.a.
Figure 2.a. State diagram, state table and K-maps for 3-bit
Johnson counter
The circuit diagram and truth table of 3-bit Johnson counter
using D flip-flop IC 7474 is shown in
figure 1.b.
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Figure.1.b. Circuit diagram and truth table of Johnson counter
using D flip-flop IC 7474
PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULTS:
Viva questions:
1. Design a counter with the following state diagram. (2
marks)
2. Design 4-bit ring counter using T flip-flops. (1 marks)
3. Design 4-bit Johnson counter using T flip-flops. (1 mark)
4. Identify f/8 counter and draw the circuit. (1 mark)
Note: Prepare all ICs pinout diagram and functions of each
pin.
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EXPT. No. 11: FOUR-BIT MAGNITUDE COMPARATOR
AIM:
To realize a 4-bit magnitude comparator.
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. IC 7485 1 No.
THEORY:
The comparison of two numbers is an operation that determines
whether one number is greater
than, equal to, or less than the other number. Two numbers, A
and B can be compared results the
followings: = 0 = 1, < 1 = 1 > 2 = 1. Where A
and B may be any n-bit number.
The truth table and circuit diagram of 1-bit magnitude
comparator is shown in figure.1.
Figure.1. Truth table and circuit diagram of 1-bit magnitude
comparator
(Note: Choose appropriate ICs and do the experiment)
The pinout diagram, pin functions and truth table of 4-bit
magnitude comparator IC 7485 is
shown in figure 2.a.
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Figure 2.a. Pinout diagram, pin functions and truth table of
4-bit magnitude comparator IC 7485
The circuit diagram of 4-bit magnitude comparator using IC-7485
is shown in figure 2.b.
Figure 2.b. 4-bit magnitude comparator using IC-7485
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Observed results:
PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULTS:
Viva questions:
1. Draw the circuit diagram of 8-bit magnitude comparator using
IC-7485. (3 marks)
2. Design 2-bit comparator using 1x8 demultiplexer. (2 mark)
Note: Prepare all ICs pinout diagram and functions of each
pins.
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EXPT. No. 12: BCD TO 7-SEGMENT DECODER AND DISPLAY
AIM:
To design and realize BCD to 7-segment decoder and display
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. Resistor 180 7 No.
5. ICs
a) 7447 1 No.
b) 7-segment display (Common anode) 1 No.
THEORY
BCD to 7-segment decoder is a combinational circuit to convert
BCD number to 7-bit binary
output. BCD number is binary coded decimal, used to represent
decimal number in binary form. Then for
one digit BCD number, there will be 4-bit binary number.
7-segment display is LED display, organized by 7 LEDs for
displaying all numeric numbers (0 to
9) and few alphabetic characters (A, b, C, d, E, F, H, I, P, t,
v). There is also to display dot by 8th LED.
There are two types of 7-segment displays:
1) Common anode display Here the anode terminal of all LEDs are
common and input to the
display is connected to cathode of each LED. The symbol,
internal diagram and pinout diagram
of common anode display is shown in figure 1.a.
2) Common cathode display Here the cathode terminal of all LEDs
are common and input to the
display is connected to anode of each LED.
Common anode 7-segment display
Figure 1.a. Symbol, internal diagram and pinout diagram of
common anode 7-segment display.
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The IC-7447 is 4-bit BCD to 7-segment decoder IC, which convert
BCD into corresponding
common anode 7-segment signal. The pinout diagram and functions
of pins in IC-7447 is shown in
figure 1.b.
Figure 1.b. Pinout diagram and functions of pins in IC-7447
The truth table of IC-7447 is shown in figure 1.c.
Figure 1.c. Truth table of IC 7447
The circuit diagram of BCD to 7-segment decoder and display is
shown in figure 2.a.
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Figure 2.a. BCD to 7-segment decoder and display.
Observation table (Left side of the record)
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PROCEDURE:
1. Place the ICs on trainer kit.
2. Wire the circuit diagram.
3. Connect VCC and GND to respective pins of trainer kit.
4. Connect the inputs to the input switches provided in the
trainer kit.
5. Connect the outputs to the terminals of output LEDs.
6. Apply various combinations of inputs according to the truth
table and observe condition of LEDs.
RESULT:
Viva questions:
1. Design BCD to decimal decoder (2 marks)
2. Design a 4-bit Gray code to 4-bit binary converter (3
marks)
Note: Prepare all ICs pinout diagram and functions of each
pin.
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EXPT. No. 13: ASTABLE AND MONOSTABLE MULTIVIBRATORS USING
ICs
AIM:
a) To design astable multivibrator using IC-555.
b) To design monostable multivibrator using IC-555.
COMPONENTS REQUIRED:
1. Digital IC Trainer kit
2. Connecting wires
3. Bread board (If required)
4. Digital storage oscilloscope / CRO
5. Function generator
6. Resistors
7. Capacitors
8. IC 555 1 No.
THEORY:
Timer IC 555
The Timer IC 555 is a highly stable device for generating
accurate time delays or oscillation. The
piout diagram and functions of pins are shown in figure 1.
Figure 1. Pinout diagram and pin functions of IC-555
Astable multivibrator using IC-555
Astable multivibrator is a free running multivibrator or square
wave generator. It has no stable
state, ie the output switches between ON and OFF states. The
circuit diagram for astable multivibrator
using IC-555 and the wave forms are shown in figure 2.a and 2.b.
respectively.
The equation for time period of output wave = 0.693 1 + 22 ,
where ON period
1 = 0.693 1 + 2 and OFF period 2 = 0.6932. The duty cycle of
output wave form
=1+21+22
100% .
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Figure 2.a. Astable Multivibrator using IC-555
Figure 2.b. Model wave forms
Design:
For f = 1kHz and D=75%,
T = 1ms, T1 = D x T = 0.75 x 1ms = 0.75ms, T2 = T T1 =
0.25ms
We have =1+21+22
100% , 1+21+22
= 0.75,12
= 2.
From 2 = 0.6932, choose C = 0.1F, 2 = 2
0.693= 3.6.
Then R1 = 2R2 = 7.2k (Use 6.8k std. value)
Observed waveforms: (on left page)
(Draw the wave at Vo and Vc with time periods)
Monostable multivibrator using IC-555
The monostable multivibrator is a one-shot multivibrator, in
which the duration of the
output pulse is determined by the RC circuit connected
externally to the 555 timer. It has one
stable state and one unstable state. For applying a trigger to
the circuit, it goes to its unstable state
from its stable state. After the time determined by RC circuit,
it comes back to its stable state
from the unstable state. The circuit diagram for monostable
multivibrator using IC-555 and the
wave forms are shown in figure 3.a. and 3.b. respectively.
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The equation for the time period of unstable state is = 1.1
Figure 3.a. Monostable multivibrator using IC-555
Figure 3.b. Model wave forms
Design
For T = 5ms, choose C = 0.1F. We have = 1.1, then R = 45k (Use
std. value 43k)
Note: For trigger in, choose t1 < T and Tt > T. Then for
given T = 5ms, choose t1 = 1ms and
Tt = 9ms, then frequency of trigger pulse is 1/10ms =100Hz, with
duty cycle 90%
Observed waveforms: (On left page)
(Draw the wave at Trigger in, Vo and Vc with time periods)