Digital Low Level RF control for Advanced Light Source · DDS LO (IF/CLK = 2/11) DLO I DLO Q DLOphi DDC DLO Q DLO I FIR FIR Cart2Polar CORDIC C art2Pol CORDIC Clip Linerize Interpolate

Digital Low Level RF control for Advanced Light SourceQiang Du1, Lawrence R Doolittle1, Kenneth Baptiste1, Michael Betz1, Massimiliano Vinco1, Gang Huang1

1Lawrence Berkeley National Laboratory, Berkeley, CA 94720

Abstract

A digital LLRF control system has been built and installed as part of the Storage Ring RF system upgrade project at Advanced Light Source in LBNL. In order toenable a configurable two klystrons driving two cavities operation, the system implements low-noise RF front-end, non-IQ digital receiver/digitizer, double rate feedbackcontrol loop, and 42 channels distributed RF monitor with integrated fast interlock across multiple chassis and subsystems. Chassis level test shows > 78 dB isolationbetween feedback channels, and 128 fs RMS time jitter [10Hz, 50MHz] at Klystron drive ports. Preliminary test result shows RF field stability of 0.01% in amplitudeand 0.01◦ in phase at 499.654 MHz for the band above 1 Hz (no beam).

System setup: LLRF controller + RF monitors + Fast RF interlock

ADC PHY

ADC PHY

ADC PHYX12

14-bit ADCADS62P49

14-bit ADCADS62P49

229.0MSPS

229.0MSPS

14-bit ADCLT2175

14-bit ADCLT2175

14-bit ADC4X3 CHAN

LT2175

114.5MSPS

14-bit ADCLT2175

14-bit ADCLT2175

14-bit ADC4X3 CHAN

LT2175

114.5MSPS

14-bit ADCLT2175

14-bit ADCLT2175

14-bit ADCLT2175

14-bit ADC4X4 CHAN

LT2175

114.5MSPS

LO458.0 MHz

LO458.0 MHz

LO458.0 MHz

LO458.0 MHz

... X12

LO458.0 MHz

LO458.0 MHz

... X12

LO458.0 MHz

LO458.0 MHz

... X16

ADC PHYX12

ADC PHYX16

Cavity1 Cell

Cavity2 Cell

Cavity1 RevCavity2 FwdCavity2 RevBPMMaster Osc

Cavity1 Rev

Kly1 Drive RevKly1 Out FwdKly1 Out RevCirc1 Load FwdCirc1 Out FwdCirc1 Out Rev

Kly1 Drive Fwd

Kly2 Drive RevKly2 Drive Fwd

Kly2 Out FwdKly2 Out RevCirc2 Load FwdCirc2 Out FwdCirc2 Out Rev

Magic T In RevMagic T Load FCirc2 Load RevTest Load 1 FwdTest Load 1 RevTest Load 2 Fwd

Magic T In Fwd

Test Load 2 Rev

LO GEN

114.5MHz

229.0MHz

458.0MHz499.64MHz

Master Oscillator

Circular RAM(64k)

DDS LO(IF/CLK = 2/11)

DLO I

DLO Q

DLO phi

DDC

DLO Q

DLO I

FIR

FIR

Cart2Polar

CORDIC

Cart2Polar

CORDIC

ClipLinerize

Interpolate

P

A

Cart2Cart

CORDIC

Q

I

PHS

phs set

AMP

amp set

DLO phi

DAC PHYEN

offset

14-bit DAC

DAC3283

229.0MSPS

LO458.0 MHz

Kly2 Drive

Permit

ClipLinerize

Interpolate

P

A

Cart2Cart

CORDIC

Q

I

PHS

phs set

AMP

amp set

DLO phi

DAC PHYEN

offset

14-bit DAC

DAC3283

229.0MSPS

LO458.0 MHz

Kly1 Drive

Permit

runtimedecimation

2nd orderCIC

Permit

DDC

DLO Q

DLO I

DDC

DLO Q

DLO I

DDC

DLO Q

DLO I... X12

Aurora 8b10b

GTXduplex

Integral

Ki

Kp

-SP

AMP/PHS PI

Circular RAM(64k)

runtimedecimation

2nd orderCIC

Permit

DDC

DLO Q

DLO I

DDC

DLO Q

DLO I... X16

Aurora 8b10b

GTXduplex

DDC

DLO Q

DLO I

DDC

DLO Q

DLO I... X12

DDS LO(IF/CLK = 2/11)

DLO I

DLO Q

DLO phi

Aurora 8b10b

GTXduplex

Aurora 8b10b

GTXduplex

Fast RF

Power Interlock

(14)

Fast RF

Power Interlock

(28)

RISC-VCPU

UART

GBE MAC

GBE MAC

GBE MAC

Circular RAM(64k)

MODBUS RTU - TO PLC

CMODSerial

&

CMODSerial

ARC Status(16)

ARC Pwr Status(16)

&

Config

RF Permit

LLRF FPGA

RFMON FPGA Interlock FPGAField IO FPGA

Digital LLRF chassis

Figure: LLRF chassis assembly

Features

I 74.3 dBFS signal-noise ratio on feedback channels, 72.1 dBFS on monitorchannels;

I > 78 dB channel isolation between feedback channels;

I 128 fs RMS time jitter [10Hz, 50MHz] at Klystron Drive ports;

I < 3.4 microsecond total feedback group delay;

I < 0.01% amplitude and phase stability (preliminary);

I 42 channels distributed synchronous digital oscilloscope with deterministiclatency;

I 1.45 microsecond maximum RF power interlock latency;

I Programmable feedback and interlock configurations with respect tooperation modes;

I Non-OS, Non-Ethernet, direct hardware integration with high power RFand personnel safety interlocks;

I EPICS and various diagnostic software support;

I Fully open source from hardware, gateware, firmware to software design;

Status

As part of ALS Storage Ring RF System upgrade project, the digital LLRFcontrol system was commissioned in March 2017 and enabled nominaloperation with desired preliminary performance. Further optimization isplanned together with additional upgrades in the FY 2018.

Digital Low Level RF control for Advanced Light Source LLRF17 Workshop, Barcelona, Spain, Oct. 2017Q.Du, L.R Doolittle, K.Baptiste, M.Betz, M.Vinco, G.Huang P-46