Digital Integrated Circuits – EECS 312 http://ziyang.eecs.umich.edu/ ∼ dickrp/eecs312/ Teacher: Robert Dick Office: 2417-G EECS Email: [email protected]Phone: 734–763–3329 Cellphone: 847–530–1824 GSI: Myung-Chul Kim Email: [email protected]HW engineers SW engineers 0 1 2 3 4 5 6 7 8 9 10 200 220 240 260 280 300 Current (mA) Time (seconds) Typical Current Draw 1 sec Heartbeat 30 beats per sample Sampling and Radio Transmission 9 - 15 mA Heartbeat 1 - 2 mA Radio Receive for Mesh Maintenance 2 - 6 mA Low Power Sleep 0.030 - 0.050 mA Year of announcement 1950 1960 1970 1980 1990 2000 2010 Power density (Watts/cm 2 ) 0 2 4 6 8 10 12 14 Bipolar CMOS Vacuum IBM 360 IBM 370 IBM 3033 IBM ES9000 Fujitsu VP2000 IBM 3090S NTT Fujitsu M-780 IBM 3090 CDC Cyber 205 IBM 4381 IBM 3081 Fujitsu M380 IBM RY5 IBM GP IBM RY6 Apache Pulsar Merced IBM RY7 IBM RY4 Pentium II(DSIP) T-Rex Squadrons Pentium 4 Mckinley Prescott Jayhawk(dual) IBM Z9
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Digital Integrated Circuits – EECS 312
http://ziyang.eecs.umich.edu/∼dickrp/eecs312/
Teacher: Robert DickOffice: 2417-G EECSEmail: [email protected]: 734–763–3329Cellphone: 847–530–1824
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX using logic gates
A B
I0
I1
I2
I3
Z
37 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX using TGs
I3
I0
I2
I1
AA BB
ZZ
38 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
C
C
C
C
A
B
D
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
C
C
C
C
A
B
DC=1
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
C
C
C
C
A
B
DC=1
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
C
C
C
C
A
B
D
D=A
C=1
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
C
C
C
C
A
B
D
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
C
C
C
C
A
B
D
C=0
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
C
C
C
C
A
B
D
C=0
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
C
C
C
C
A
B
D
D=BC=0
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
2:1C
C
C
C
A
B
DA
BC C
D
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Hierarchical MUX implementation
4 :1
mux
4 :1
mux
8 :1
mux
2 :1
mux
0
1
2
3
0
1
2
3
S
S1
S0
S1
S0
Z
ACB
I0
I1
I2
I3
I4
I 5
I6
I7
0
1
40 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Alternative hierarchical MUX implementation
00
11SS
00
11SS
00
11 SS
00
11SS
00
11
S 1
22
33S 0
AA BB
II00
II11
II22
II33
II44
II55
II66
II77
CC
CC
CC
41 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX examples
2:1
m ux
I0
I1
A
Z
Z = AI0 + AI1
42 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX examples
I0
A
I1
I2
I3
B
Z4:1
m ux
Z = AB I0 + ABI1 + AB I2 + ABI3
43 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX examples
I0
A
I1
I2
I3
B
Z8:1
m ux
C
I4
I5
I6
I7
Z = AB C I0 + ABCI1 + ABC I2 + ABCI3+
AB C I4 + ABCI5 + ABC I6 + ABCI7
44 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX properties
A 2n : 1 MUX can implement any function of n variables
A 2n−1 : 1 can also be used
Use remaining variable as an input to the MUX
45 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX example
F (A,B,C ) =∑
(0, 2, 6, 7)
= AB C + ABC + ABC + ABC
46 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Truth table
A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
47 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Lookup table implementation
8:1
MUX
1
0
1
0
0
0
1
11
0
1
2
3
4
5
6
77 S2 S1 S0
AA BB CC
FF
48 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX example
F (A,B,C ) =∑
(0, 2, 6, 7)
= AB C + ABC + ABC + ABC
Therefore,
AB → F = C
AB → F = C
AB → F = 0
AB → F = 1
49 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Truth table
A B C F0 0 0 10 0 1 10 1 0 10 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1
F=C
50 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Truth table
A B C F0 0 0 10 0 1 10 1 0 10 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1
F=C
50 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Lookup table implementation
S1 S0
AA BB
4:1
MUX
0
1
2
33
00
11
FF
51 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Logic design summary
Logic gate, transmission gate, and pass transistor design eachhave applications.
MUX-based design provides a good starting point fortransmission gate and pass transistor based design.
52 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Examples
Instead of flying through a bunch of slides, let’s try examples.
f (a) = a.
f (a) = a
f (a, b) = ab
f (a, b) = ab (Check Figure 6-33 in J. Rabaey, A. Chandrakasan,and B. Nikolic. Digital Integrated Circuits: A Design Perspective.Prentice-Hall, second edition, 2003!)
f (a, b, c) = ab + bc (try both ways).
Derive and explain.
53 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Upcoming topics
Alternative logic design styles.
Latches and flip-flops.
Memories.
54 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Lecture plan
1. Interconnect: Rent’s rule and coupling capacitance
2. Elmore delay modeling
3. Logic design
4. Homework
55 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Homework assignment
9 November, Tuesday: Read Section 6.3 in J. Rabaey,A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: ADesign Perspective. Prentice-Hall, second edition, 2003.
11 November, Thursday: Homework 3.
56 Robert Dick Digital Integrated Circuits
Special topic: Atomic layer deposition
Katherine Dropiewski, Matt Jansen, and Olga Rouditchenko