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Digital Integrated Digital Integrated Digital Integrated Digital Integrated CircuitsCircuits

D i i S ti lD i i S ti lDesigning SequentialDesigning SequentialLogic CircuitsLogic Circuitsgg

© Digital Integrated Circuits2ndSequential Circuits

Sequential LogicSequential LogicSequential LogicSequential Logic


Naming ConventionsNaming ConventionsNaming ConventionsNaming Conventions

In our text:a latch is level sensitivea latch is level sensitivea register is edge-triggered

There are many different namingThere are many different naming conventions

F i b k ll dFor instance, many books call edge-triggered elements flip-flopsThi l d t f i hThis leads to confusion however


Latch versus RegisterLatch versus RegisterLatch versus RegisterLatch versus RegisterLatch RegisterLatchstores data when clock is low

Registerstores data when clock rises

D Q D Q

clock rises

Clk Clk

Clk Clk

DD D

Q Q


Q Q

LatchesLatchesLatchesLatches


LatchLatch--Based DesignBased DesignLatchLatch--Based DesignBased Design

• N latch is transparentwhen φ = 0

• P latch is transparent when φ = 1

φφ

φ

NLatch Logic P

LatchLatch Latch

Logic


Timing DefinitionsTiming DefinitionsTiming DefinitionsTiming Definitions

CLK

t

CLK

tholdtsu

RegisterD Q

t

D

tc - q

DATASTABLE

CLK

t

Q DATASTABLE


Characterizing TimingCharacterizing TimingCharacterizing TimingCharacterizing Timing


Maximum Clock FrequencyMaximum Clock FrequencyMaximum Clock FrequencyMaximum Clock Frequency

s

φ

FF’

LOGIC Also:

tp,combtcdreg + tcdlogic > thold

tcd: contamination delay = minimum propagation minimum propagation delaytclk-Q + tp,comb + tsetup = T


Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityPositive Feedback: BiPositive Feedback: Bi--StabilityStability

Vo1

Vo1Vo

Vi25Vo

i25Vo1

Vi2


MetaMeta--StabilityStabilityMetaMeta--StabilityStability


Writing into a Static LatchWriting into a Static LatchWriting into a Static LatchWriting into a Static Latch


MuxMux--Based LatchesBased LatchesMuxMux--Based LatchesBased LatchesNegative latch Positi e latchg(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

1

0D

Q 0

1D

Q

0D

CLK

1D

CLK CLK

InClkQClkQ ⋅+⋅= InClkQClkQ ⋅+⋅=


MuxMux--Based LatchBased LatchMuxMux--Based LatchBased Latch


MuxMux--Based LatchBased LatchMuxMux--Based LatchBased Latch


MasterMaster--Slave (EdgeSlave (Edge--Triggered) Triggered) ( g( g gg )gg )RegisterRegister


MasterMaster--Slave RegisterSlave RegisterMasterMaster--Slave RegisterSlave Register


ClkClk--Q DelayQ DelayClkClk--Q DelayQ Delay


Setup TimeSetup TimeSetup TimeSetup Time


Reduced Clock Load Reduced Clock Load MasterMaster--Slave RegisterSlave Register

CLK CLK

D T I

CLK

T

CLK

ID QT1 I 1 T2

I2

I 3

I4CLK CLK

I2 I4


Avoiding Clock OverlapAvoiding Clock OverlapAvoiding Clock OverlapAvoiding Clock OverlapCLK X CLK

AB

D

Q

CLK

(a) Schematic diagramCLK

CLK

(b) Overlapping clock pairs

CLK


Avoiding Clock OverlapAvoiding Clock OverlapAvoiding Clock OverlapAvoiding Clock OverlapCLK X CLK

AB

D

Q

CLK

(a) Schematic diagramCLK

CLK

CLK

CLK

(b) Two-phase non-overlapping clock pairs


Solving leakage problem using Solving leakage problem using multiplemultiple--threshold CMOSthreshold CMOS


CrossCross--Coupled PairsCoupled PairsCrossCross--Coupled PairsCoupled Pairs


CrossCross--Coupled NANDCoupled NANDCrossCross--Coupled NANDCoupled NAND


Sizing IssuesSizing IssuesSizing IssuesSizing IssuesM2 vs. M5+M6 ?M2 vs. M5 M6 ?


Storage MechanismsStorage MechanismsStorage MechanismsStorage Mechanisms


Making a Dynamic Latch PseudoMaking a Dynamic Latch Pseudo--StaticStaticMaking a Dynamic Latch PseudoMaking a Dynamic Latch Pseudo--StaticStatic


More Precise Setup TimeMore Precise Setup TimeMore Precise Setup TimeMore Precise Setup Time


Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)

Clk Q D l

Circuit before clock arrival (Setup 1 case)CN

Inv2TG1

Clk-Q Delay

DQ MD1 SM

Inv1

Inv2

TClk-Q

CP

TSetup-1 Time

ClockDataT

Time

TSetup-1


t=0

Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsCircuit before clock arrival (Setup 1 case)

Clk Q D l

CN

Inv2TG1

Circuit before clock arrival (Setup-1 case)

Clk-Q Delay

DQ MD1 SM

Inv1

Inv2

TClk-QCP

TSetup-1 Time

ClockDataT

Time

TSetup-1


Timet=0

Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsCi it b f l k i l (S t 1 )

Clk Q D l

Circuit before clock arrival (Setup-1 case)CN

Inv2TG1

Clk-Q Delay

DQ MD1 SM

Inv1

Inv2

TClk-Q

CP

TSetup-1 Time

ClockDataT

Time

TSetup-1


et=0


Clk Q Delay

CN

Inv2TG1


Clk-Q Delay

DQ MD1 SM

Inv1

Inv2

TClk-Q

CP

TSetup-1 Time

ClockData

Time

TSetup-1


Timet=0


CN

Inv2TG1


Clk Q Delay

DQ MD1 SM

Inv1

Inv2 Clk-Q DelayTClk-Q

CP

ClockDataTSetup-1 Time

Time

TSetup-1


Timet=0

Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsHold-1 caseHold-1 case

CN

Inv2TG1 Clk-Q Delay

DQ MD1 SM

Inv1

Inv2

CP0

TClk-Q

DataClockTHold-1 Time

Timet 0

THold-1


Timet=0

Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsHold-1 case

Clk-Q Delay

Hold-1 caseCN

Inv2TG1

DQ MD1 SM

Inv1

Inv2

TClk-Q

CP0

THold-1 Time

DataClock

Timet 0

THold-1


Timet=0


Clk-Q Delay

CN

Inv2TG1

Hold-1 case

DQ MD1 SM

Inv1

Inv2

TClk-QCP

0

THold-1 Time

DataClock

Timet 0

THold-1


Timet=0

Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsSetup/Hold Time IllustrationsH ld 1

Clk-Q Delay

CN

Inv2TG1

Hold-1 case

T

DQ MD1 SM

Inv1

Inv2

TClk-Q

CP0

THold-1 Time

Clock Data

Timet 0

THold-1


Timet=0


Clk-Q Delay

CN

Inv2TG1

Hold-1 case

TClk-Q

DQ MD1 SM

Inv1

Inv2

CP0

THold-1 Time

Clock Data

Timet 0

THold-1⇒


Timet=0

Other Latches/Registers: COther Latches/Registers: C22MOSMOSOther Latches/Registers: COther Latches/Registers: C MOSMOSClocked CMOS


Insensitive to ClockInsensitive to Clock--OverlapOverlapInsensitive to ClockInsensitive to Clock--OverlapOverlap

M2

VDD

M6

VDD

M2

VDD

M6

VDD

M40 0X

M8X

D QX

M3

D Q

1

X

M71

M1 M5 M1 M5

(a) (0-0) overlap (b) (1-1) overlap


PipeliningPipeliningPipeliningPipelining


Other Latches/Registers: TSPCOther Latches/Registers: TSPCOther Latches/Registers: TSPCOther Latches/Registers: TSPC


Including Logic in TSPCIncluding Logic in TSPCIncluding Logic in TSPCIncluding Logic in TSPC


TSPC RegisterTSPC RegisterTSPC RegisterTSPC Register


PulsePulse--Triggered LatchesTriggered LatchesA Alt ti A hA Alt ti A hAn Alternative ApproachAn Alternative ApproachWays to design an edge-triggered sequential cell:

Master-Slave Latches

Pulse-Triggered LatchLatches

D Q D QData

D QData

LatchL1 L2 L

D

Clk

Q D

Clk

Q D

Clk

Q

Clk

Clk


Pulsed LatchesPulsed LatchesPulsed LatchesPulsed Latches


Pulsed LatchesPulsed LatchesPulsed LatchesPulsed Latches


Hybrid LatchHybrid Latch--FF TimingFF TimingHybrid LatchHybrid Latch--FF TimingFF Timing


SenseSense--Amplifier Based FlipAmplifier Based Flip--FlopFlopSenseSense--Amplifier Based FlipAmplifier Based Flip--FlopFlop


SenseSense--Amplifier Based FlipAmplifier Based Flip--FlopFlopSenseSense--Amplifier Based FlipAmplifier Based Flip--FlopFlop


LatchLatch--Based PipelineBased PipelineLatchLatch--Based PipelineBased Pipeline


NonNon--Bistable Sequential Circuits─Bistable Sequential Circuits─NonNon Bistable Sequential CircuitsBistable Sequential CircuitsSchmitt TriggerSchmitt Trigger

Vout VOHIn Out

VOL•VTC with hysteresis

•Restores signal slopes

VinVM– VM+

Restores signal slopes


Noise Suppression using Schmitt Noise Suppression using Schmitt pp gpp gTriggerTrigger


CMOS Schmitt TriggerCMOS Schmitt TriggerCMOS Schmitt TriggerCMOS Schmitt Trigger


Schmitt Trigger Sim lated VTCSchmitt Trigger Sim lated VTCSchmitt Trigger Simulated VTCSchmitt Trigger Simulated VTC

2.5 2.5

V

2.0 2.0

VX(V) VM2

VM11.5

1.0 Vx(V) k = 1

1.5

1.0V

0.5

Vk = 2

k = 3

k = 40.5

Vin (V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of the

0.00.0 0.5 1.0 1.5 2.0 2.5

Vin (V)

0.00.0 0.5 1.0 1.5 2.0 2.5


g y y gPMOS device M4. The width is k* 0.5 m.m

CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)


Multivibrator CircuitsMultivibrator CircuitsMultivibrator CircuitsMultivibrator CircuitsS

R

Bistable Multivibratorflip-flop, Schmitt Trigger

S

T

Monostable Multivibratorone-shot

Astable MultivibratorAstable Multivibratoroscillator


TransitionTransition--Triggered MonostableTriggered MonostableTransitionTransition Triggered MonostableTriggered Monostable

DELAY

t

In

Outtd td


Monostable Trigger (RCMonostable Trigger (RC--based)based)Monostable Trigger (RCMonostable Trigger (RC based)based)VDD

InOutA B

R

C (a) Trigger circuit.

In

B VM(b) Waveforms.

Out tt2t1


1

Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)


Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)

VDD

M4

VDD

M6

Schmitt Triggerrestores signal slopes

In

M1

M2

I I

M3M5

Vcontr Current starved inverter

Iref Iref

4

6

nsec

)

0.5 1.5 2.5Vcontr (V)

0.0

2

t pH

L (n

propagation delay as a functionof control voltage


Differential Delay Element and VCODifferential Delay Element and VCO

vV V

in2v 1

v 2

v 3

v 4

Vo2 V o1

in1

two stage VCO

Vctrl

delay cell

1 5

2.0

2.5

3.0V1 V2 V 3 V4

0.0

0.5

1.0

1.5

simulated waveforms of 2-stage VCO

0.52 0.51.5

time (ns)2.5 3.5


simulated waveforms of 2 stage VCO

Digital Integrated Circuits - bandi.cbnu.ac.kr

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