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Digital IC Introduction

Digital Integrated Circuits A Design Perspective

Chapter 5 Arithmetic Circuits � 

1

Digital IC

A Generic Digital Processor

2

MEMORY

DATAPATH

CONTROL

INPUT-OUTPUT

Digital IC

Bit-Sliced Datapath

3

Adder stage 1

Wiring

Adder stage 2

Wiring

Adder stage 3

Bit slice 0

Bit slice 2

Bit slice 1

Bit slice 63

Sum Select

Shifter

Multiplexers

Loopback Bus

From register files / Cache / Bypass

To register files / CacheLoopback B

us

Loopback Bus

Digital IC

outline � •  Adder •  Datapath functional unit

•  Comparators •  Shifters •  Multi-input Adders

•  Multipliers

4

Digital IC Introduction

Adders Multitudes of contrivances were designed,and almost endless drawings made, for the purpose of economizing the time and simplifying the mechanism of carriage

__charles babbage, on difference engine No.1,1864

5

Digital IC

Outline •  Single-bit Addition •  Carry-Ripple Adder •  Carry-Skip Adder •  Carry-Lookahead Adder •  Carry-Select Adder •  Carry-Increment Adder •  Tree Adder

Slide 6

Digital IC

PGK •  For a full adder, define what happens to carries

•  Generate: Cout = 1 independent of C •  G =

•  Propagate: Cout = C •  P =

•  Kill: Cout = 0 independent of C •  K =

Slide 7

Digital IC

PGK •  For a full adder, define what happens to carries

•  Generate: Cout = 1 independent of C • G = A • B

•  Propagate: Cout = C • P = A ⊕ B

•  Kill: Cout = 0 independent of C • K = ~A • ~B

•  Note that we will be sometimes using an alternate definition for (only for carry)

Slide 8

Propagate (P) = A + B

Digital IC

Single-Bit Addition Half Adder Full Adder

Slide 9

A B Cout S 0 0 0 1 1 0 1 1

A B C Cout S 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

A B

S

Cout

A B

C

S

Coutout

S A BC A B

= ⊕

= g out ( , , )S A B C

C MAJ A B C= ⊕ ⊕

=

)C,B,A(MAJ=C)B+A(+BA=

C)B+A(+AB=CC⊕P=C⊕B⊕A=

ABC+CBA+CBA+CBA=S

out

Digital IC

Single-Bit Addition Half Adder Full Adder

Slide 10

A B Cout S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0

A B C Cout S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

A B

S

CoutA B

C

S

Coutout

S A BC A B

= ⊕

= g out ( , , )S A B C

C MAJ A B C= ⊕ ⊕

=

delete

propagate

generate )C,B,A(MAJ=C)B+A(+BA=

C)B+A(+AB=CC⊕P=C⊕B⊕A=

ABC+CBA+CBA+CBA=S

out

Digital IC

Full Adder Design I •  implementation from eqns

Slide 11

out ( , , )S A B C

C MAJ A B C= ⊕ ⊕

=

ABC

S

Cout

MAJ

ABC

A

B BB

A

CS

C

CC

B BB

A A

A B

C

B

A

CBA A B C

CoutC

A

A

BB

Fewer than mentioned above because of sharing some transistors for XOR gate

)C,B,A(MAJ=C)B+A(+BA=

C)B+A(+AB=CC⊕P=C⊕B⊕A=

ABC+CBA+CBA+CBA=S

out

Digital IC

Full Adder Design II •  Factor S in terms of Cout

S = ABC + (A + B + C)(~Cout) Cout=MAJ(A,B,C)

•  Critical path is usually C to Cout in ripple adder

Slide 12

Co = AB+BCi + ACi

S = ABCi +Co(A+B+Ci )

)C,B,A(MAJ=C)B+A(+BA=

C)B+A(+AB=CC⊕P=C⊕B⊕A=

ABC+CBA+CBA+CBA=S

out

Digital IC

Full Adder Design II

13

A B

B

A

Ci

Ci A

X

VDD

VDD

A B

Ci BA

B VDD

A

B

Ci

Ci

A

B

A CiB

Co

VDD

S

Complimentary Static CMOS Full Adder__28 Transistors

)( ioi

iio

CBACABCS

ACBCABC

+++=

++=

Digital IC

Mirror Adder-Stick Diagram

14

CiA B

VDD

GND

B

Co

A Ci Co Ci A B

S

)( ioi

iio

CBACABCS

ACBCABC

+++=

++=

Digital IC

The Mirror Adder •  The NMOS and PMOS chains symmetrical. A maximum of

two series transistors arranged in the carry-generation •  the most critical issue is the minimization of the

capacitance at node Co. The reduction of the diffusion capacitances is particularly important.

•  The capacitance at node Co is composed of 4 diffusion capacitances, 2 internal gate capacitances, and 6 gate capacitances in the connecting adder cell .

•  The transistors connected to Ci are closest to the output. •  Only the transistors in the carry stage have to be optimized

for optimal speed. All transistors in the sum stage can be minimal size.

15

Digital IC

Inversion Property

16

A B

S

CoCi FA

A B

S

CoCi FA

S A B Ci, ,( ) S A B Ci

, ,( )=

Co A B Ci, ,( ) Co A B Ci

, ,( )=

Digital IC

Minimize Critical Path by Reducing Inverting Stages

17

Exploit Inversion Property

A3

FA FA FA

Even cell Odd cell

FA

A0 B0

S0

A1 B1

S1

A2 B2

S2

B3

S3

Ci,0 Co,0 Co,1 Co,3Co,2

Digital IC Slide 18

Transmission Gate

S

S

D0

D1YS

Mux

B

B

A

F = AB

0

AND

B

B

A

F = A+~B

1

Digital IC 19

Pass-Transistor Based

AM2

M1B

S

S

S F

VDD

A

B

F

B

A

B

B M1

M2

M3/M4

Multiplexer XOR

Digital IC 20

Complementary Pass Transistor Logic

A

B

A

B

B B B B

A

B

A

B

F=AB

F = AB

F=A+B

F = A+B

B B

A

A

A

A

F=A @B

F = A @B

OR/NOR EXOR/NEXOR AND/NAND

F

F

Pass-Transistor Network

Pass-Transistor Network

A A B B

A A B B

Inverse

(a)

(b)

Digital IC

A

C

S

S

B

B

C

C

C

B

B Cout

Cout

C

C

C

C

B

B

B

B

B

B

B

B

A

A

A

Full Adder Design III •  Complementary Pass Transistor Logic (CPL)

•  Slightly faster, but more area

Slide 21

)( ioi

iio

CBACABCS

ACBCABC

+++=

++=

A@B ~(A@B) ~(A@B@C)

~A~B

~(AB)

(~A~B)C+~(AB)~C

Digital IC

Full Adder Design IV � 

22

A@B

CBABAA

CBABAAAABCBAABC

CPCBAABCCBACBACBAS

out

)⊕()⊕(

)⊕()⊕(

⊕⊕⊕

+=

++=+=

==

+++=

Digital IC

Manchester Carry Chain

23

G2

φ

C3

G3Ci,0

P0

G1

VDD

φ

G0

P1 P2 P3

C3C2C1C0

Digital IC

Generate / Propagate •  Equations often factored into G and P •  Generate and propagate for groups spanning i:j

•  Base case

•  Sum:

Slide 24

: : : 1:

: : 1:

i j i k i k k j

i j i k k j

G G P GP P P

−

−

= +

=

gg

:

:

i i i i i

i i i i i

G G A BP P A B

≡ =

≡ = ⊕

g

0:00:00inGCP==

0:0 0

0:0 0 0inG G C

P P≡ =

≡ =

1:0i i iS P G −= ⊕

Digital IC

PG Logic

Slide 25

S1

B1A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4 Cin

G0 P0

1: Bitwise PG logic

2: Group PG logic

3: Sum logicC0C1C2C3

Cout

C4

1:0i i iS P G −= ⊕

:

:

i i i i i

i i i i i

G G A BP P A B

≡ =

≡ = ⊕

g

0:0 0

0:0 0 0inG G C

P P≡ =

≡ =

: : : 1:

: : 1:

i j i k i k k j

i j i k k j

G G P GP P P

−

−

= +

=

gg

Digital IC

Carry-Ripple Revisited

Slide 26

:0 1:0 i i i iG G P G −= + g

S1

B1A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4 Cin

G0 P0

C0C1C2C3

Cout

C4

Digital IC

Carry-Ripple PG Diagram

Slide 27

Delay

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

Bit Position

ripple xor( 1)pg AOt t N t t= + − +

Digital IC

PG Diagram Notation

i:j

i:j

i:k k-1:j

i:j

i:k k-1:j

i:j

Gi:k

Pk-1:j

Gk-1:j

Gi:j

Pi:j

Pi:k

Gi:k

Gk-1:j

Gi:j Gi:j

Pi:j

Gi:j

Pi:j

Pi:k

Black cell Gray cell Buffer

Slide 28

Digital IC

Higher-Valency Cells

i:j

i:k k-1:l l-1:m m-1:j

Gi:k

Gk-1:l

Gl-1:m

Gm-1:j

Gi:j

Pi:j

Pi:k

Pk-1:l

Pl-1:m

Pm-1:j

Slide 29

Digital IC

Manchester Carry Chain � 

30

))CP+G(P+G(P+G=G=C)CP+G(P+G=G=C

CP+G=G=CC=G=C

01122330:33

011220:22

0110:11

00:00

Digital IC

Manchester Carry Chain � 

31