Digital Integrated Circuits (83-313) Semester B, 2015-16 Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1 Lecture 9: Multipliers
Digital Integrated Circuits
(83-313)
Semester B, 2015-16
Lecturer: Adam Teman
TAs: Itamar Levi, Robert Giterman 1
Lecture 9:
Multipliers
Binary Multiplication
4
multiplicand
multiplier
partial
product
array
double precision product
N
2N
N can be formed in parallel
Array Multiplier
6
Y0
Y1
X3 X2 X1 X0
X3
HA
X2
FA
X1
FA
X0
HA
Y2X3
FA
X2
FA
X1
FA
X0
HA
Z1
Z3Z6Z7 Z5 Z4
Y3X3
FA
X2
FA
X1
FA
X0
HA
Z2
Z0
Carry-Save Multiplier
8
HA HA HA HA
FAFAFAHA
FAHA FA FA
FAHA FA HA
Vector Merging Adder
1 1mult carry AND merget N t N t t
Multiplier Floorplan
9
SCSCSCSC
SCSCSCSC
SCSCSCSC
SC
SC
SC
SC
Z0
Z1
Z2
Z3Z4Z5Z6Z7
X0X1X2X3
Y1
Y2
Y3
Y0
Vector Merging Cell
HA Multiplier Cell
FA Multiplier Cell
X and Y signals are broadcasted
through the complete array.
( )
Booth Recoding
10
Multiplying by ‘0’ is redundant.
Can we reduce the number of partial products?
Based on the observation that
We can turn sequences of 1’s into sequences of 0’s
For example: 0111=1000-0001
So we can introduce a ‘-1’ bit and recode the multiplier:
For example, the number 56
1
0
2 2 1n
i n
i
Radix-2 Booth Recoding
11
Parse multiplier from left to right
For each change from 0 to 1, encode a ‘1’
For each change from 1 to 0, encode a ‘-1’
For bit 0, assume bit i=-1 is a 0
Example: 0011 0111 0011
Modified (Radix-4) Booth Recoding
12
Radix-2 Booth Recoding doesn’t work for parallel hardware implementations, since:
A worst case (010101010101010) doesn’t reduce the number of partial products.
Variable length recoders (according to the length of ‘1’ strings) cannot be implemented efficiently.
Instead, just assume a constant length recoder.
First apply standard booth recoding.
Next encode each pair of bits:
This can be summarized in a truth table:
Partial Product Selection Table
Multiplier Bits Recorded Bits
000 0
001 + Multiplicand
010 + Multiplicand
011 +2 × Multiplicand
100 -2 × multiplicand
101 - Multiplicand
110 - Multiplicand
111 0
Modified (Radix-4) Booth Recoding
13
For example, let’s take our previous example:
0011 0111 0011 = 01 0-1 10 0-1 01 0-1
We could have done this by using the table:
0 0 1 1 0 1 1 1 0 0 1 1
To implement this we need pretty simple hardware:
Mi
yj
Xi
yj-1
2Xi
PPij
Booth
Selector
Booth
Encoder
x2i+1
x2i
x2i-1
Tree Multipliers
14
Can we further reduce the multiplier delay
by employing logarithmic (tree) structures?
PP1PP2 PP3PP4PP5
+
CLA
Result
PP6PP7PP8
+ +
+ +
PP0
+
+
Wallace-Tree Multiplier
15
FA
FA
FA
FA
y0 y1 y2
y3
y4
y5
S
Ci-1
Ci-1
Ci-1
Ci
Ci
Ci
FA
y0 y1 y2
FA
y3 y4 y5
FA
FA
CC S
Ci-1
Ci-1
Ci-1
Ci
Ci
Ci
Wallace-Tree Multiplier
17
6 5 4 3 2 1 0 6 5 4 3 2 1 0
Partial products First stage
Bit position
6 5 4 3 2 1 0 6 5 4 3 2 1 0
Second stage Final adder
FA HA
(a) (b)
(c) (d)
HA