Digital Integrated Circuit Design The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB Via Golgi 40, Milano 1.

Digital Integrated Circuit Design The Devices

The DevicesThe Devices

Digital Integrated Circuit Digital Integrated Circuit DesignDesignAndrea BonfantiDEIBVia Golgi 40, Milano

1


Aims of this chapterAims of this chapter

Present intuitive understanding of device operation

Introduction of basic device equations Introduction of models for manual analysis Analysis of secondary and deep-sub-micron

effects Future trends

2


The DiodeThe Diode

n

p

p

n

B A SiO2Al

A

B

Al

A

B

Cross-section of pn-junction in an IC process

One-dimensionalrepresentation diode symbol

Mostly occurring as parasitic element in Digital ICs

3


Depletion RegionDepletion Regionhole diffusion

electron diffusion

p n

hole driftelectron drift

ChargeDensity

Distancex+

-

ElectricalxField

x

PotentialV

W2-W1

(a) Current flow.

(b) Charge density.

(c) Electric field.

(d) Electrostaticpotential.

4


Diode CurrentDiode Current

5


Forward BiasForward Bias

x

pn0

np0

-W1 W20p n

(W2)

n-regionp-region

Lp

diffusion

Typically avoided in Digital ICs6


Reverse BiasReverse Bias

x

pn0

np0

-W1 W20n-regionp-region

diffusion

The Dominant Operation Mode7


Models for Manual AnalysisModels for Manual Analysis

VD

ID = IS(eVD/T – 1)+

–

VD

+

–

+

–VDon

ID

(a) Ideal diode model (b) First-order diode model

8


Junction CapacitanceJunction Capacitance

9


Diffusion CapacitanceDiffusion Capacitance

10


Secondary EffectsSecondary Effects

–25.0 –15.0 –5.0 5.0

VD (V)

–0.1

I D (A

)

0.1

0

0

Avalanche Breakdown

11


Diode ModelDiode Model

ID

RS

CD

+

-

VD

12


SPICE ParametersSPICE Parameters

13


What is a Transistor?What is a Transistor?

VGS VT

RonS D

A Switch!

|VGS|

An MOS Transistor

14


The MOS TransistorThe MOS Transistor

Polysilicon Aluminum

15


MOS Transistors -MOS Transistors -Types and SymbolsTypes and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact

16


Threshold Voltage: ConceptThreshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel

17


The Threshold VoltageThe Threshold Voltage

18


The Body EffectThe Body Effect

-2.5 -2 -1.5 -1 -0.5 00.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VBS

(V)

VT (

V)

19


Current-Voltage RelationsCurrent-Voltage RelationsA good ol’ transistorA good ol’ transistor

QuadraticRelationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

20


Transistor in LinearTransistor in Linear

n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

MOS transistor and its bias conditions21


Transistor in SaturationTransistor in Saturation

n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-

Pinch-off

22


Current-Voltage RelationsCurrent-Voltage RelationsLong-Channel DeviceLong-Channel Device

23


A model for manual analysisA model for manual analysis

24


Current-Voltage RelationsCurrent-Voltage RelationsThe Deep-Submicron EraThe Deep-Submicron Era

LinearRelationship

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation

25


Velocity SaturationVelocity Saturation

(V/µm)c = 1.5

n

(m/s

)

sat = 105

Constant mobility (slope = µ)

Constant velocity

26


PerspectivePerspective

IDLong-channel device

Short-channel device

VDSVDSAT VGS - VT

VGS = VDD

27


IIDD versus V versus VGSGS

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VGS (V)

I D (

A)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VGS (V)

I D (

A)

quadratic

quadratic

linear

Long Channel Short Channel

28


IIDD versus V versus VDSDS

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

ResistiveSaturation

VDS = VGS - VT

Long Channel Short Channel

29


A unified modelA unified modelfor manual analysisfor manual analysis

S D

G

B

30


Simple Model versus SPICE Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS

(V)

I D (

A)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

31


A PMOS TransistorA PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

-0.8

-0.6

-0.4

-0.2

0x 10

-4

VDS (V)

I D (

A)

Assume all variablesnegative!

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V

32


Transistor Model Transistor Model for Manual Analysisfor Manual Analysis

33


The Transistor as a SwitchThe Transistor as a Switch

VGS VT

RonS D

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

34



0.5 1 1.5 2 2.50

1

2

3

4

5

6

7x 10

5

VDD

(V)

Req

(O

hm)

35



36


MOS CapacitancesMOS CapacitancesDynamic BehaviorDynamic Behavior

37


Dynamic Behavior of MOS TransistorDynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB

38


The Gate CapacitanceThe Gate Capacitance

tox

n+ n+

Cross section

L

Gate oxide

xd xd

L d

Polysilicon gate

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W

39


Gate CapacitanceGate Capacitance

S D

G

CGC

S D

G

CGC

S D

G

CGC

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

40

<


Gate CapacitanceGate Capacitance

WLCox

WLCox

2

2WLCox

3

CGC

CGCS

VDS /(VGS-VT)

CGCD

0 1

CGC

CGCS = CGCDCGC B

WLCox

WLCox

2

VGS

Capacitance as a function of VGS(with VDS = 0)

Capacitance as a function of the degree of saturation

41

0V


Measuring the Gate CapMeasuring the Gate Cap

2 1.52 12 0.5 0

3

4

5

6

7

8

9

103 102 16

2

VGS (V)

VGS

Gate

Ca

paci

tan

ce (

F)

0.5 1 1.5 22 2

I

42


Diffusion CapacitanceDiffusion Capacitance

Bottom

Side wall

Side wallChannel

SourceND

Channel-stop implant NA1

SubstrateNA

W

xj

LS

43


Junction CapacitanceJunction Capacitance

44


Linearizing the Junction CapacitanceLinearizing the Junction Capacitance

Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest

45


Capacitances in 0.25 Capacitances in 0.25 m CMOS m CMOS processprocess

46


The Sub-Micron MOS TransistorThe Sub-Micron MOS Transistor

Threshold Variations Subthreshold Conduction Parasitic Resistances

47


Threshold VariationsThreshold Variations

VT

L

Long-channel threshold Low VDS threshold

Threshold as a function of the length (for low VDS)

Drain-induced barrier lowering (for low L)

VDS

VT

48


Sub-Threshold ConductionSub-Threshold Conduction

0 0.5 1 1.5 2 2.510

-12

10-10

10-8

10-6

10-4

10-2

VGS (V)

I D (

A)

VT

Linear

Exponential

Quadratic

Typical values for S:60 .. 100 mV/decade

The Slope Factor

ox

DnkT

qV

D C

CneII

GS

1 ,~ 0

S is VGS for ID2/ID1 =10

49


Sub-Threshold Sub-Threshold IIDD vs vs VVGSGS

VDS from 0 to 0.5V

kT

qV

nkT

qV

D

DSGS

eeII 10

50


Sub-Threshold Sub-Threshold IIDD vs vs VVDSDS

DSkT

qV

nkT

qV

D VeeIIDSGS

110

VGS from 0 to 0.3V

51


Summary of MOSFET Operating Summary of MOSFET Operating RegionsRegions

Strong Inversion VGS > VT

Linear (Resistive) VDS < VDSAT

Saturated (Constant Current) VDS VDSAT

Weak Inversion (Sub-Threshold) VGS VT

Exponential in VGS with linear VDS dependence

52


Parasitic ResistancesParasitic Resistances

W

LD

Drain

Draincontact

Polysilicon gate

DS

G

RS RD

VGS,eff

53


Latch-upLatch-up

54

Equivalent model


Future PerspectivesFuture Perspectives

25 nm FINFET MOS transistor

55

Digital Integrated Circuit Design The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB Via Golgi 40, Milano 1.

Documents