Digital Integrated Circuit Design I ECE 425/525 Chapter 3web.cecs.pdx.edu/~ecex25/pdf/chapter3.pdf · 2014-10-27 · Digital Integrated Circuit Design I ECE 425/525 Chapter 3 Professor

Digital Integrated Circuit Design IECE 425/525

Chapter 3

Professor R. Daasch

Depar tment of Electrical and Computer EngineeringPortland State UniversityPortland, OR 97207-0751([email protected])

http://ece .pdx.edu/ ~ecex25

©R.Daasch, Por tland State University 1 October 2014

Chapter 3Fabr ication of FET circuits is a complex enter prise

A circuit designer relates to the fabr ication process indirectly

The device electrical character istics are determined by thefabr ication “recipe” — the device models such SPICE orother simulation

The device physical character istics are determined by theresolution of the lithography — the design rules, extractionrules

The circuit perfor mance combines electrical and physicalcharacter istics with design decisions

Substrates — in MOS doped “n” or “p” type Silicon (ChemicalSymbol Si)

NFET is assembled in, on and over p-type Si

PFET is assembled in, on and over n-type Si


Chapter 3CMOS requires both NFET and PFET devices hence n-type Si and p-type Si is needed

Well — is a region of the opposite type as the substrate

Example: A n-type substrate (doped with phosphorus (P))is compensation doped p-type (doped with boron (B))

Yields a p-type region on the n-type substrate for theconstr uction of one or (typically) more NFETs

Process flow steps

Processing steps for 0. 18µm range from 200-400

The FET requires 6-10 layers and each layer of metalinterconnect 2 or 3 additional layers

Metal interconnect layers range from four to seven

Most steps require well-controlled chemistry, optics, andmechanical handling.


Chapter 3Substrate doping concentrations are less than1015atoms/cm3

Wafer back-grinding (to reduce the thickness of the wafer sothe resulting chip can be put into a thin device like a smar t-card or PCMCIA card.)

Processing steps ⟨http://en.wikipedia.org/wiki/Semiconductor_device_fabrication#List_of_steps⟩in modern electronic device manufacture (not necessarily aspecific order) include wafer processing, die processing,package processing, and testing

Wafer processing

Wet cleans

Photolithography

Ion implantation (in which dopants are embedded in thewafer creating regions of increased (or decreased)conductivity)


Chapter 3Dr y etching

Wet etching

Plasma ashing

Ther mal treatments

• Rapid thermal anneal

• Fur nace anneals

• Ther mal oxidation

Chemical vapor deposition (CVD)

Physical vapor deposition (PVD)

Molecular beam epitaxy (MBE)

Electro-chemical Deposition (ECD). See Electro-plating

Chemical-mechanical planarization (CMP)


Chapter 3Wafer testing (where the electrical perfor mance is ver ified)

Die preparation

Wafer mounting

Die cutting

IC packaging

Die attachment

IC Bonding

• Wire bonding

• Flip chip

• Tab bonding

IC encapsulation

• Baking


Chapter 3• Plating

• Laser-mar king

• Trim and for m

IC testing

Patter ning — transfer image from mask to current surface ofsemiconductor wafer

Typically photolithography

Light sensitive mater ial called photoresist changeschemically after exposure to light

Patter n is obtained by removing exposed areas (positive)or unexposed areas (negative)

Create n-well regions — What is the substrate in this case?

Grow oxide — SiO2 silicon dioxide is the heart and soul of SiMOSFET technology


Chapter 3Field Oxide isolates wires and conductors

• Field-Ox approximately 1000 angstroms thick

Gate Oxide isolate controlling terminal (gate) fromconducting channel

• Gate-Ox is approximately 10 angstroms thick

Deposit and Patter n polysilicon — polysilicon replaced theor iginal metal (Al) for the gate

An amorphous crystal can be patterned more preciselythan a metal

Doped to yield a conductor with low resistivity

Polysilicon patterning is so-called self-aligned

Implant transistor terminals, substrate and well contacts —each source or drain terminal for ms a rev ersed biased pndiode


Chapter 3Open contact holes (windows) and deposit and pattern metal— signal conductors are an alloy of mostly Al and Cu and,more recently Cu

Each technology generation requires special structures

Polysilicon

• Self-aligned gate - introduced long ago

• Grow gate oxide with the sum of the both N active, Pactive and gate masks

• Deposit polysilicon (gate electrode)

• Patter n all polysilicon

• Etch (remove) gate oxide not patterned by polysilicon(active mask)

• Implant each active area separately


Chapter 3• Silicide for mation to lower the intrinsic resistance of

polysilicon

• Local interconnects for m a ohmic connection betweenactive and polysilicon without a metal contact

Drain engineering

• Goal is to improve character istics of MOS transistorswith ultra-shor t channel.

• Lightly-doped drain - limit oxide damage from hotelectron effects

• Drain engineering - modifications of the drain andchannel region adjacent to drain

• Low er concentrations (1018−20)

• Shallow and near the gate-oxide boundary


Chapter 3

Cross section of FET. Note the active doping var iation isseveral orders of magnitude lower near channel


Chapter 3A completed wafer is finally passivated (a glass covering)

Contact holes through passivation allow for contact to thepackage and the outside wor ld

Testing is on-going during processing steps, at the wafer-level, package and in the field.

Pr inting the pattern of the physical layout is imperfect

Defects on the raw, original wafer interfere with printing

Each mask has to have precise focus to transfer thepatter n to the wafer

• Mask is the size of a single die to as many as dozen diebut nev er entire wafer

• Focus at wafer edge less reliable than the center

Resists and material removed can leave unwantedpar ticles on wafer


Chapter 3Implant, deposition and other addition steps can leavetrace materials

After each major step (polysilicon, metal1, metal2...) thewafer is replanar ized


Chapter 3 ��

Photo from IBM


Chapter 3 ��

Cross section MOSFET, Photo from LSI Logic


Chapter 3 ��

Pinhole in MOSFET gate oxide, Photo from LSI Logic


Chapter 3 ��

Metal bridge, Photo from LSI Logic


Chapter 3 ��

No channel junction in MOSFET, Photo from LSILogic


Chapter 3Physical design defines the patterns to be transferred duringfabr ication

Physical design is largely controlled by CAD tools

Each transistor, the interconnect wires linking them, thepower distr ibution, input and output pads are all specifiedon a 2-dimensional grid of coordinates

Layout Design Rules are also known as Physical DesignRules and as just Design Rules

Layout Design Rules — the contract between the intendedcircuit and fabr ication

Any semiconductor technology CMOS, Bipolar etc. havedesign rules

Each “technology node” such as 0. 25µm versus 0. 18µmwill have different design rules


Chapter 3Design Rules evolve as the processing for a technologymatures

Physical Design Rules are the result of what can bephysically patterned on the wafer and electricalconsiderations such field strength, capacitive coupling andthe like

In some cases two sets of design rules are specified; oneset for physical limitations of the fabr ication and a secondset detailing the electrical limitations

Design rules for both physical and electrical propertiesspecified in physical dimensions

Scaling a technologies physical dimensions by a constantfactor is one path from technology node to technology node

In this situation it is common to define design rules on adimensionless grid called the lambda grid (λ)


Chapter 3Constant scaling of physical design rules wor ks well atlarger dimensions (ie 0. 8µm and above)

At smaller dimensions a single scaling factor the physicaldesign rules may be ver y conser vative → potentialsignificant perfor mance loss


Chapter 3

Simulation

Circuit Topo

Est. Parasitics

Size FETs

Prelim Layout

Mask Layout

DRC

Extraction

Opt

imiz

atio

n

Specifications

Design flow at right combines physical andcircuit design layers

Physical design limited by the geometricdesign rules

Circuit design uses simulation models of activeand passive devices

Optimization for circuit design includes; power,area, delay, input/output load

Optimization may force changes at topologyentr y point


Chapter 3

��

��

��

��

��

Polysilicon

ContactCut

ActiveActive

Extension

Active Extension

WidthActive

PolysiliconLength

Separation

Design rule types

Width — minimum pattern feature of active lay er

Length — minimum pattern feature of a polysilicon gate (ietransistor)


Chapter 3Separation — minimum distance between two electr icallydifferent nodes on same layer

— minimum distance between two different layers

Extension and Overhang — minimum distance that onelayer must “cover” another

Ever y layer such as metal 1, metal 2, ... metal N, polysilicon,contacts, vias etc. has design rules for inter-layer physicalrestr ictions and intra-layer restr ictions

MOSIS design rules used in class are simplified

Scalable λ rules

Conser vative to limit the number of conditions to consider

Complete description located athttp://www.mosis.edu/Technical/Designr ules/scmos/


Chapter 3 ��

Mosis design rules for metal 1

Rule Description λ7.1 Minimum width 37.2 Minimum spacing 27.3 Minimum overlap of any contact 17.4 Minimum spacing when either metal line is wider than 10λ 4


Chapter 3 ��

Mosis design rules for p-type and n-type active

Rule Description λ2.1 Minimum width 32.2 Minimum spacing 32.3 Source/Drain active to well edge 52.4 Substrate/well contact active to well edge 32.5 Minimum spacing between non-abutting active 4


Chapter 3 ��

Mosis design rules for vias

Rule Description λ8.1 Exact size 2x28.2 Minimum via 1 spacing 38.3 Minimum overlap by metal1 18.4 Minimum spacing to contact 28.5 Minimum spacing to poly or active edge 2


Chapter 3Design rules are derived for correct by constr uction

Via rule 8.1 result in a reasonable guarantee (defects pertr illion) that every via will be manufactured correctly

Metal and active rules 2.1 and 7.1 limit the minimumfeature size of a mater ial

Other design rules address reliability of final circuits

Antenna rules limit process induced damage of gateoxides

• Polysilicon and metal collect charge during reactive ionetch

• Connected to gate oxide the collected charge developspotentials for significant tunneling current through thethin oxide

Time Dependent Dielectric Breakdown (TDDB) reliabilityrequirements limit wire length connected gate oxide


Chapter 3• Metal1 signal distribution structure then a "cut and link"

method using shorter lengths of metal1 and metal2

Resoultion enhancement techniques

Eventually resolution enhancement flows “upstream” intodesign space A Designer’s Guide to SubresolutionLithography: Enabling the Impossible to Get to the 14-nmNode ⟨http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6491444⟩

Area fill — add dummy mater ial in spaces for each layer tofor a more unifor m density

Source light wavelengths longer than image feature sizeare poorly reproduced

• Control focus etc. insufficient to create sharp images

• Optical proximty correction modifies design mask shapesto shapes which sharpen image on wafer


Chapter 3• Off-axis imaging opens the angle of the light source to

the wafer

• double pattern/exposure techniques separate one layerinto several masks

No process produces a perfect result

All physical measurements of process layers are distributions

Thickness of gate oxide, implants change VT

Metal thickness, vias, contacts change wire resistances

Typical distributions are Unifor m(), Nor mal() and Lognormal()

The effect of the var iation is no two transistors source/sink thesame current

Compensate for the var iation by designing a var iationtolerance


Chapter 3Design Margins simulate or test devices under multipleconditions to reveal design sensitivity

Design corner on transistors (fast, nominal, slow)

Chip voltages 1. 1VDD , VDD , 0. 9VDD

Chip (junction) temperature 0oC , 75oC , 125oC ,

Variation tracking is an additional step to design to furtherreduce effect of processing

Delay tracking uses dummy copies of timing critical paths

Device matching with layout techniques such as using 2parallel transistors instead of twice the width


Digital Integrated Circuit Design I ECE 425/525 Chapter 3web.cecs.pdx.edu/~ecex25/pdf/chapter3.pdf · 2014-10-27 · Digital Integrated Circuit Design I ECE 425/525 Chapter 3 Professor

Documents