EXP. NO: 1 STUDY OF LOGIC GATES DATE : AIM: To study about logic gates and verify their truth tables. APPARATUS REQUIRED: THEORY: Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates. Basic gates form these gates. AND GATE: SL No. COMPONENT SPECIFICATION QTY 1. AND GATE IC 7408 1 2. OR GATE IC 7432 1 3. NOT GATE IC 7404 1 4. NAND GATE 2 I/P IC 7400 1 5. NOR GATE IC 7402 1 6. X-OR GATE IC 7486 1 7. NAND GATE 3 I/P IC 7410 1 8. IC TRAINER KIT - 1 9. PATCH CORD - 14
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EXP. NO: 1STUDY OF LOGIC GATES
DATE :
AIM:
To study about logic gates and verify their truth tables.
APPARATUS REQUIRED:
THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate has
one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs
is low.
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The
output is high when any one of the inputs is high. The output is low level when both the inputs
are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are
low and any one of the input is low .The output is low level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
The output is low when one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.
2Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
AND GATE: SYMBOL: PIN DIAGRAM:
OR GATE:
3Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
NOT GATE: SYMBOL: PIN DIAGRAM:
X-OR GATE : SYMBOL : PIN DIAGRAM :
2-INPUT NAND GATE:
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SYMBOL: PIN DIAGRAM:
3-INPUT NAND GATE :
NOR GATE:
5Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
6Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
PROCEDURE:
a. Give connections as per the circuit diagramb. Inputs are given to the circuit making high ‘1’ i.e. +5 V or + Vcc supply to the
14th pin and for low ‘0’ i.e. GND to the 7th pin of the gate ICc. Depending upon the truth table, if the LED glow it represent 1 and else it
represents ‘0’d. Verify the truth table as given e. Repeat the procedure steps for different gates.
RESULT: Thus the truth tables for logic gates are verified using IC trainer kit.
7Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
EXP. NO: 2 DESIGN AND IMPLEMENTATION HALF ADDER AND
FULL ADDER.DATE:
AIM: To construct half and full adder circuits and verify the truth table
APPARATUS REQUIRED:
S.NO Particular Name SPECIFICATION QUANTITY
1234
Digital IC trainer kitIC7432 IC7408, IC7486Connecting Wires
----QUAD QUAD
11
1 each
CIRCUIT DIAGRAM:
HALF – ADDER:
IC 7486 A 1 3 SUM B 2 S = A (+)B
IC 7408 1 CARRY 3 Cr = A . B 2
8Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
TRUTH TABLE
A B SUM ( S)
CARRY ( Cr )
0 0 1 1
0 1 0 1
0 1 1 0
0 0 0 1
K-Map for SUM: K-Map for CARRY:
SUM = A’B + AB’ CARRY = AB
9Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
10Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
K-Map for SUM:
SUM = A’B’C + A’BC’ + ABC’ + ABC
CARRY = AB + BC + AC
TRUTH TABLE
A B C S Cr 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
0 0 0 1 0 1 1 1
11Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
PROCEDURE:
1. Give connections as per the circuit diagram
2. Inputs are given to the circuit making high ‘1’ i.e. +5 V or
+ Vcc supply to the 14th pin and for low ‘0’ i.e. GND to the 7th
pin of the gate IC
3. Depending upon the truth table, if the LED glow it represent 1 and else it represents ‘0’
4. Verify the truth table as given for half adder
5. Repeat the procedure steps for full adder circuit
RESULT:
The half and full adder circuits are constructed and verified.
12Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
EXP. NO: 3DESIGN AND IMPLEMENTATION OF SUBTRACTORS
USING LOGIC GATESDATE:
AIM:
To construct half and full subtractor circuits and verify the truth table
APPARATUS REQUIRED:
S.NO Particular Name SPECIFICATION QUANTITY
1 2 3 4 5 6
Digital IC trainer kitIC7404IC7432 IC7408IC7486Connecting Wires
---- 11 each1 each1 each1 each
CIRCUIT DIAGRAM:
13Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
TRUTH TABLE:
Half Subtractor
FULL SUBTRACTOR:
14Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
X Y Diff Borr0011
0101
0110
0100
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
TRUTH TABLE:
15Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
A B C Diff Borro00001111
00110011
01010101
01101001
0111000 1
PROCEDURE: 1. Give connections as per the circuit diagram
2. Inputs are given to the circuit making high ‘1’ i.e. +5 V or + Vcc supply to the 14th
pin and for low ‘0’ i.e. GND to the 7th pin of the gate IC
3. Depending upon the truth table, if the LED glow it represent 1 and else it represents
‘0’
4. Verify the truth table as given for half subtractor
5. Repeat the procedure steps for full subtractor circuits
RESULT:
The half and full subtractor circuits are constructed and truth table was verified
16Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
EXP. NO: 4BINARY TO GRAY - CODE CONVERTER
DATE:AIM:
To Construct and Verify the Truth Table of Binary to Gray Code Converter.
APPARATUS REQUIRED:
S.NO Particular Name SPECIFICATION QUANTITY
123
Digital IC trainer kitIC 7486Connecting Wires
----QUADQUAD
131
THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for
same information. Thus, code converter is a circuit that makes the two systems
compatible even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code
uses four bits to represent a decimal digit. There are four inputs and four outputs.
Gray code is a non-weighted code.
17Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
LOGIC DIAGRAM:
K-Map for G3:
G3 = B3
K-Map for G2:
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K-Map for G1:
K-Map for G0:
TRUTH TABLE:
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