1 Verilog Digital System Desi gn Z. Navabi, 2006 Digital Design Flow Digital Design Flow Digital Design Flow begins with specification of Digital Design Flow begins with specification of the design at various levels of abstraction. the design at various levels of abstraction. Design entry phase: Design entry phase: Specification of design as a Specification of design as a mixture of behavioral mixture of behavioral Verilog code, instantiation of Verilog modules, Verilog code, instantiation of Verilog modules, and bus and wire assignments and bus and wire assignments
Digital Design Flow. Digital Design Flow begins with specification of the design at various levels of abstraction. Design entry phase: Specification of design as a mixture of behavioral Verilog code, instantiation of Verilog modules, and bus and wire assignments. Digital Design Flow. - PowerPoint PPT Presentation
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1Verilog Digital System Design Z. Navabi, 2006
Digital Design FlowDigital Design Flow
Digital Design Flow begins with specification of the Digital Design Flow begins with specification of the design at various levels of abstraction.design at various levels of abstraction.
Design entry phase:Design entry phase: Specification of design as a Specification of design as a mixture of behavioralmixture of behavioralVerilog code, instantiation of Verilog modules, and Verilog code, instantiation of Verilog modules, and bus and wire assignmentsbus and wire assignments
2Verilog Digital System Design Z. Navabi, 2006
Digital Design FlowDigital Design Flow
FPLD Design FlowFPLD Design Flow
Compilation and SynthesisAnalysis Synthesis Routing and placement
module testbench (); generate data; process data;endmodule
Design Design EntryEntryPhasePhase
4Verilog Digital System Design Z. Navabi, 2006
Digital Design FlowDigital Design Flow
Presynthesis verification:Presynthesis verification: Generating testbenches for Generating testbenches for verification of the design and later for verifying the verification of the design and later for verifying the synthesis outputsynthesis output
5Verilog Digital System Design Z. Navabi, 2006
Compilation and SynthesisAnalysis Synthesis Routing and placement
Synthesis process:Synthesis process: Translating the design into actual Translating the design into actual hardware of a target device (FPLD, ASIC or custom hardware of a target device (FPLD, ASIC or custom IC)IC)
7Verilog Digital System Design Z. Navabi, 2006
Compilation and SynthesisAnalysis Synthesis Routing and placement
Postsynthesis simulation:Postsynthesis simulation: Testing the behavioral Testing the behavioral model of the design and its hardware model by using model of the design and its hardware model by using presynthesis test datapresynthesis test data
module testbench (); generate data; process data;endmodule
Device Programming ASIC Netlist Custom IC Layout
EDIFor other netlists1010...
PostsynthesiPostsynthesiss
VerificationVerification
10Verilog Digital System Design Z. Navabi, 2006
Digital Design FlowDigital Design Flow
Digital Design Flow ends with generating netlist for Digital Design Flow ends with generating netlist for an application specific integrated circuits (ASIC), an application specific integrated circuits (ASIC), layout for a custom IC, or a program for a layout for a custom IC, or a program for a programmable logic devices (PLD)programmable logic devices (PLD)
A language that can be understood by:A language that can be understood by: System Designers System Designers RT Level Designers, RT Level Designers, Test Engineers Test Engineers Simulators Simulators Synthesis ToolsSynthesis Tools Machines Machines
Has become an IEEE standardHas become an IEEE standard
14Verilog Digital System Design Z. Navabi, 2006
The Verilog LanguageThe Verilog Language The Verilog HDL satisfies all requirements for design The Verilog HDL satisfies all requirements for design
and synthesis of digital systems:and synthesis of digital systems:
Supports hierarchical description of hardware Supports hierarchical description of hardware from system to gate or even switch level. from system to gate or even switch level.
Has strong support at all levels for timing Has strong support at all levels for timing specification and violation detection. specification and violation detection.
A hardware component is described by the A hardware component is described by the module_declaration module_declaration language construct in it. language construct in it.
15Verilog Digital System Design Z. Navabi, 2006
The Verilog LanguageThe Verilog Language The Verilog HDL satisfies all requirements for design The Verilog HDL satisfies all requirements for design
and synthesis of digital systems (Continued):and synthesis of digital systems (Continued):
Description of a module specifies a component’s Description of a module specifies a component’s input and output list as well as internal input and output list as well as internal component busses and registers within a component busses and registers within a modulemodule, , concurrent assignments, component concurrent assignments, component instantiations, and procedural blocks can be used instantiations, and procedural blocks can be used to describe a hardware component.to describe a hardware component.
Several modules can hierarchically be instantiated Several modules can hierarchically be instantiated to form other hardware structure. to form other hardware structure.
Simulation environments provide graphical front-Simulation environments provide graphical front-end programs and waveform editing and display end programs and waveform editing and display tools. tools.
Synthesis tools are based on a subset of Verilog. Synthesis tools are based on a subset of Verilog.
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Elements of VerilogElements of Verilog
We discuss basic constructs of Verilog language for We discuss basic constructs of Verilog language for describing a hardware module.describing a hardware module.
17Verilog Digital System Design Z. Navabi, 2006
Elements of VerilogElements of VerilogHardware Hardware Modules Modules
modulemodule module-name module-name List of ports;List of ports;DeclarationsDeclarations......Functional specification of moduleFunctional specification of module......
endmoduleendmodule
Module SpecificationsModule Specifications
KeyworKeyword d
modulemodule
module :module :The Main The Main ComponeCompone
nt of nt of VerilogVerilog
Keyword Keyword endmodendmod
uleule
Variables, Variables, wires, and wires, and
module module parametersparameters
are declared.are declared.
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Hardware ModulesHardware Modules
There is more than one way to describe a Module in There is more than one way to describe a Module in Verilog.Verilog.
May correspond to descriptions at various levels of May correspond to descriptions at various levels of abstraction or to various levels of detail of the abstraction or to various levels of detail of the functionality of a module. functionality of a module.
We show a small example and several alternative ways We show a small example and several alternative ways to describe it in Verilog.to describe it in Verilog.
Controller:Controller: Is wired into data part to control its flow of data.Is wired into data part to control its flow of data. The inputs to it controller determine its next states and The inputs to it controller determine its next states and
outputs.outputs. Monitors its inputs and makes decisions as to when and what Monitors its inputs and makes decisions as to when and what
output signals to assert.output signals to assert. Keeps the history of circuit data by switching to appropriate Keeps the history of circuit data by switching to appropriate
states.states. Two examples to illustrate the features of Verilog for describing Two examples to illustrate the features of Verilog for describing
state machines:state machines: SynchronizerSynchronizer Sequence DetectorSequence Detector
ifif (reset) current = s0; (reset) current = s0; elseelse
casecase (current) (current) s0: s0: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; s1: s1: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s0; current <= s0; s2: s2: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s3; current <= s3; s3: s3: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; endcaseendcase
endend
assignassign w = (current == s3) ? 1 : 0; w = (current == s3) ? 1 : 0;
endmoduleendmodule
Verilog Code for Verilog Code for 110110 Detector Detector
65Verilog Digital System Design Z. Navabi, 2006
Sequence DetectorSequence Detector
modulemodule Detector110 ( Detector110 (inputinput a, clk, reset, a, clk, reset, outputoutput w); w);
ifif (reset) current = s0; (reset) current = s0; elseelse
casecase (current) (current) s0: s0: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; s1: s1: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s0; current <= s0; s2: s2: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s3; current <= s3; s3: s3: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; endcaseendcase
endend
Verilog Code for Verilog Code for 110110 Detector Detector
if-elseif-else statementstatementchecks for checks for
resetresetAt the At the Absence Absence of aof a 1 1 on on
resetreset
The 4 Case-The 4 Case-alternativesalternatives
each correspond each correspond to a state of state to a state of state
machinemachine
67Verilog Digital System Design Z. Navabi, 2006
Sequence DetectorSequence Detector
State Transitions on Corresponding Verilog CodeState Transitions on Corresponding Verilog Code
s10
s20
s00
a=0
a=1
s1:
if (a)
current <= s2;
else
current <= s0;
68Verilog Digital System Design Z. Navabi, 2006
Sequence DetectorSequence Detector
endend................................................................................................................assignassign w = (current == s3) ? 1 : 0; w = (current == s3) ? 1 : 0;
endmoduleendmodule
Verilog Code for Verilog Code for 110110 Detector Detector
Assigns a Assigns a 11 to to w ow output when utput when