Digital Design: An Embedded Systems Approach Using Verilog Chapter 2 Combinational Basics Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
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Digital Design: An Embedded Systems Approach Using Verilog Chapter 2 Combinational Basics Portions of this work are from the book, Digital Design: An Embedded.
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Digital Design:An Embedded Systems Approach Using Verilog
Chapter 2Combinational Basics
Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
Digital Design — Chapter 2 — Combinational Basics 2
Verilog
Combinational Circuits
Circuits whose outputs depend only on current input values no storage of past input values no state
Can be analyzed using laws of logic Boolean algebra, similar to
propositional calculus
Digital Design — Chapter 2 — Combinational Basics 3
Verilog
Boolean Functions
Functions operating on two-valued inputs giving two-valued outputs 0, implemented as a low voltage level 1, implemented as a high voltage
level Function defines output value for
all possible combinations of input value
Digital Design — Chapter 2 — Combinational Basics 4
Verilog
Truth Tables
Tabular definition of a Boolean function
x y x + y0 0 0
0 1 1
1 0 1
1 1 1
x y0 0 0
0 1 0
1 0 0
1 1 1
x0 1
1 0
yx x
Logical OR Logical AND Logical NOT
OR gate AND gate
inverter
Digital Design — Chapter 2 — Combinational Basics 5
Verilog
Boolean Expressions
Combination of variables, 0 and 1 literals, operators:
cba
Parentheses for order of evaluation Precedence: · before +
cba
Digital Design — Chapter 2 — Combinational Basics 6
Verilog
Boolean Equations
Equality relation between Boolean expressions Often, LHS is a single variable name The Boolean equation then defines a function
of that name Implemented as a combinational circuit
zyxf x
fy
z
Digital Design — Chapter 2 — Combinational Basics 7
Verilog
Boolean Equations
Boolean equations and truth tables are both valid ways to define a function
zyxf x y z f
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Q: How many rows in a truth table for an n-input Boolean function?
Evaluate f for each combination of input values, and fill in table
Digital Design — Chapter 2 — Combinational Basics 8
Verilog
Minterms
Given a truth table For each rows where
function value is 1, form a minterm: AND of
variables where input is 1 NOT of variables where
input is 0 Form OR of minterms
x y z f
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
zyxzyxzyxf
Digital Design — Chapter 2 — Combinational Basics 9
Verilog
P-terms
This is in sum-of-products form logical OR of p-terms (product terms)
Not all p-terms are minterms eg, the following also defines f
zyxzyxzyx
zxzyx
Digital Design — Chapter 2 — Combinational Basics 10
Verilog
Equivalence
These expressions all represent the same Boolean function
zxzyx
zyxzyxzyx
zyxf
The expressions are equivalent Consistent substitution of variable values
gives the same values for the expressions
Digital Design — Chapter 2 — Combinational Basics 11
Verilog
Optimization
Equivalence allows us to optimize choose a different circuit that implements
the same function more cheaply
Caution: smaller gate count is not always better choice depends on constraints that apply
xy
z
xy
z
Digital Design — Chapter 2 — Combinational Basics 12
Verilog
Complex Gates
All Boolean functions can be implemented using AND, OR and NOT But other complex gates may meet
constraints better in some fabrics
NAND NOR
XOR XNOR
AND-OR-INVERT
x y
NOR NAND
XOR XNOR
0 0 1 1 0 1
0 1 0 1 1 0
1 0 0 1 1 0
1 1 0 0 0 1
yx yx yx yx
Digital Design — Chapter 2 — Combinational Basics 13
Verilog
Complex Gate Example
These two expressions are equivalent:
cbaf 1 cbaf 2
The NAND-NOR circuit is much smaller and faster in most fabrics!
abc
f1
ab
c
f2
Digital Design — Chapter 2 — Combinational Basics 14
Verilog
Buffers
Identity function: output = input Needed for high fanout signals
Digital Design — Chapter 2 — Combinational Basics 15
Verilog
Don’t Care Inputs
Used where some inputs don’t affect the value of a function
Example: multiplexers a b z
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
s a b z
0 0 – 0
0 1 – 1
1 – 0 0
1 – 1 1
Digital Design — Chapter 2 — Combinational Basics 16
Verilog
Don’t Care Outputs
For input combinations that can’t arise don’t care if output is 0 or 1 let the synthesis tool choose
a b c f f1 f2
0 0 0 – 0 1
0 0 1 0 0 0
0 1 0 1 1 1
0 1 1 0 0 0
1 0 0 – 0 1
1 0 1 1 1 1
1 1 0 0 0 0
1 1 1 0 0 0
a
b
c
a
a
b
c
f1
f2
f2
c
b0
Digital Design — Chapter 2 — Combinational Basics 17
Verilog
Commutative Laws
Associative Laws
Distributive Laws
Identity Laws
Complement Laws
Boolean Algebra – Axioms
xyyx xyyx
zyxzyx zyxzyx
)()()( zxyxzyx )()()( zxyxzyx
xx 0 xx 1
1 xx 0xx
Dual of a Boolean equation substitute 0 for 1, 1 for 0, + for ·, · for + if original is valid, dual is also valid
Digital Design — Chapter 2 — Combinational Basics 18