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Preliminary (a) Version S2. Created from 70-113268-02 8/16/99

REV DESCRIPTION DATE ECO SIGN

DOCUMENT TITLE

Specification, Design ASICBy: Date 03/01/99ASIC Group Leader C. Wong

FMTR Block J Appelbaum ATA Block W. Low

BFR Block P. Gill SVO T. Luu

MTR Block D. Do Clock Block D. Do

SER Block M. Uppuluri HNS M. Uppuluri

UPI Block H. Wong ECC Block S. Mo

Documentation R. C. Ayeras

Quantum

DOCUMENT NUMBER REVISION SHEET

R.C. Ayeras Preliminary (a) Printed 8/22/01 1 OF 571Q


R.C. Ayeras Preliminary (a) 8/22/01 2 OF 571

DOCUMENT NUMBER REVISIONR.C. Ayeras Preliminary (a) 8/22/01

GENERAL DESCRIPTION 181.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.2 PART NUMBERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.3 Operating Conditions and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.3.1 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.3.2 Power Estimates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.4 CAPABILITIES AND FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.4.1 ATLAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.4.2 UPI (Microprocessor Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.4.3 Clock Generation and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.4.4 Test Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.4.5 Host Interface (ATA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.4.6 Buffer Control (BFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.4.7 Formatter (FMTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.4.8 ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.4.9 Digital Servo (SVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.4.10 Motor (MTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211.4.11 Serial Interface (SER-RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.5 SYSTEM ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.5.1 ATA Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.5.2 A/V Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.6 MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241.6.1 Ivory Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241.6.2 V850E Mapping (Non A/V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251.6.3 V850E Mapping A/V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261.6.4 SDRAM ADDRESS PINS CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

USER GUIDE 302.1 INITIALIZATION ROUTINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.1.1 Sonic Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.1.2 BFR Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.2 BASIC FUNCTIONAL OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.2.1 Disk read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.2.2 ATA Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.3 MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.3.1 Restrictions (Bugs and/or Design). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

REGISTER DESCRIPTION 343.1 PIN DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.2 REGISTER DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2.1 BUFFER BLOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.2.2 BFR Module (8000h – 80F3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.2.3 RESERVED (BUFFER 80F4h - 80FFh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773.2.4 FORMATTER REGISTERS (8100h - 81AFh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773.2.5 PROGRAMMING OF SELFSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023.2.6 THERMAL ASPERITY (8180h - 818Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043.2.7 RESERVED (FMTR/TA/RWIF 81B0h - 81FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103.2.8 ECC Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113.2.9 ECC Module Registers (8200h - 8300h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153.2.10 RESERVED (ECC 8290h - 829Eh, 829A - 82FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363.2.11 AT INTERFACE (SONIC 8300h - 83FFh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373.2.12 1394 (8400h - 84FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823.2.13 RESERVED (8500h - 857Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833.2.14 CACHE SCAN (8580h - 85FFh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184


3.2.15 SERVO (DIGITAL SYNCHRONOUS SPOKE - DSS 8600h - 86FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2053.2.16 RESERVED SERVO (86A2h - 86FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2503.2.17 MOTOR CONTROL (8700h - 871Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2513.2.18 RESERVED MOTOR (8734h - 873Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2663.2.19 TEST/DEBUG REGISTERS (TMUX 8740h - 875Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2663.2.20 RESERVED TEST/DEBUG (8760h - 877Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2783.2.21 CLOCK/APLL REGISTERS (8780h - 879Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2783.0.1 UPI/PROCESSOR REGISTERS (87C0h -87CFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2893.0.1 RESERVED UPI/PROCESSOR (87D0h - 87DFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2953.0.2 SERIAL BLOCK (87E0h - 87EFh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2963.0.3 RESERVED SERIAL (87F0h -87FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

EXTERNAL TIMING SPECIFICATIONS 2984.1 MICROPROCESSOR INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

4.1.1 K7 Read/Write Cycle (Ivory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2984.2 BUFFER INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

4.2.1 Buffer Timing Diagrams Ivory Buffer Performance Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3004.3 1394 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

4.3.1 TRANSACTION LAYER And ASIC INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3044.4 AT INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

4.4.1 Host Interface Timing - PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3084.4.2 Multiword DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3094.4.3 AT IF/Buffer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3104.4.4 AT IF/Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

4.5 SERVO TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3124.5.1 Raw Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

4.6 SERIAL BLOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3134.6.1 Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3134.6.2 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

4.7 MOTOR BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3154.7.1 Motor Block Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

4.8 ECC BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3184.8.1 GENERAL TIMING DIAGRAMS (For ECC Basic Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3184.8.2 ECC - FORMATTER INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3214.8.3 BUFFER - ECC INTERFACE TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

4.9 Clock Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3244.9.1 SERVO — svoclk1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3254.9.2 SERVO — svoclk2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3254.9.3 SERVO — rwclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3264.9.4 MOTOR — servoclk1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3274.9.5 MOTOR — trclk66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3274.9.6 MOTOR — mtrclk1g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3274.9.7 MOTOR — mtrclk2g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3284.9.8 FMTR — bfrclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3284.9.9 BFR — bfrclk1m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3294.9.10 FMTR — rwclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3304.9.11 BFR — bfrclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3304.9.12 BFR — bfrclk1f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3314.9.13 BFR — rwclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3324.9.14 BFR — refreshed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3334.9.15 BFR — upi_upclkout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3334.9.16 ECC — eccclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3334.9.17 ECC — rwclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3344.9.18 ECC — bfrclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3344.9.19 ATA — ifclk1f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335


4.9.20 ATA — ifclk1g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3364.9.21 ATA — ifclk2f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3374.9.22 SERIAL — serclkg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3374.9.23 TMUX — xtal1f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3374.9.24 UPI — xtal1f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3374.9.25 UPI — upclkout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3384.9.26 V850E CORE — coreclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3394.9.27 ICE — EMULCLK (pin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3394.9.28 AV-ASIC — ATANMINT_AVCLOCK (pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3404.9.29 AVPASIC — UPCLKOUT (pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

PHYSICAL DESCRIPTION 3445.1 MECHANICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

5.1.1 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3445.1.2 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

5.2 PINOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3465.2.1 Pinout Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

5.3 ASIC Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3525.4 Programmable IO Port Assignments and Pull-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

THEORY OF OPERATIONS 3566.1 TOP LEVEL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3566.2 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

6.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3576.2.2 CORE Processor Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3576.2.3 UDL Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

6.3 BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3576.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3576.3.2 Interface Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

6.14 AT INTERFACE BLOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3706.14.1 ATIF Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3706.14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3716.14.3 ATAUPIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3716.18.1 ATAIO Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3736.22.1 TASKFILE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3756.29.1 BFRIF Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3776.35.1 INTSTATUS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3816.52.1 CONTROL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3826.60.1 ATATESTMUX Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

6.61 RWIF BLOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3996.61.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3996.61.2 Serial Command Mode Read/Write Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

6.68 DIGITAL SERVO BLOCK (PRML SPOKE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4056.68.1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4056.75.1 Description Of Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4086.75.2 Synchronous Servo Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4096.75.3 Spoke Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4096.78.1 Track Soft Errors and Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4136.80.1 PRS Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4156.86.1 Skip Track Servo Write (STSW) in MOR Mode = 0 (Rembrandt Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4206.86.2 WCS Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4216.88.1 WCS Program Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4246.88.2 SVO Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4256.88.3 Servo NMI Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4256.90.1 Self Servo Write (SSW) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426


6.92.1 Servo Model State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4286.93 FORMATTER BLOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

6.93.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4316.93.2 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4316.93.3 Calculator State Machine (CALSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4316.93.4 Formatter State Machine (FMTRSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4316.93.5 Defect State Machine (DFSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4326.93.6 Logical Sector Address Manager (LSAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4326.93.7 Dialog Between the Formatter and the µP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4326.93.8 Formatter Command Queue Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

6.97 MOTOR BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4336.97.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4336.97.2 I/O Description And Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4346.100.1 Theory Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

6.106 SERIAL BLOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4646.106.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4646.106.2 Moray R/W Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

6.107 ANALOG PHASE LOCK LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4686.107.1 APLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4686.107.2 PORN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4686.108.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4686.108.2 APLL Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4686.108.3 APLL Stabilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4696.110.1 M, N and P Selection Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4716.110.2 NEC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

6.111 MICROPROCESSOR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4736.111.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4736.111.2 Processor - UPI Block Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4756.111.3 UPI - UDL (User Defined Logic) Block Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4756.111.4 Miscellaneous UPI Block Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4786.112.1 UDL Single Register R/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4786.115.1 Register Write Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4806.116.1 Programmable Hardware Waits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4826.117.1 Suggested Initial Operating Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

6.120 CLOCK BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4846.120.1 Clocks Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

6.121 TMUX BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4856.122 THERMAL ASPERITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

6.122.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4856.122.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4866.122.3 Input Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4866.122.4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

6.123 ECC BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4886.123.1 Channel To ASIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4886.125.1 Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4906.126.1 Sector Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4926.126.2 ECC Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4926.130.1 ECC & XC I/O Port Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4946.130.2 ECC Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4956.130.3 DIB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4986.130.4 ECC On-The-Fly (OTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4996.134.1 Disk Scan (Leo Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

6.137 ECC - BUFFER INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5056.137.1 Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

6.138 ECC - FORMATTER INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5066.138.1 ECC - Formatter Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506


INTERNAL/EXTERNALTIMING SPECIFICATIONSand FLOW DIAGRAMS 5087.1 MICROPROCESSOR INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5087.2 BUFFER INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

7.2.1 Buffer Timing Diagrams Ivory Buffer Performance Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5087.6 1394 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

7.6.1 TRANSACTION LAYER And ASIC INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5127.7 AT INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

7.7.1 Host Interface Timing - PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5167.7.2 Multiword DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5177.7.3 AT IF/Buffer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5187.7.4 AT IF/Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

7.8 SERVO TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5207.8.1 Raw Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

7.9 SERIAL BLOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5217.9.1 Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5217.9.2 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

7.10 MOTOR BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5237.10.1 Motor Block Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

7.11 ECC BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5267.11.1 GENERAL TIMING DIAGRAMS (For ECC Basic Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5267.11.2 ECC - FORMATTER INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5297.11.3 BUFFER - ECC INTERFACE TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

PERFORMANCE 5348.1 BANDWIDTHS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

8.1.1 Buffer and Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5348.1.2 Host Burst and Sustained. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5348.1.3 Disk Burst and Sustained. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

8.2 ECC CORRECTION AND DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

TEST CASE DESCRIPTIONS 5369.1 TOP LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5369.2 BLOCK LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5369.3 COSIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5369.4 COSIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5369.5 RANDOM SIMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

AV Transfer Protocol 538

Update Log 540


DOCUMENT NUMBER REVISIONR.C. Ayeras Preliminary (h) 8/22/01

Q

LIST OF FIGURES

GENERAL DESCRIPTION 18Figure 1-1: Eclipse-2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 1-2: A/V System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 1-3: V850E Mapping - AV: 4 Mbits and 16 MBits SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 1-4: V850E Mapping - AV: 64 MBits SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 1-5: 4 Mbit SDRAM Address Pins Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 1-6: 16 Mbit SDRAM Address Pins Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 1-7: 64 Mbit SDRAM Address Pins Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

USER GUIDE 30

REGISTER DESCRIPTION 34Figure 3-1: Wedge To Wedge Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 3-2: Level 1 High Page Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

EXTERNAL TIMING SPECIFICATIONS 298Figure 4-1: K7 Write Cycle Timing Diagram (Ivory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298Figure 4-2: K7 Read Cycle Timing Diagram (Ivory). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299Figure 4-3: DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300Figure 4-4: DRAM Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301Figure 4-5: Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301Figure 4-6: DRAM Reads For 2 Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303Figure 4-7: Transaction Layer Writes to SDRAM (HBRSTENA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304Figure 4-8: Transaction Layer Writes to SDRAM (HBRSTENA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305Figure 4-9: Transaction Layer Reads To SDRAM (HBRSTENA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306Figure 4-10: Transaction Layer Reads To SDRAM (HBRSTENA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307Figure 4-11: Programmed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308Figure 4-12: Multiword DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309Figure 4-13: ATIF/Buffer Host Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310Figure 4-14: ATIF/Buffer Host Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310Figure 4-15: AT IF/µP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311Figure 4-16: Ivory Rawdata Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312Figure 4-17: Srvstb timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313Figure 4-18: Serial Interface Read/Write To A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313Figure 4-19: SCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314Figure 4-20: SDATA Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314Figure 4-21: SDATA Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314Figure 4-22: Motor Phase Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315Figure 4-23: Motor Run Logic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316Figure 4-24: Motor PWM Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317Figure 4-25: Voice Coil PWM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318Figure 4-26: Two Level Syndrome Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318Figure 4-27: Correctable Error, Uncorrectable with Multimedia Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319Figure 4-28: Uncorrectable Error, Correctable with Disabled Buffer Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319Figure 4-29: ECC Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Figure 4-30: Data Timing During a Disk Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320


Figure 4-31: Data Timing During a Disk Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321Figure 4-32: ECC Block–Formatter–Write Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321Figure 4-33: ECC Block–Formatter–Read Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322Figure 4-34: ECC Block–Formatter–Write Long Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322Figure 4-35: ECC Block–Formatter–Read Long Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323Figure 4-36: Buffer/ECC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

PHYSICAL DESCRIPTION 344Figure 5-1: Ivory (S2) Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344Figure 5-2: Ivory Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

THEORY OF OPERATIONS 356Figure 6-1: Ivory Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356Figure 6-2: Buffer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359Figure 6-3: Buffer Core Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360Figure 6-4: UPl-Buffer Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362Figure 6-5: UPl-Buffer Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362Figure 6-6: UPI/Buffer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363Figure 6-7: Buffer/Cache_scan IF Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363Figure 6-8: Write Data Transfer (Host To Buffer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365Figure 6-9: Read Data Transfer (Buffer to Host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366Figure 6-10: ECC Data Correction Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367Figure 6-11: Write Data Transfer (Buffer to Formatter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368Figure 6-12: Read Data Transfer (Formatter to Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368Figure 6-13: Defect-Buffer Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368Figure 6-14: TA/Buffer Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369Figure 6-15: Formatter Queue/Buffer Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369Figure 6-16: AT Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370Figure 6-17: Write Strobe Generation Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371Figure 6-18: PORN Synchronizer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372Figure 6-19: Wakeup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372Figure 6-20: CRC Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373Figure 6-21: Buffer to ATA Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377Figure 6-22: ATA to Buffer Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378Figure 6-23: ATA to Buffer DIB Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378Figure 6-24: Buffer to ATA DIB Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379Figure 6-25: DIB Error Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380Figure 6-26: Host Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382Figure 6-27: ATIF State Machine (1 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385Figure 6-28: ATIF State Machine (2 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386Figure 6-29: ATIF State Machine (3 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387Figure 6-30: ATIF State Machine (4 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388Figure 6-31: ATIF State Machine (5 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389Figure 6-32: Sonic State Machine Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390Figure 6-33: PIO Write Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391Figure 6-34: PIO Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392Figure 6-35: DMA Write Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393Figure 6-36: DMA Read Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394Figure 6-37: SDMA Write Transfer (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395Figure 6-38: SDMA Write Transfer (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396Figure 6-39: SDMA Read Transfer (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397Figure 6-40: SDMA Read Transfer (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398Figure 6-41: ATIF TESTIO MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399Figure 6-42: R/W Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400Figure 6-43: Command Interface State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401


Figure 6-44: Command Mode Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403Figure 6-45: Synchronous Servo block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409Figure 6-46: Sector Timing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411Figure 6-47: 1-Bit PRS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414Figure 6-48: DSVO Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417Figure 6-49: Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417Figure 6-50: Multiplier Block Diagram For BRSTCAL2 (Dual Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418Figure 6-51: Square Root Function Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419Figure 6-52: BCV Write Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420Figure 6-53: Skip-Track Servo Write (STSW) in MOR_MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421Figure 6-54: SSW Mode (WCS, FMTRSKPLO programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427Figure 6-55: Servo Model State Machine (Sheet 1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428Figure 6-56: Servo Model State Machine (Sheet 2 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429Figure 6-57: Servo Model State Machine (Sheet 3 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430Figure 6-58: Defect Entry Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432Figure 6-59: DRAM Defect Table Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432Figure 6-60: Ivory/Mighty Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435Figure 6-61: Motor Grey Code Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436Figure 6-62: Ivory/Qombo Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438Figure 6-63: Ivory/Hitachi Combo Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440Figure 6-64: Motor Run Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445Figure 6-65: Motor Control Sequencer Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446Figure 6-66: Motor Top Level State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447Figure 6-67: Motor Start Up Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448Figure 6-68: Motor Control Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449Figure 6-69: Motor Phase Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451Figure 6-70: Motor Run Logic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453Figure 6-71: Motor PWM Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454Figure 6-72: Voice Coil PWM Logic Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455Figure 6-73: Voice Coil PWM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456Figure 6-74: Voice Coil Position Code Fix (1 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457Figure 6-75: Voice Coil Position Code Fix (2 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458Figure 6-76: Voice Coil Position Code Fix (3 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459Figure 6-77: Qombo Serial Read/Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461Figure 6-78: Serial Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465Figure 6-79: Qombo and Moray state Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466Figure 6-80: Serial Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467Figure 6-81: Serial Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467Figure 6-82: APLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468Figure 6-83: APLL Stabilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470Figure 6-84: APLL Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471Figure 6-85: uPI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474Figure 6-86: Register Write (1 SHW, 1PHW) 66.6 MHz Processor to 100 MHz Block . . . . . . . . . . . . . . . . . . . . . . . 480Figure 6-87: Register Write (1 SHW, 6 PHW) 66.6 MHz to 40 MHz Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481Figure 6-88: Thermal Asperity Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486Figure 6-89: TA Input Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488Figure 6-90: 10-Bit Data Path During Disk Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491Figure 6-91: 10-Bit Data Path During Disk Write Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491Figure 6-92: Redundancy Generator Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491Figure 6-93: Sector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492Figure 6-94: Read/Write Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492Figure 6-95: ECC Module Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495Figure 6-96: ECC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496Figure 6-97: ECC Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497Figure 6-98: DIB - Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498Figure 6-99: DIB - Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499


Figure 6-100: ECC Syndrome Open/Close Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500Figure 6-101: Two Level Syndrome Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501Figure 6-102: Correctable Error, Uncorrectable with Multimedia Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502Figure 6-103: Uncorrectable Error, Correctable with Disabled Buffer Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . 503Figure 6-104: ECC Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503Figure 6-105: Disk Scan Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505Figure 6-106: ECC/Buffer Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505Figure 6-107: ECC - Formatter Block Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

INTERNAL/EXTERNALTIMING SPECIFICATIONSand FLOW DIAGRAMS 508Figure 7-1: DRAM Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508Figure 7-2: DRAM Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509Figure 7-3: Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509Figure 7-4: DRAM Reads For 2 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511Figure 7-5: Transaction Layer Writes to SDRAM (HBRSTENA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512Figure 7-6: Transaction Layer Writes to SDRAM (HBRSTENA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513Figure 7-7: Transaction Layer Reads To SDRAM (HBRSTENA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514Figure 7-8: Transaction Layer Reads To SDRAM (HBRSTENA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515Figure 7-9: Programmed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516Figure 7-10: Multiword DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517Figure 7-11: ATIF/Buffer Host Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518Figure 7-12: ATIF/Buffer Host Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518Figure 7-13: AT IF/µP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519Figure 7-14: Ivory Rawdata Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520Figure 7-15: Srvstb timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520Figure 7-16: Serial Interface Read/Write To A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521Figure 7-17: SCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522Figure 7-18: SDATA Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522Figure 7-19: SDATA Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522Figure 7-20: Motor Phase Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523Figure 7-21: Motor Run Logic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524Figure 7-22: Motor PWM Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525Figure 7-23: Voice Coil PWM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526Figure 7-24: Two Level Syndrome Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526Figure 7-25: Correctable Error, Uncorrectable with Multimedia Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527Figure 7-26: Uncorrectable Error, Correctable with Disabled Buffer Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527Figure 7-27: ECC Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528Figure 7-28: Data Timing During a Disk Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528Figure 7-29: Data Timing During a Disk Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529Figure 7-30: ECC Block–Formatter–Write Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529Figure 7-31: ECC Block–Formatter–Read Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530Figure 7-32: ECC Block–Formatter–Write Long Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530Figure 7-33: ECC Block–Formatter–Read Long Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531Figure 7-34: Buffer/ECC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

PERFORMANCE 534

TEST CASE DESCRIPTIONS 536


Update Log 540


Q

LIST OF TABLES

GENERAL DESCRIPTION 18Table 1-1: Ivory Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Table 1-2: Ivory V850E Mapping - Non AV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 1-3: Ivory V850E Mapping - AV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

USER GUIDE 30

REGISTER DESCRIPTION 34Table 3-1: Ivory Pin Definitions (8/13/99) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Table 3-2: Buffer Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Table 3-3: Formatter Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Table 3-4: Selfscan Compare Register Byte Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Table 3-5: ECC Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Table 3-6: DIB Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Table 3-7: DIB Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Table 3-8: ECC Syndrome Registers (REG-8204h ECTRL1 [9:8] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Table 3-9: 16-Bit Error Location Registers (REG-8204h ECTRL1 [9:8] = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Table 3-10: 16-Bit Error Mask Registers (REG-8204h ECTRL1 [9:8] = 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Table 3-11: 9-Bit Error Location (REG-8204h ECTRL1 [9:8] = 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Table 3-12: 11-Bit Error Mask Registers (REG-8204h ECTRL1 [9:8] = 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132Table 3-13: AT IF Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Table 3-14: TRPTIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Table 3-15: HNS (Cache Scan) Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184Table 3-16: DSS Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205Table 3-17: Motor Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251Table 3-18: TMUX Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266Table 3-19: TMUX Test I/O 1 Select Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267Table 3-20: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271Table 3-21: TMUX Test I/O2 Select Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271Table 3-22: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276Table 3-23: Clock Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278Table 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279Table 3-1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280Table 3-2: UPI Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289Table 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289Table 3-1: Serial Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

EXTERNAL TIMING SPECIFICATIONS 298Table 4-1: K7 Write Cycle Timing (Ivory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299Table 4-2: K7 Read Cycle Timing (Ivory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300Table 4-3: 60 nSec. EDO DRAM Delay Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302Table 4-4: Programmed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308Table 4-5: Multiword DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309Table 4-6: Ivory Raw Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312Table 4-7: Serial Interface SDATA And SCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315Table 4-8: SERVO — svoclk1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325


Table 4-9: SERVO — svoclk2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325Table 4-10: SERVO — rwclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326Table 4-11: MOTOR — servoclk1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327Table 4-12: MOTOR — mtrclk66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327Table 4-13: MOTOR — mtrclk1g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327Table 4-14: MOTOR — mtrclk2g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328Table 4-15: FMTR — bfrclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328Table 4-16: BFR — bfrclk1m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329Table 4-17: FMTR — rwclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330Table 4-18: BFR — bfrclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330Table 4-19: BFR — bfrclk1f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331Table 4-20: BFR — rwclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332Table 4-21: BFR — refreshed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Table 4-22: BFR — upi_upclkout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Table 4-23: ECC — eccclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Table 4-24: ECC — rwclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334Table 4-25: ECC — bfrclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334Table 4-26: ATA — ifclk1f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Table 4-27: ATA — ifclk1g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336Table 4-28: ATA — ifclk2f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337Table 4-29: SERIAL — serclkg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337Table 4-30: TMUX — xtal1f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337Table 4-31: UPI — xtal1f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337Table 4-32: UPI — upclkout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338Table 4-33: CORE — coreclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339Table 4-34: ICE — EMULCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339Table 4-35: AV-ASIC — ATANMI_AVCLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340Table 4-36: AV-ASIC — UPCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

PHYSICAL DESCRIPTION 344Table 5-1: Ivory Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347Table 5-2: Ivory/Indigo Programmable Port Assignments: ATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355Table 5-3: Ivory/Indigo Programmable Port Assignments: AV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

THEORY OF OPERATIONS 356Table 6-1: CRC Polynomial Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374Table 6-2: ATA Signal Muxing in Various Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374Table 6-3: Taskflie Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375Table 6-4: ATIF Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376Table 6-5: State Machine Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384Table 6-6: DATA[7:0] Roles in Various Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408Table 6-7: XOR Patterns Yielding Full Length (255) for PRSPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415Table 6-8: XOR Patterns Yielding Nearly Full Length (217) for PRSPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415Table 6-9: WCS Do Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422Table 6-10: WCS Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423Table 6-11: WCS Wait Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424Table 6-12: UNLOCK Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470Table 6-13: STBY (Standby Control Signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471Table 6-14: APLL Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473Table 6-15: APLL AC/DC Characteristics (Ta=-40oC-85oC, AVDD=3.0-3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473Table 6-16: Programming Hardware Wait Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483Table 6-17: Ivory Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484Table 6-18: ECC Block I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494Table 6-19: DIB Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498Table 6-20: Worst Case Error Correction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500


Table 6-21: Firmware Readback Status (ECC-OTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

INTERNAL/EXTERNALTIMING SPECIFICATIONSand FLOW DIAGRAMS 508Table 7-1: 60 nSec. EDO DRAM Delay Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510Table 7-2: Programmed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516Table 7-3: Multiword DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517Table 7-4: Ivory Raw Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520Table 7-5: Serial Interface SDATA And SCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

PERFORMANCE 534

TEST CASE DESCRIPTIONS 536


Update Log 540


HARDWARE MANUAL

ASICVOLUME 1 - FIRMWARE

Volume 1 contains the Firmware Specification(Sections 1 through 5).




NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPERTY OF QUANTUM CORPORATION. THE POSSESSOR AGREES TO MAINTAIN THIS DOCUMENT INCONFIDENCE, NOT TO REPRODUCE, COPY, REVEAL OR PUBLISH IT IN WHOLE OR IN PART.

Volume 1 Section 2USER GUIDE

2.1 INITIALIZATION ROUTINES

2.1.1 Sonic InitializationThe Sonic block powers on as busy and the registers power up with all zeros. To initialize the block, the followingregisters must be programmed in the sequence shown below:

1) Set ATA clock to 100 Mhz in Clock blockSet ATACLK = 8'h02

2) Set MaxLba to the capacity of the driveSet MAXLBA1, MAXLBA2, MAXLBA3, MAXLBA4.

3) Set MaxCHSLba to the logical CHS of the driveSet MAXCHSLBA1, MAXCHSLBA2, MAXCHSLBA3, MAXCHSLBA4.

4) Set the size of the write command queueSet WCQSIZE to the Command Queue Size.

5) Clear Interrupts (INTST)Set INTSTL = 8'hFF;Set INTSTH = 8'hFF;Set INTSTL2 = 8'hFF;

6) Enable Interrupt Masks (INTMSK)Set INTMSKL = 8'hFF;Set INTMSKH = 8'hFF;Set INTMSKL2 = 8'hFF;

7) Program Sector and Head roll overSet SECROLL and HEADROLL to drive configuration.

8) Program Sector Per Track and Sectors per Cylinder for CHS to LBA conversionSet SECPERTRK, SECPERCYLLO and SECPERCYLHI

9) Program Physical and Logical Ecc byte countSet LOGECCCNT and PHYECCCNT

10) Enable Commands for hardware decode (CMDENL & CMDENH)óSet CMDENL = 8'hFF;óSet CMDENH = 8'hFF;

11) Clear busy (set bit 4 of IFCTL 1)

12) Program Host Status register (HSTSTAT)Set HSTSTAT = 8'h50;

2.1 INITIALIZATION ROUTINES 2.1.2 BFR Initialization



NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPERTY OF QUANTUM CORPORATION. THE POSSESSOR AGREES TO MAINTAIN THIS DOCUMENT INCONFIDENCE, NOT TO REPRODUCE, COPY, REVEAL OR PUBLISH IT IN WHOLE OR IN PART.

2.1.2 BFR InitializationThe BFR initialization routine follows.

begint‘uwrreg (24’hff: 8783, 8’h02)if sdram 4mbit_10ns

‘uwwreg (24’hFF: 8780, 8’h04) // for 4Mbit DRAM write these values‘uwrword(24’hFF: 8062, 16’h F1C7)

else if sdram 16mbit_10ns‘uwrreg(24’hFF 8780, 8’h44) // for 16Mbit DRAM put the following values‘uwrword (24’hFF8062, 16’hF0B4)

else if sdram 64mbit_10ns‘uwrreg(24’hFF 87802, 8’h484) // for 64Mbit DRAM put following values‘uwrword (24’hFF8062, 16’hF9E7);

endifuwrreg (24’hFF8061, 8’h00);no_opno_opuwrreg (24’FF8061, 8’h00);

end initialization routine


HARDWARE MANUAL

ASICVOLUME 2 - HARDWARE

Volume 2 contains the ASIC Hardware Specification(Sections 6 through 9).




Volume 2 Section 5PHYSICAL DESCRIPTION

5.1 MECHANICAL SPECIFICATIONS

5.1.1 Package176 plastic TQFP, 0.4 mm pin pitch, refer to Figure 5-1: for additional information..

Figure 5-1: ASIC Package Specifications

.

88

89132

133

176

44

45

1

17.20 Typ.

22.20 – 21.80

20.20 – 19.80

22.2

0–

21.8

0

20.2

0–

19.8

0

0.05 Min.

1.4 Typ.

0.13 Nom.

0.08

Seating Plane

1.60 Max.

0° – 7°0.60 – 0.40

0.23 – 0.13 0.08 M

0.40 Typ. 176 Places

All dimensions are in millimeters.

5.1 MECHANICAL SPECIFICATIONS 5.1.2 Miscellaneous



5.1.2 Miscellaneous• Low power CMOS 2.5 V/0.25 µm Standard Cell technology.• RAM cells:

- one (128 Words x 16 Bits 18,025 grids- two (64 Words x 16 Bits) 23,00 grids- two (64 Words x 47 bits) 61,252 grids- one (16 Words x 16 Bits) 6.710 grids- one (32 Words x 16 Bits) 8,072 grids

• NEC V850E Core 75,000 grids• BFR Block 92,300 grids• ECC Block 169,000 grids• FMTR Block 59.400 grids• µPI Block 17,800 grids• Motor Block 20.170 grids• Clock Block 19.700 grids• Serial Block 2,200 grids• Servo Block 66,500 grids• Tmux Block 10,400 grids• ATA Block 70,400 grids• Cache Scan Block 61,400 grids

5.2 PINOUT 5.2.1 Pinout Drawing



5.2 PINOUT

5.2.1 Pinout Drawing

VSS— —133

UPLBEN — —134

UPUBEN — —135

SENU_FS — —136

MTRINT — —139

SC3_MSENA — —140

VDD — —141

SC1_MSCLK — —142

VIPWML — —144

SHK_XCLK2A_TST2 — —145

VSSPWM — —147

VIPWMH_SVDAT — —148

VDDPWM — —149

79 — — BADD8_BADD10




75 — — SDRAMCS

74 — — BRASN

73 — — VDD

66 — — VDD

72 — — SDRAMCLK

71 — — VSS

70 — — BCASN

69 — — DQMH

68 — — BWEN

67 — — DQML

64 — — BDAT8/BADD9

63 — — BDAT7

65 — — VSS

60 — — VDD2

62 — — BDAT9/BADD8

58 — — BDAT5

59 — — BDAT10

57 — — BDAT11

55 — — VSS

56 — — BDAT4

54 — — BDAT12

53 — — BDAT3

52 — — BDAT13

50 — — VDD

51 — — BDAT2

48 — — BDAT1

49 — — BDAT14

47 — — BDAT15

45 — —VSS

46 — — BDAT0



81 — — VSS






RW

DA

TA

8—

—1

I_R

EF

——

3

RW

DA

TA

9—

—2

VS

S—

—4

HR

ES

INT

_P25

——

6

VD

D—

—5

HD

8_P

OR

T17

——

8

HD

6_P

OR

T16

——

9

VS

S—

—11

HD

5_P

OR

T15

——

12

HD

4_A

VN

MIN

T—

—14

VD

D(N

EC

)/V

DD

5(Lu

cent

)—

—16

HD

11_P

OR

T22

——

15

HD

3_H

AC

K—

—17

HD

13—

—20

HD

12_P

OR

T24

——

18

VS

S—

—21

VD

D2

——

22

HD

14_A

VR

ES

ET

N(a

vin

)—

—24

HD

1_P

OR

T11

——

23

HD

0_P

OR

T10

——

25

VD

D—

—27

HD

15_I

FW

AIT

N(a

vin

)—

—26

DM

AR

Q(a

taou

tonl

y)—

—28

IOW

N—

—29

IOR

N—

—30

DM

AC

KN

——

32

IOR

DY

(ata

outo

nly)

——

31

IRQ

14_A

VIN

T(a

vis

in)

——

33

VS

S—

—35

IOC

S16

N_A

VH

INT

(bot

hin

)—

—34

HA

1—

—36

HA

0—

—38

PD

IAG

_PO

RT

14—

—37

HA

2—

—39

CS

1N_H

RE

Q(a

vin

)—

—41

CS

0N—

—40

DA

SP

_PO

RT

13—

—42

VD

D—

—44

HR

ES

ET

N—

—43

118

——

MA

D13

P37

_MA

D13

95—

—A

TA

NM

I_A

VC

LOC

K

116

——

MA

D11

P35

_MA

D11

115

——

MA

D10

P27

_MA

D10

114

——

MA

D9P

26_M

AD

9

112

——

VD

D

111

——

MA

D7P

17_M

AD

7

99—

—U

PW

AIT

N

110

——

MA

DP

16_M

AD

6

109

——

MA

D5P

15_M

AD

5

105

——

MA

D1P

11_M

AD

1

108

——

MA

D4P

14_M

AD

4

107

——

MA

D3P

13_M

AD

3

106

——

MA

D2P

12_M

AD

2

102

——

EM

UC

LK

104

——

MA

D0P

10_M

AD

0

103

——

VS

S

101

——

UP

AS

TB

100

——

UP

CLK

OU

T

96—

—V

DD

98—

—P

OR

N

97—

—U

PD

ST

BN

120

——

MA

D15

P22

_MA

D15

117

——

MA

D12

P36

_MA

D12

125

——

A19

_SI

124

——

A18

_MO

DE

2

123

——

A17

_MO

DE

1

122

——

A16

_MO

DE

0

121

——

VS

S

119

——

MA

D14

P24

_MA

D14

126

——

A20

_SO

(SO

out)

129

——

A23

_MO

DE

4

128

——

A22

_MO

DE

3

127

——

A21

_AV

SE

L

132

——

VD

D2

131

——

UP

R_W

N

130

——

BR

ST

RQ

_SC

VSSA — —150

XTLOUT1 — —151

XTLINP1 — —152

VDDA — —153

VSS — —154

WRGATEIN — —156

SVOGATE — —157

S_RCLK — —160

VDD2 — —159

AUXCTL — —161

SDATA — —162

RWGATE — —158

FAULTN — —163

VSS — —164

RWCLK — —165

VDD — —166

RWDATA0 — —167

RWDATA2 — —169

VSS — —171

RWDATA4 — —172

RWDATA3 — —170

RWDATA1 — —168

RWDATA6 — —174

RWDATA5 — —173

VDD2 — —176

RWDATA7 — —175

88 — — VDD2

94—

—V

DD

2

93—

—A

TA

HIN

T_A

VC

LKE

N

92—

—T

ES

TIO

1

91—

—F

INT

90—

—B

AD

D3_

BA

DD

3

89—

—V

SS

SENV_EXTCLK2B — —137

SENW_EXTCLK1B — —138

SC2_MSDAT — —143

TST2_XCLK1A_SMO — —155

HD

2_P

OR

T12

——

19

HD

10_P

OR

T37

——

13

HD

7_P

OR

T35

——

7

HD

9_P

OR

T36

——

10

61 — — BDAT6

SIPWM — —146

C. Wong R10 9/3/99

ASIC

113

——

MA

D8_

MA

D8

VDD (10) = 3.3VVDD2 (7) = 2.5VVDD5 (1) = 5VVSS (11) = GndVDDA (1) = 3.3V APLLVSSA (1) = Gnd APLLVDDPWM (1) = 3.3V PWMVSSPWM (1) = Gnd PWMIREF(1) = Current reference




Figure 5-2: ASIC PinoutPin Descriptions

Table 5-1: ASIC Pin Description

PIN NUMBER SIGNAL NAME DESCRIPTION

SYSTEM Total 43 Pins

3 IREF 1. Current reference for ATA100 I/Os.2. Requires an external resistor, 1kΩ +/- 1%, wired to ground.

152 XTLINP1 3. 40MHz resonator input4. APLL test mode: REFCLK

151 XTLOUT1 40MHz resonator output

92 TESTIO1 1. Core test mode: Test bidi signal #29.2. Other modes: TRIGGER IN or multiplex UDL output signals. POR default to output mode.3. APLL test mode: VCO

155TST2_XCLK1A_SMODE

1. ATA or A/V normal mode: TRIGGER IN or multiplex UDL output signals.2. Core test mode: Test bidi signal #19.3. Other modes: EXTCLK1A, or TRIGGER IN or multiplex UDL output signals. POR default to

input mode.4. APLL test mode: VCOP

16 VDD5 (1) 5v supply for the ATA interface signals.

5, 27, 44, 50, 66, 73, 96, 112, 141, 166 VDD (10) 3.3v supply pins. Pins 29 and 44 are dedicated for the UDMA IO ring.

22, 60, 88, 94, 132, 159, 176 VDD2 (7) 2.5v supply for the internal UDL and the processor core.

4, 11, 35, 45, 55, 65, 71, 81, 89, 103, 121,133, 153, 164, 171

VSS (16) Digital ground. Pins 12, 23, and 35 are dedicated to the UDMA IO ring.

154 VDDA Frequency synthersizer isolated supply pin:1. For ASIC, it is 3.3v; Also, the resonator IO shares this supply.2. For ASIC, it is 2.5v.

150 VSSA Frequency synthersizer isolated ground pin:1. For ASIC, the resonator IO shares this ground pin.

149 VDDPWM Motor PWM output signal isolated 3.3v supply.

147 VSSPWM Motor PWM output signal isolated ground pin.

UPI I/F Total 39 pins

104 MAD0P10_MAD0 1. ATA normal mode: Port 1, bit 02. ATA emulation mode: multiplexed data and address bit 03. A/V normal or emulation mode: multiplexed data and address bit 04. Core test mode: Test bidi signal #0











113 MAD8_MAD8 1. ATA normal mode: Not used2. ATA emulation mode: multiplexed data and address bit 83. A/V normal or emulation mode: multiplexed data and address bit 84. Core test mode: Test bidi signal #8








122 A16_MODE0 1. ATA or A/V emulation mode: address bit 162. During POR, latched in as MODE bit 03. Core test mode: Test input #334. APLL test mode: M[0]



125 A19_SI 1. ATA or A/V emulation mode: address bit 192. ATA or A/V normal mode: Serial input for external FLASH upload

126 A20_SO 1. ATA or A/V emulation mode: address bit 202. ATA or A/V normal mode: Serial output for external FLASH download3. APLL test mode: FRANGE

127 A21_AVSEL 1. ATA or A/V emulation mode: address bit 212. A/V normal mode: A/V select to ASIC 2 (output)3. Core test mode: Test bidi signal #244. APLL test mode: M[3]


129 A23_MODE4 1. ATA or A/V emulation mode: address bit 232. During POR, latched in as MODE bit 33. Core test mode: Test input #384. APLL test mode: N[0]

130 BRSTRQ_SC 1. ATA or A/V emulation mode: Burst transfer request (input)2. ATA or A/V normal mode: Serial clock for external FLASH (output)

131 UPR_WN 1. ATA or A/V emulation mode: IO R/W (input)2. A/V normal mode: IO R/W (output from core to ASIC 2)3. Core test mode: Test bidi signal #25

134 UPLBEN 1. ATA or A/V emulation mode: IO R/W low byte enable (input)2. A/V normal mode: IO R/W low byte enable (output from core to ASIC 2)3. Core test mode: Test bidi signal #26

Table 5-1: ASIC Pin Description (Continued)





135 UPUBEN 1. ATA or A/V emulation mode: IO R/W high byte enable (input)2. A/V normal mode: IO R/W high byte enable (output from core to ASIC 2)3. Core test mode: Test bidi signal #27

95 ATANMINT_AVCLOCK 1. ATA emulation mode: Servo (NMI) interrupt (output)2. Core test mode: Test bidi signal #283. AV normal and emulation mode: AV Clock

91 FINT 1. ATA or A/V emulation mode: Formatter interrupt (output)2. ATA or A/V normal mode: SpareInt (input)3. Core test mode: Test output #324. APLL test mode: N[2]

5 HRESINT_P25 1. ATA or A/V emulation mode: Host reset interrupt (output)2. ATA normal mode: PORT 2, bit 5 (IDE_CABLE_SELECT)

93 ATAHINT_AVCLKEN 1. ATA emulation mode: Host interrupt (output)2. AV normal and emulation mode: AV clock enable3. Core test mode: Test bidi signal #204. APLL test mode: PWRDN

139 MTRINT 1. ATA or A/V emulation mode: Mighty motor interrupt (output)2. ATA or A/V emulation mode: Redwood motor interrupt (input)3. Core test mode: Test bidi signal #214. APLL test mode: N[1]

97 UPDSTBN 1. ATA or A/V emulation mode: IO R/W data Strobe (input)2. A/V normal mode: IO R/W data strobe (output from core to ASIC 2)3. Core test mode: Test bidi signal #22

98 PORN 1. All modes: power on reset

99 UPWAITN 1. ATA or A/V emulation mode: processor wait (output)2. Core test mode: Test input #35

100 UPCLKOUT 1. All modes: processor clock for burst mode (3.3v failsafe)

101 UPASTB 1. ATA or A/V emulation mode: IO R/W address Strobe (input)2. A/V normal mode: IO R/W address strobe (output from core to ASIC 2)3. Core test mode: Test bidi signal #23

102 EMULCLK 1. All modes: Emulation clock

SDRAM I/F (Buffer) Total 37 pins

77(MSB), 78, 76, 79, 80, 83, 85, 87, 90, 86,84, 82(LSB)

BADD[11:0] 1. All modes: Buffer address [11:0] for 4 Mbit SDRAM, badd[7:0]2. For 16Mb SDRAM: BADD[9:8] mapped to SDRAM pin ADD11:10], BADD[11:10] mapped

to SDRAM pin ADD[9:8], BADD[7:0] mapped to ADD[7:0].3. For 64 Mbit SDRAM : BADD[11:8] mapped to BADD[13:10]

62 BDAT9_BADD8 1. All modes: Buffer data bit 92. For 64 Nbit SDRAM : shared with BADD[8]

64 BDAT8_BADD9 1. All modes: Buffer data bit 82. For 64 Mbit SDRAM : shared with BADD[9]

47(MSB), 49, 52, 54, 57, 59(LSB) BDAT[15:10]] 1. All modes: Buffer data [15:10].

63(MSB), 61, 58, 56, 53, 51, 48, 46(LSB) BDAT[7:0] 1. All modes: Buffer data [7:0]

68 BWEN 1. All modes: Buffer write enable

69 DQMH 1. All modes: Buffer high byte enable

67 DQML 1. All modes: Buffer low byte enable

70 BCASN 1. All modes: Buffer column address strobe

74 BRASN 1. All modes: Buffer row address strobe

72 SDRAMCLK 1. All modes: Buffer clock

75 SDRAMCS 1. All modes: Buffer chip select

Motor I/F Total 10 pins

142 SC1_MSCLK 1. Mighty : Spindle phase 12. Redwood : Serial port clock3. Core test mode: Test output #33

143 SC2_MSDAT 1. Mighty : Spindle phase 22. Redwood : Serial port data3. Core test mode: Test bidi signal #16

140 SC3_MSENA 1. Mighty : Spindle phase 32. Redwood : Serial port enable3. Core test mode: Test bidi signal #174. APLL test mode: RESET






136 SENU_FS 1. Mighty : Sense phase U2. Redwood : Failsafe (same as UPF)3. Core test mode: Test bidi signal #314. APLL test mode: BYPASS

137 SENV_EXTCLK2B 1. Mighty : Sense phase V2. Core test mode: Test bidi signal #303. APLL test mode: P[1]

138 SENW_EXTCLK1B 1. Mighty : Sense phase W2. Core test mode: Test input #363. APLL test mode: P[0]

148 VIPWMH_SVDAT 1. Mighty : PWM (MSB) to control voice coil current2. Redwood : PWM Serial port data

144 VIPWML 1. Mighty : PWM (LSB) to control voice coil current

146 SIPWM 1. Mighty : PWM to control motor current

145 SHOCK_XCLK2A_TST2

1. Shock Sensor detection2. EXTCLK2A3. In Mighty mode: TESTIO24. Core test mode: Test bidi signal 185. PC debug mode: PC(18)

ATA Interface Total 31 pins

25 HD0_PORT10 1. Normal ATA mode: HD02. Normal A/V mode: Port 1, bit 03. Program Count Debug mode: PC[1]



17 HD3_HACK 1. Normal ATA mode: HD32. Normal A/V mode: Host ACK3. Program Count Debug mode: PC[4]

15 HD4_AVNMINT 1. Normal ATA mode: HD42. AV emulation mode: NMINT3. Program Count Debug mode: PC[5]









21 HD13 1. Normal ATA mode: HD132. Normal A/V mode: Port 2, bit 53. Program Count Debug mode: PC[14]

24 HD14_AVRESETN 1. Normal ATA mode: HD142. All AV mode: AV reset from ASIC 23. Program Count Debug mode: PC[15]






26 HD15_IFWAITN 1. Normal ATA mode: HD152. ALL AV modes: Interface waitn3. Program Count Debug mode: PC[16]

6 HRESETN 1. All ATA mode: Host Reset_

28 IOWN 1. All ATA mode: IO Write_

27 DMARQ 1. All ATA mode: DMA Request

30 IORN 1. All ATA mode: IO Read_

31 IORDY 1. All ATA mode: IO Ready

32 DMACKN 1. All ATA mode: DMA ACK_

33 IRQ14_AVINT 1. All ATA mode: IRQ142. All A/V mode: A/V Host Interrupt In

34 IOCS16N_AVHINT 1. All ATA mode: IOCS16_2. AV emulation mode: AV host Interrupt out

36 HA1 1. All ATA mode: Host Address 1

37 PDIAG_PORT14 1. All ATA mode: PDIAG_2. Normal A/V mode: Port 1, Bit 4


43 DASP_PORT13 1. All ATA mode: DASP2. Normal A/V mode: Port 1, bit 33. Program Count Debug mode: PC[17]


42 CS1N_HREQ 1. All ATA mode: Chip Select 1_2. All A/V mode: Host Request

41 CS0N 1. Normal ATA mode: Chip Select 0_

R/W I/F (FMTR) Total 18 pins

3(MSB), 2, 175, 174, 173, 172, 170, 169,168, 167(LSB)

RWDAT[9:0] 1. All Modes: Channel data during Read, Write, and Servo operation

163 FAULTN 1. All Modes: Read channel or Preamp fault_

160 S_RCLK 1. All Modes: Channel Serial port clock & REFCLK

162 SDATA 1. All Modes: Channel Serial port data

161 AUXCTL 1. All Modes: Extended control

156 WRGATEIN 1. All Modes: Enables write data drives & preamp wrgout via quiet buffer on channel

158 RWGATE 1. All Modes: Functions as “read gate” or “write gate”, as per state of WRGATEIN

157 SVOGATE 1. All Modes: Enable servo mode operation

165 RWCLK 1. All Modes: RW clock



5.3 ASIC Modes of Operation 5.2.1 Pinout Drawing



5.3 ASIC MODES OF OPERATION

The ASIC family has twenty-six modes of operation which are determined by the states of the five mode pins upon therising edge of reset: PORN, 121.

The mode pins are A23, MODE4, A22_MODE4, A22_MODE3, A18_MODE2, A17_MODE1, A16_MODE0, and chippins 155, 153, 149, 148, 146. All mode pins except A16_MODE0 have internal pull-downs; A16_MODE0 has aninternal pull-up. All modes are assigned with a mode number Mxx, where xx is the decimal value from the mode pinsupon POR. M0 and M1 are reserved to the ATA_Standalone and ATA_Emulation modes, respectively, so that they arecompatible with Tristar.

Following is a brief description of the twenty-six modes, including debug modes.

Note: The ATA drive heads must use M0 and M1 (M10 and M11for the AV drive team) for drive bring-up and testing. M4for the ATA and M14 for the AV are the emergency modeswhich allow the core program counter value to beobserved at the chip IO.

M0:ATA_Standalone• Normal core run mode.• External FLASH code downloaded into internal SRAM after POR (E/P builds).• 16 programmable IO ports available on the MAD bus and “HRESINT”.• APLLs have been checked out: They are functioning.• Core powered up with the OSC 40 MHz: FW can switch the core clock to 33MHz,

50MHJz, or 66MHz.• Normally, external clocks are not required: SHOCK, TESTIO2, SENV, and SENW are

used. If either or both EXTCLK2 or EXTCLK1 is required, they can be receivedthrough pins SHOCK and TESTIO2, respectively.

• There must be an internal Shock Enable register bit (POR default is disabled). It mustbe set to enabled when SHOCK is used normally.

• Functional HW blocks provide options to select the OSC, APLL outputs, or APLL out-put derivatives.

M1: ATA_Emulation• Normal emulation debug/run mode: Test Vector generation mode.• 40 MHz OSC clock to core during POR; then use STOPB to step the core.• 16 Programmable IO ports available from the emulator.• If APLLs are working (normal emulation mode):

- 13.3MHz EMULCLK (66MHz µP clock) is the POR default.FW can switch to other EMUL-CLK frequencies (6.6MHz, 8MHz, 10MHz).

- External clocks are not required. SHOCK, TESTIO2, SENV, and SENW are used normal-ly.

- Function HW blocks provide options to select the OSC, APLL outputs, or APLL output de-rivatives.

• If the APLLs or the OSC are not working:- If NO EMULCLK, then use an external emulation clock.- To determine which clock is non-functional, bring out the OSC clock (POR) default) and

APLL outputs to TESTIO1 one at a time.- Use SHOCK as EXTCLK2 to bring in 66.6MHz, and use TESTIO2 as EXTCLK1 to provide

100MHz.- Functional HW blocks provide the ability to select a clock that is available.

• With EXTCLK1 and EXTCLK2 brought in from TESTIO2 and SHOCK, respectively,this mode can be used to generate test vectors for all blocks except for theservoblocks and the tmux blocks. EXTCLK1 and EXTCLK2 can also be used to generateIDDQ test vectors.




M2: ATA_Standalone_Debug• Core debug mode for checking the core/UDL interface. Similar to M0

(ATA_Standalone), with the following modifications:- The Core receives clock from EXTCLK2 through the SHOCK pin, instead of APLL.- Internal Shock Enable bit remains disabled.

M3: ATA_Emulation_Test• Similar to M1 (ATA_Emulation) except for the following:

- EXTCLK1 and EXTCLK2 are brought in from SENW and SENV, respectively. This modeis used to generate test vectors for the servo block and the tmux blocks, respectively. Thiscan also be used to generate IDDQ test vectors.

M4: ATA_PC_Debug• Similar to M0 (ATA_Standalone) except with the following:

- ATA cable is disconnected.- 16 programmable IO ports are available on the MAD bus and the HRESING pin.- Core Program Count [18:1] are visible on ATA HD, IORN, and DASP lines.

M5: ATA_CORE_IF_TEST• CORE/UDL Test Vector generation mode.

M6: ATA_Emulation_33• Similar to M1 (ATA_Emulation) except that EMULCLK is set to 6.6MHz (33MHz µP

clock) at POR. It can be switched to other frequencies by FW.M7: ATA_Emulation_50

• Similar to M1 (ATA_Emulation), except that EMULCLK is set to 10MHz (50MHz mPclock) and POR. Ican be switched to other frequencies, 6.6MHz, 8MHz, or 13.3MHz,by FW.

M8: ATA_Emulation_40• Similar to M1 (ATA_Emulation), except that EMULCLK is set to 8MHz (40MHz µP

clock) at POR. It can be switched to other frequencies by FW: 6.6MHz, 10MHz,13.3MHz.

M9: ATA_Standalone_Profile: New for V2• Except Port2.5 (CABLE_SELECT_IDE), all programmable IO ports defined in normal

ATA standalone modes (M0, M2, M4, and M5), are NOT available.• Pins 120-113 and 111-104 are re-defined as the normal bi-directional uP MAD bus.• All five processor control signals are driven by the Core and available on the pins

UPR_WN, UPDSTBN, UPASTB, UPLBEN, and UPUBEN.• Pin 127 (A21_AVSEL) is asserted when address between 00FF:8400h to

00FF:84FFh is decoded, indicating this is in the FW profiling arrange.M10: AV_Standalone:

• Similar to M0 (ATA_Standalone) except with the following modifications:• ATA interface control signal pins are re-defined to interface with ASIC 2• UP interface pins are needed for the core to talk to ASIC 2• Programmable I/O ports are available on the ATA interface data pins• AV FW_Profiling functional mode

M11: AV_Emulation:• Similar to M1 (ATA_Emulation) except with the following modifications:• ATA control signal pins are re-defined to interface with ASIC 2

M12: AV_Standalone_Debug:• Similar to M2 (ATA_Standalone_Debug) except with the following modifications:• ATA interface control signal pins are re-defined to interface with ASIC 2• UP interface pins are needed for the core to talk to ASIC 2• Programmable I/O ports are available on the ATA interface data pins




M13: AV_Emulation_Test :• Similar to M3 (ATA_Emulation_Test) except with the following modification :• ATA control signal pins are re-defined to interface with ASIC 2

M14: AV_PC_Debug :• Similar to M4 (ATA_PC_Debug) except with the following modifications :• Programmable I/O ports are NOT available• Core Program Count [18:1] are visible on ATA HD, IORN, and DASP lines

M15: AV_CORE_IF_TEST :• CORE/UDL Test Vector generation mode• AV FW_Profiling Test Vector generation mode

M16: AV_Emulation_33 :• Similar to M11 (AV_Emulation) except that the “EMULCLK” is set to 6.6MHz (33MHz

uP clock) at POR, and it can be switched to other frequencies by FW.M17: AV_Emulation_50:

• Similar to M11 (AV_Emulation) except that “EMULCLK” is set to 10MHz (50MHz uPclock) at POR, and it can be switched to other frequencies (6.6, 8, or 13.3MHz) byFW.

M18: AV_Emulation_40:• Similar to M11 (AV_Emulation) except that “EMULCLK” is set to 8MHz (40MHz uP

clock) at POR, and it can be switched to other frequencies (6.6, 10, or 13.3MHz) byFW.

M19: ATA_CORE_IF_PROFILE_TEST: New for V2• For test vector generation only (M9 is the functional mode)• Core boot up from external SDRAM similar to M5, ATA_CORE_IF_TEST• MAD bus, uP control signals, and A21_AVSEL are same as defined in M9.

M20: ATA/AV CORE_TEST• Reserved for vendor Core test.

M21: ATA/AV CORE_BIST• Reserved for Lucent Core memory test.

M22: ATA/AV DC_TEST• Reserved for NEC manufacturing test.

M23: ATA/AV Lucent APLL1_TEST• Reserved for APLL1 (100MHz and 200MHz) test.• Inputs to the APLL1 macro can be controlled from the chip pins.• Output of the APLL1 macro can be observed at the chip pin.

M24: ATA/AV Lucent APLL2_TEST• Reserved for APLL2 (66.6MHz and 133MHz) test.• Inputs to the APLL2 macro can be controlled from the chip pins.• Outputs of the APLL2 macro can be observed at the chip pins.

M25: ATA/AV NEC APLL1_TEST• Reserved for NEC APLL1 test.

M26: ATA/AV NEC APLL2_TEST• Reserved for NEC APLL2 test.

5.4 Programmable IO Port Assignments and Pull-Up Requirements 5.2.1 Pinout Drawing



5.4 PROGRAMMABLE IO PORT ASSIGNMENTS AND PULL-UP REQUIREMENTS

Table 5-2: ASIC Programmable Port Assignments: ATA

PinNumber Pin Description Assignment

Pull-UpResister

104 MAD0/Port 1.0 MTR_ID Y

105 MAD1/Port 1.1 HTEMP Y

106 MAD2/Port 1.2 GMR_SELECT Y

107 MAD3/Port 1.3 LEDON Y

108 MAD4/Port 1.4 SMODE N

109 MAD5/Port 1.5 DWENA Y

110 MAD6/Port 1.6 SKCOMP Y

111 MAD7/Port 1.7Port 2.1 IN

RETRACTInternally Tied High

N

120 MAD15/Port 2.2 PWR_FLT_INT Y

119 MAD14/Port 2.4 PARK_IDE Y

5 HRESINT/Port 2.5 CABLE_SELECT_IDE Y

114 MAD9/Port 2.6 DS_IDE Y

115 MAD10/Port 2.7 CS_IDE Y

116 MAD11/Port 3.5 VPCNTL N

117 MAD12/Port 3.6 FLASH_CS Y

118 MAD13/Port 3.7 SCOPETRIG Y

Table 5-3: ASIC Programmable Port Assignments: AV

PinNumber Pin Description Assignment

Pull-UpResister

25 HD0/Port 1.0 MTR_ID Y

22 HD1/Port 1.1 HTEMP Y

20 HD2/Port 1.2 GMR_SELECT Y

43 DASP/Port 1.3 LEDON Y

37 PDIAG/Port 1.4 SMODE N

11 HD5/Port 1.5 DWENA Y

9 HD6/Port 1.6 SKCOMP Y

8 HD8/Port 1.7 RETRACT N

16 HD11/Port 2.2 PWR_FLT_INT Y

19 HD12/Port 2.4 NC (No Connect) Y

7 HD7/Port 3.5 VPCNTL N

10 HD9/Port 3.6 FLASH_CS Y

13 HD10/Port 3.7 SCOPETRIG Y



Volume 2 Section 7INTERNAL/EXTERNAL

TIMING SPECIFICATIONSand FLOW DIAGRAMS

7.1 MICROPROCESSOR INTERFACE TIMING

For information, see the NEC Microprocessor Interface Timing Specification.

7.2 BUFFER INTERFACE TIMING

This section provides detailed infromation of the electrical characterstics and the timing of the buffers.

7.2.1 Electrical Characteristics and Recommended AC Operating ConditionsThe following diagrams show the behavior of buffer interface signals during read and write sessions to DRAMtype buffers.

Figure 7-1: DRAM Read Timing

RASN

tRC

CASN

BADD[9:0]

ROW COLUMN 2 COLUMN 3 COLUMN

tRAS

tCSH

tRP

tCRP tRCD tRSH

tCAS

tASR

tPC

PAGE MODENORMAL MODE

tRAD

tRAH

tCAH

tASC

tCP

COLUMN 1ROW

F. Haq 2/23/95

7.2 BUFFER INTERFACE TIMING 7.2.1 Electrical Characteristics and Recommended AC Operating



Figure 7-2: DRAM Write Cycle Timing

Figure 7-3: Refresh Timing

PAGE MODENORMAL MODE

RASN

tRC

CASN

BADD[9:0]

ROW COLUMN COLUMN COLUMN

tRAS

tCSH

tRP

tCRP tRCD tRSH

tCAS

tASR

tPC

tRAD

tRAH

tCAH

tASC

tCP

BDAT[15:0]

BLWEN/BHWEN

tWP

tWCS tWCH

tDS tDH

tDHR

DIN 1 DIN 2 DIN 3

ROW COLUMN

DIN 0

B. Stewart 11/3/94

RASN

CASN

tCHR

tCPT

tRAS

tRP

tRPC

tCSR

7.2 BUFFER INTERFACE TIMING 7.2.2 Buffer Delay Margins



7.2.2 Buffer Delay MarginsTable 7-1 summarizes the delay margins between the ASIC design and the NEC DRAM specifications. aspublished in the 1995 NEC DRAM Data Book.

Table 7-1: 60 nSec. EDO DRAM Delay Margins

BUFFER AC PARAMETERS

Ivory DELAY VALUES

DESIGNSPEC.

MARGIN

Min. Max. Min. Max.

BUFFER READ CYCLE

tRC (RAS cycle) 120 120 104 16 16

tRP (RAS pulse width) 45 45 40 5 5

tRAS (Width of RAS) 75 75 60 15 15

tCAS (Width of CAS) 11 19 10 1 9

tRCD (from neg edge RAS to neg edge CAS) 45 45 14 31 31

tRSH (from neg edge CAS to pos edge RAS) 30 30 10 20 20

tCSH (from neg edge RAS to pos edge CAS) 60 60 40 20 20

tCRP (from pos edge CAS to neg edge RAS) 60 60 5 55 55

tASR (addr setup time for neg edge RAS) 45 45 0 45 45

tRAH (addr hold time for neg edge RAS) 30 30 10 20 20

tASC (addr setup time for neg edge CAS) 15 15 0 15 15

tCAH (addr hold time for neg edge CAS) 11 19 10 1 9

tRAD (from neg edge RAS to valid col addr) 30 30 12 18 18

tRAL (from valid col addr to pos edge RAS) 45 45 30 15 15

tCP (CAS pulse width in page mode) 11 19 10 1 9

tPC (CAS cycle in page mode) 30 30 25 5 5

BUFFER WRITE CYCLE

tRC (RAS cycle) 120 120 104 16 16


tRAS (Width of RAS) 75 75 60 15 15

tCAS (Width of CAS) 11 19 10 1 9

tRCD (from neg edge RAS to neg edge CAS) 45 45 14 31 31

tRSH (from neg edge CAS to pos edge RAS) 30 30 10 20 20

tCSH (from neg edge RAS to pos edge CAS) 60 60 40 20 20

tCRP (from pos edge CAS to neg edge RAS) 60 60 5 55 55

tASR (addr setup time for neg edge RAS) 45 45 0 45 45

tRAH (addr hold time for neg edge RAS) 30 30 10 20 20

tASC (addr setup time for neg edge CAS) 15 15 0 15 15

tCAH (addr hold time for neg edge CAS) 11 19 10 1 19

tRAD (from neg edge RAS to valid col addr) 30 30 12 18 18

tRAL (from valid col addr to pos edge RAS) 45 45 30 15 15

tCP (CAS pulse width in page mode) 11 15 10 1 9

tPC (CAS cycle in page mode) 30 30 25 5 5

tDS (data setup time for neg edge CAS) 45 45 0 45 45

tDH (data hold time for neg edge CAS) 11 19 10 1 9

tWCS (from neg edge WEN to neg edge CAS) 45 45 0 45 45

tWCH (from neg edge CAS to pos edge WEN) 30 30 10 20 20

7.2 BUFFER INTERFACE TIMING 7.2.2 Buffer Delay Margins



7.3.1.3 Buffer Read CyclesFigure 7-4 shows the read cycles of the BFR block with an internal clock to register read data for the DRAMprotocol. Additional internal delay is provided on the BDAT input path to ensure sufficient hold time to clock inthe data. It is assumed that the DRAM OEN (output enable) pin is always active.

Figure 7-4: DRAM Reads For 2 Channels

tWP (width of WEN) 75 75 10 65 65

tCWL (from neg edge WEN to pos edge CAS) 45 45 10 35 35

tRWL (from neg edge WEN to pos edge RAS) 75 75 10 65 65

tWRC (from neg edge RAS to pos edge WEN) 75 75 10 65 65

BUFFER REFRESH CYCLE

tRC (RAS cycle) 120 120 104 16 16


tCSR (from neg edge CAS to neg edge RAS) 15 15 5 10 10

tCHR (from neg edge RAS to pos edge CAS) 60 60 10 70 70

tRPC (from pos edge RAS to neg edge CAS) 75 75 5 70 70

tCP (CAS pulse width in refresh cycle) 75 75 18 57 57

Table 7-1: 60 nSec. EDO DRAM Delay Margins (Continued)

BUFFER AC PARAMETERS

Ivory DELAY VALUES

DESIGNSPEC.

MARGIN

Min. Max. Min. Max.

Programmable

Programmable

Programmable

BRAS

BCAS

BDAT

DATA READ CLK(Inside BFR)

CHANNEL 1 CHANNEL 2

7.4 1394 TIMING DIAGRAMS 7.4.1 TRANSACTION LAYER And ASIC INTERFACE TIMING



7.4 1394 TIMING DIAGRAMS

7.4.1 TRANSACTION LAYER And ASIC INTERFACE TIMING

Figure 7-5: Transaction Layer Writes to SDRAM (HBRSTENA = 0)

SDRAMCLK

BADD

BDAT

RASN

CASN

DMGH

DMGL

HREG

HACK

HRD_WRN

HMODE[3:0]

HBRSTENA

WEN

T. Nguyen 7/30/97

R.Addr C.Addr

Data

IDLE

R.Addr C.Addr

Data

tdhold (2 ns)

(2 ns)tdsu

SELECTED POINTERS




Writes To SDRAM

Figure 7-6: Transaction Layer Writes to SDRAM (HBRSTENA = 1)

SDRAMCLK

BADD

BDAT

RASN

CASN

DMGH

DMGL

HREG

HACK

HRD_WRN

HMODE[3:0]

HBRSTENA

WEN

T. Nguyen 7/30/97

R.Addr C.Addr

Data

IDLE

tdhold (2 ns)

(4 ns)tdsu

SELECTED POINTERS

C.Addr C.Addr C.Addr C.Addr C.Addr C.Addr C.Addr

Data DataData Data Data Data Data




Reads to SDRAM

Figure 7-7: Transaction Layer Reads To SDRAM (HBRSTENA = 0)

IDLE IDLE

R.ADD C. ADD R.ADD C. ADD

DATADATA

SDRAMCLK

BADD

BDAT

RASN

CASN

DMGH

DMGL

HREG

HACK

HRD_WRN

HMODE[3:0]

HBRSTENA

WEN

SELECTED POINTERS

T. Nguyen 7/30/97

tdsu

tdhold (2 nS)

(4 nS)

CAS Latency = 3 CAS Latency = 3




Figure 7-8: Transaction Layer Reads To SDRAM (HBRSTENA = 1)

SDRAMCLK

BADD

BDAT

RASN

CASN

DMGH

DMGL

HREG

HACK

HRD_WRN

HMODE[3:0]

HBRSTENA

WEN

R.Addr C.Addr

Data

IDLE

tdhold (2 ns)

(4 ns)tdsu

C.Addr C.Addr C.Addr C.Addr C.Addr C.Addr C.Addr

Data DataData Data Data Data Data

CAS Latency = 3

SELECTED POINTERS









Appendix AAV Transfer Protocol

A.1 THEORY OF OPERATION

The ownership of SDRAM bus, including clock and control signals, are transferred between ASIC 1and ASIC 2. Thehand shaking is executed through the signals hreq, hack, and cke. The following diagrams illustrate this operation:

Figure A-1: SDRAM Bus

ASIC 1

SDRAM

hreqClock (100MHz)hackcke

ASIC 2



Figure A-2: Clock Timing

clock

hreq

hack

cke

sdrclk

Ivory/Indigo GenesisIvory/Indigo

DOCUMENT NUMBER REVISION SHEETR.C. Ayeras Preliminary (a) 8/22/01 544 OF 571

Numerics10-bit interface 48810-bit symbols 48911 276AT IF Bits

SECPERCYL 165fmt2bfr_sectsize/ 3671394 Operating Mode bit (TEST Read Only) 2761394_ack 3641394_brst 3641394_dir 3641394_en 3641394_req 364Auto Write Rollover Bits 48BFR Bits

Lobound_addr/ 62Auto Write Reload Address 49Auto Write Rollover Address 48

AT IF Bitsardlba 161

BFR BitsFormatter Rollover Address 53

AT IF BitsBCHDEVCTL_ALTSTAT 175

wt_value 685-bit mode servo burst demodulation 4906burst global err ena bit (DSS) 218ECC Bits

RLBA2 119BFIR Bits

Lobound_addr/ 61BFR Bits

Host Address 46ECC Bits

EHIST 121BFR Bits

CPUS Next Read Address 67(AT IF) Bits

wdxfrcntr 154BFR Bits

Prefetch Next Address 708-bit mode for backward compatibility 488DSS Bits

sinvalx 248

AAborted Command bit (AT IF) 149Aborted Command bit (ATIF) 171Aborted Command Mask bit (AT IF) 151abortnow bit (FMTR) 89abortxfr bit (FMTR) 89, 95Accelerate/Once Around Mode bit (MTR) 253Accumulated Error Number History Register (ECC) 121accumulated error reset bit (ECC) 118Accumulated Sector In Error Counter Register (ECC) 120Accumulated Uncorrectable Sector Count Register (ECC) 121Add HNS CWS register 201Add to Current Read Sectors Register (AT IF) 144Add to Current Write Sectors Register (AT IF) 143Add To Loop Count At Pointer Value Register (TA) 108Add to Loop Counter register (TA) 107ADDCRS bits (AT IF) 144ADDCWS[7:0] (AT IF) 143addcwspend bit (HNS) 201addcwsval bits (HNS) 201addlup_ptr bit (TA) 107

addlupfail_ptr bit (TA) 107addlupfaile_ptr bit (TA) 107addr_sel[2:0] 364addv[13:0]

369ADRGEN Control Register (BFR) 61Agent Request bits (BFR) 59agent_seq bit (BFR) 58All Done bit (ECC) 124All Error Number bits (ECC) 121All Errors in ECC bit (ECC) 122Allocate mode bit (HNS) 200allocvldoena bit (HNS) 190alloreuse bit (HNS) 200Always Preload Buffer Pointer bit (ATIF) 173AM Search Delay Register (FMTR) 83AM Timeout Register (FMTR) 82AM678SEL bits (DSS) 233amtimout bit (FMTR) 92, 95AMTOL bits (DSS) 233Any Error bit (ECC) 122anyerrorint bit (FMTR) 94APLL1 Bypass bit (Clock/APLL) 284APLL1 Power Down bit (Clock/APLL) 284, 286APLL1 Reset bit (Clock/APLL) 284APLL1 VCO Frequency Range bit 285APLL1 VCO Frequency Range Select bits (Clock/APLL) 286apll1sel66 bit (CLK/APLL) 283APLL2 Bypass bit (Clock/APLL) 284APLL2 Power Down bit (Clock/APLL) 284, 286APLL2 Reset bit (Clock/APLL) 284APLL2 VCO Frequency Range bit 285APLL2 VCO Frequency Range Select bits (Clock/APLL) 286Arbiter Control Registers (BFR) 58Arbiter Status Low Register (BFR) 59Arbiter Status Registers (BFR) 59Arm Auto Read bit (AT IF) 146ASIC Reset Register (CLK/APLL) 283async ref_req bit (BFR) 76AT Hardware Reset bit (ATIF) 170AT Hardware Reset Last bit (ATIF) 170AT I/O Cell Power Down Enable Low Register (Test/Debug) 277AT IF Bit

Force DMARQ 180AT IF Bits

Aborted Command 149, 170Aborted Command Mask 151addcrs[7:0] 144addcws[7:0] 143Always Preload Buffer Ptr 173ardlba[15:8] 161ardlba[27:0] 161ardlba[27:24] 161ARIRQ Enable 145Arm Autoread 145ashdw_lbamode 163ashdwcmd[7:0] 164ashdwcylinder[15:0] 164ashdwcylinder[15:8] 164ashdwhead[3:0] 163ashdwseccnt[7:0] 164ashdwsecnum[7:0] 163AT Hrdwr Reset 170AT Sftwr Reset 170ATHR Last 170ATSR Last 170AUTO 148


Auto Arm Autoread 145Auto Read Miss 144Auto Read Needs Service 149Auto Read Started 149Auto Write Needs Service 149Auto Write Started 149AutoRead Enable 146AutoRead Enable (read only) 145AutoRead Needs Service 151AutoRead Srvcd (read only) 144AutoRead Started Mask 151AutoWrite Needs Service 151AutoWrite Srvcd (read only) 144AutoWrite Started Mask 151AWIRQ Enable 145BCH Enable 178BCH Enable DMARQ 178BCH Error 150BCHCMD_STAT[1:0] 177BCHCMD_STAT[3:2] 177BCHCYLHI[1:0] 177BCHCYLHI[3:2] 177BCHCYLL0[1:0] 176BCHCYLLO[3:2] 176BCHDEVCTL_ALTSTAT[1:0] 175BCHDRVHD[1:0] 177BCHDRVHD[3:2] 177BCHFEATR_ERR[1:0] 175BCHFEATR_ERR[3:2] 175BCHSECCNT[1:0] 176BCHSECCNT[3:2] 176BCHSECNUM[1:0] 176BCHSECNUM[3:2] 176bfr2hst_fifo_words[7:0] 154bfrdone 154blkcnt[7:0] 156Blksize > CWS Mask 151Blocksize Greater than CWS 150Buffer Disable 180Buffer Ptr Preload Enable 173Busy 168Clear Busy 169Clear DRQ 169Clear IRQ14 169clrfifoeerr[7:0] 155Command Queue 148Command Queue Full Mask 152Corrected 168CRC Enable 157CRC Error 150CRC Error Mask 152crcvalue[15:0] 174CRS Decrement Error 144CRS Invalid (read only) 163CRS Overflow Error 144CRS[14:8] 143CRS[7:0] 143crsgesc (read only) 163CWS [7:0] 142CWS Decrement Error 144CWS Invalid (read only) 163CWS Overflow Error 144CWS[14:8] 142cwsgesc (read only) 163dackn 179dackn assert 179

dackn assert mask 179dackn de-assert 179dackn de-assert mask 179DASP In 172DASP Out 172Data ECC 170Data Mark 170DD_PUEN 173DD7_PU EN 173Decrement Queue Counter 159DEV 162Device DMA Enable 170Diag Enable 147DIB Compare Enable 159DIB Enable 159DIB Error Mask 151DIB LBA Error 150DIB MemFail Error 150DIB Memfail Error Mask 151DIB Reset 159diblbaerr_lba[15:0] 160diblbaerr_lba[15:8] 160dibmferr_lba[15: 0] 160dibmferr_lba[15:8] 160disable abort 157Disable AutoCHS Command 145Disable CHS Increment 148DMA 148DMACKn Test 180DMACONFIG [1:0] 171dmareqo 179DMARQ Output Enable 148DMARQ Test 180dmarqena 179Dont Deccrs 173Dont UPD ARCHS 173Drive ID 170, 172Drive Ready 168DRQ 168emptyctl[2:0] 154Enable DMA Delay 145End of Command Mask 151EOC 150EOC Needs Service 150, 151Error 168Exclude DevCtl BCH 178Exclude Reserved Bits 178FIFO Empty 154FIFO Empty + 1 154FIFO Error 150FIFO Full 154FIFO Full - 1 154FIFO Overrun Error 154FIFO Underrun Error 154fifordyctl[2:0] 155firmware DMARQ 180Firmware IORDY 180Force IODRY 180Format Enable 147fullctl[2:0] 154GFHRSTN 173GFIORN ENA 173GFIOWN ENA 173headroll[3:0] 165HNS Interrupt Mask 152HNS Mark Mask 152Host Reserved Bits 178


HSTCMD [7:0] 169hstcylinder [7:0] 162hstcylinder[15:8] 162HSTFEATR[7:0] 170hsthead[3:0] 162hstseccnt [8] 163hstseccnt[8:0] 162hstsecnum[7:0] 161ID Not Found 170Inc CHS 169Increment Queue Counter 159Index 168Interrupt Delay Done 150Interrupt Delay Done Msk 151INTRQ Disable 170intseccnt[7:0] 168IOCONCLP 173IORDY Address Only 171IORDY Inhibit 171IORDY Timeout Inhibit 171IPE Bad Block 170irqdlycntr[7:0] 159LAST 148LBA [15:8] 166LBA [23:16] 166LBA [27:0] 165LBA [27:24] 166LBA Mode 162Load AUTORD LBA 169logecccnt[5:0] 153Logical LONG 148Loop Interrupt 150Loop Interrupt Enable 148Loop Interrupt Mask 151MAXCHSLBA[15:8] 167MAXCHSLBA[23:16] 167MAXCHSLBA[27:0] 167MAXCHSLBA[27:24] 167MAXLBA[15:8] 166MAXLBA[23:16] 166MAXLBA[27:0] 166MAXLBA3 Maximum LBA 3 166MULTIPLE 148New Command 149New Command Mask 151Over Max LBA 150Over Max LBA Mask 151PDIAG In 172PDIAG Out 172phyecccnt[6:0] 153Physical LONG 148POR Last 170Power Down Enable 174Pseudo Slave Mode 171rdirqdly[7:0] 158Read DMA Enable 147Read Multiple Enable 147Read Sectors Enable 147Read XFR Done 149Read XFR Done Mask 151Reset Interrupt 174Reset Interrupt Mask 174sdma 3.5 157sdmamode[2:0] 157sdmaxfr 157SECCNT > CRS (read only) 144

SECCNT > CWS (read only) 144seclstena 148SECPERCYL [11:0] 165SECPERTRK [7:0] 165secroll[7:0] 164sectsize[8:0] 152sectsize[8] 152Seek Complete 168Set Busy 169Set DRQ 169Set IRQ14 169shdwcws[11:8] 145shdwcws[7:0] 145Slavebsyn 172Sleep Mode 174smctl[4:0] 156smstop[4:0] 156smv[7:0] 156Spare Logic Input (clk) 180Spare Logic Input (gclk) 180Status Read by Host 149Status Read by Host Mask 151Stop Enable 156test deccrs 180test deccws 180Test FIFO Words 181Test Interrupt (Wr Only) 181testdataxfr 180Track 0 170TriDASP 173trptime[4:0] 158Ultra Force DMARQ 180Ultra Force IORDY 180uP Pause 157uP Stop at Zero CS 157uP Stop Now 157wdxfrcntr[8:0] 153wrirqdly[7:0] 159Write Buffer Enable 147Write DMA Enable 147Write Fault 168Write Long Enable 147Write Multiple Enable 147Write Sectors Enable 147Write Verify Enable 147WRRDN 148XFER Active (read only) 142, 143XFR Active (read only) 163

AT Interface Configuration Register 171AT Interface see AT IFAT Soft Reset Last bit (ATIF) 170AT Software Reset bit (ATIF) 170ATA Clock Register (CLK/APLL) 281ATA Clock Select bits (CLK/APLL) 282ATA_Emulation 352ATA_Emulation_Test 353ATA_PC_Debug 353ATA_Standalone 352ATA_Standalone_Debug 353ATANMINT_AVCLOCK pin signal 340ATIF Bits

MAXLBA[27:24] 167Atlas Core Processor Clock Register 279Auto Allocate bit (HNS) 186Auto Arm Auto Read bit (AT IF) 146AUTO bit (AT IF) 148Auto Control Register (AT IF) 145


Auto Enable Register (HNS) 186Auto incremented uP Address bit (DSS) 230Auto Mark bit (HNS) 186auto page change bit (BFR) 57Auto Partial Transfer bit (HNS) 186Auto Read Address Register 47Auto Read Address Register - High Byte Register (BFR) 47Auto Read Address Register - Page Register (BFR) 48Auto Read Enable bit (AT IF) 147Auto Read Enable bit (ATIF Read Only) 146Auto Read Enable Register (AT IF) 146Auto Read IRQ14 Enable bit (AT IF) 146Auto Read LBA1-4 Registers (AT IF) 161Auto Read LBA2 Register (AT IF) 161Auto Read LBA3 Register (AT IF) 161Auto Read LBA4 Register (AT IF) 161Auto Read Miss bit (AT IF) 144Auto Read Needs Service bit (AT IF) 149Auto Read Needs Service Mask bit (AT IF) 151Auto Read Serviced bit (AT IF) 145Auto Read Started bit (AT IF) 149Auto Read Started Mask bit (AT IF) 151Auto Read Transfer (Full Hit) bit (HNS) 186Auto Reuse Buffer bit (HNS) 186Auto Reuse LBA bit (HNS) 186Auto Scan bit (HNS) 186Auto Shadow Command bits (ATIF) 164Auto Shadow Command Register (AT IF) 164Auto Shadow Cylinder High Registe (AT IF) 164Auto Shadow Cylinder Low Register (AT IF) 164Auto Shadow Cylinder Number [15:0] bits (AT IF) 164Auto Shadow Cylinder Number [15:8] bits (AT IF) 164Auto Shadow Head Number bits (AT IF) 164Auto Shadow Head Number Register (AT IF) 163Auto Shadow LBA Mode bit (AT IF) 163Auto Shadow Sector Count bits (ATIF) 164Auto Shadow Sector Count Register (AT IF) 164Auto Shadow Sector Number bits (AT IF) 163Auto Shadow Sector Number Register (AT IF) 163Auto Trim bit (HNS) 186Auto Write Address Register - High Byte (BFR) 48Auto Write Address Register - Page (BFR) 48Auto Write Address Register (BFR) 48Auto Write IRQ14 Enable bit (AT IF) 145Auto Write Needs Service bit (AT IF) 149Auto Write Needs Service Mask bit (AT IF) 151Auto Write Register [23:0] (BFR) 48Auto Write Reload Register (BFR) 49Auto Write Reload Register [15:8] Bits (BFR) 49Auto Write Reload Register [23:16] Bits (BFR) 49Auto Write Reload Register Page (BFR) 49Auto Write Rollover Address Register (BFR) 48Auto Write Rollover Page Register (BFR) 49Auto Write Rollover Register [15:8] bits (BFR) 48Auto Write Rollover Register [23:16] Bits (BFR) 49Auto Write Serviced 174Auto Write Serviced bit (AT IF) 144Auto Write Started bit (AT IF) 149Auto Write Started Mask bit (AT IF) 151auto_pg_chg bit (BFR) 58autord update bits (BFR) 50autowrupdate bit (BFR) 50AV Read Wait Count Register (UPI Offset 7) 292AV RESET bit (UPI) 293AV Write Wait Count Register (UPI Offset 6) 291AV-ASIC 340

AVINT bit (UPI) 293AVPASIC 340Awconflict bit (HNS) 189

BBCH Command-Status Register (AT IF) 177BCH Control Register (AT IF) 178BCH Cylinder HighRegister (AT IF) 177BCH Cylinder Low Register (AT IF) 176BCH Device Control/Alternate Status Register (AT IF) 175BCH Drive Head Register (AT IF) 177BCH Enable (AT IF) 178BCH Enable DMARQ (AT IF) 178BCH Error bit (AT IF) 150BCH Feature/Error Register (AT IF) 175BCH Sector Count Register (AT IF) 176BCH_ERR_STATUS[0] bit (AT IF) 178BCH_ERR_STATUS[1] bit (AT IF) 178BCH_ERR_STATUS[2] bit (AT IF) 178BCH_ERR_STATUS[3] bit (AT IF) 178BCH_ERR_STATUS[4] bit (AT IF) 178BCH_ERR_STATUS[5] bit (AT IF) 178BCH_ERR_STATUS[6] bit (AT IF) 178BCH_ERR_STATUS[7] bit (AT IF) 178BCHCMD_STAT[1:0] bits (AT IF) 177BCHCMD_STAT[3:2] bits (AT IF) 177BCHCYLHI[1:0] bits (AT IF) 177BCHCYLHI[3:2] bits (AT IF) 177BCHCYLL0[1:0] bits (AT IF) 176BCHCYLLO[3:2] bits (AT IF) 176BCHDEVCTL_ALTSTAT[1:0] bits (AT IF) 175BCHDEVCTL_ALTSTAT[3:2] bits (AT IF) 175BCHDRVHD[1:0] bits (AT IF) 177BCHDRVHD[3:2] bits (AT IF) 177BCHFEATR_ERR[1:0] bits (AT IF) 175BCHFEATR_ERR[3:2] bits (AT IF) 175BCHSECCNT[1:0] bits (AT IF) 176BCHSECCNT[3:2] bits (AT IF) 176BCHSECNUM[1:0] bits (AT IF) 176BCHSECNUM[3:2] bits (AT IF) 176bclk off bit (BFR) 62bcqentry/awptr bits (HNS) 190bcqflags[2:0] (HNS) 191BCV 405BCV AM Control Register 233BCV AM Error bit (DSS) 232BCV AM Pattern Register 232BCV Bad bit (DSS) 232BCV bit (FMTR) 90BCV Control 1 Register (DSS) 233BCV Control 2 Register 234BCV Correction Off bit (DSS) 233BCV dat err bit (DSS) 232BCV data and quality 490BCV Data bit (DSS) 226BCV disable 2-bit pad bit (DSS) 219BCV ECC [4:0] (DSS) 234BCV enable bit 233BCV Error bit (DSS) 234BCV field 407BCV Not Ready bit (DSS) 234BCV Status For Synchronous Servo register 232BCV Timeout bit (DSS) 226BCV time-out bit (DSS) 232BCV567 Select bits (DSS) 233BCVDATA[6:0] (DSS) 233Beavis/µP Interface Timing 311, 519


Beavis/Buffer Host Read Timing 310, 518Beavis/Buffer Host Write Timing 310, 518BEMF Window Threshold [5:0] 255BEMF Window Threshold Register (MTR) 255BFR Bits

adr_decode 62agent_seq 58arb_decode 62async ref_req 76auto page change 57Auto Read Address [15:8] 47Auto Read Address [23:16] 48Auto Read Address [7:0] 47Auto Write Address [15:8] 48Auto Write Address [23:16] 48Auto Write Address Register[23:0] 48Auto Write Reload Address [23:16] 49Auto Write Rollover Address [23:16] 49auto_pg_chg 58autord update 50autowr update 50bclk_off 62bfr overrun 70bfr_oerr 50, 54bfr_uerr 50, 54Burst _length 61C_spare[3:0] 67cas latency 56chg_req_hi 73chng_reg_med 73Code Range End Address[24:13] 69Code Range End Address[24:21] 69Code Range Start Address [24:17] 68Code Range Start Address[16:9] 68CPUB Next Address [24:1] 69CPUB Next Address [24:17] 69CPUB Next Address [8:1] 69cpub underrun 70cpub_ decode 63cpuback 59cpubreq 59, 70cpubrst critical threshold[4:0] 71cpubrst high threshold [4:0] 71cpubrst high threshold[2:0] 71cpubrst medium threshold[4:0] 71CPUS Next Rd Addr [24] 67CPUS Next Read Address [15:8] 67CPUS Next Read Address [23:1] (BFR) 67CPUS Write Addr 2 [24] 67CPUS Write Address 1 [15:8] 66CPUS Write Address 1 [22:1] 66CPUS Write Address 2 [15:8] 66CPUS Write Address 2 [22:1] 66CPUS Write Address 2 [23:16] 66cpus_ decode 63cpusack 59cpusreq 59, 68critical threshold[4:0] 53crt_req_lev[2:0] 51crt_req_lev[4:0] 51curr_acc_ length[0] 57curr_acc_lenth [2:1] 57curr_agent_num 59curr_agnt_num 57Current Agent Address [15:8] 60Current Agent Address [21:0] 60

Current Agent Address [21:16] 60Current Agent Number[2:0] 60current sequential 57Current[5:0] 51current_access_type 57data_decode 62Data_errs 72data_req 54dcacherw 56debug_int_clr 61def_cli_req 75defadr[16:1] 73defadr[24:17] 74defect enable 75defrldhi [16:9] 74defrldpg[22:9] 74dfq_decode 63dfqreq 59DIB_errs 72dram_ decode 62dram_state machine state bits [15:9] 57dram_state machine state bits[7:0] 57dram_state machine state[18:0] 57drdtp 56dwrtp 56ecc_decode 63ecc_enable 72ecc_sel_ack 72eccack 59ECCAGNTSM[5:0] 71ECCCoradr [15:0] 72ECCCoradr [15:8] 72eccreq 59, 72exceed_ limit 92FIFO empty 70FIFO full 70FIFO reset 55fifo_empty 50, 54Fifo_flush 71fifo_full 50, 54fmtack 59fmtg_cli_req 75fmtqentry[5:0] 75Fmtr. Q Enable 75fmtr_decode 62fmtr_oerr 54fmtr_uerr 54fmtragterrclr 55fmtrqbasehi [16:9] 74fmtrqbasepg [24:9] 74fmtrreq 59Formatter Address [16:9] 52Formatter Address [24:1] 52Formatter Address [24:17] 52Formatter Address [8:1] 52Formatter DIB page[12:0] 54Formatter DIB page[7:0] 54Formatter Enable 55Formatter Reload Address [24:17] 53Formatter Reload Address [24:9] 53Formatter Rollover Address[24:9] 53Formatter Transfer Count [11:0] 54Formatter Transfer Count [11:8] 54fq_dfack 59gate_svoint 68Hibound_addr[15:8] 62high threshold[2:0] 53


high threshold[4:0] 53high_req_lev[4:0] 51hldoff_t_ldval[7:0] 55Host Address [23:16] 46Host Address Register [23:0] 46Host Enable 50Host Reload Address [23:16] 47Host Reload Register [15:8] 47Host Rollover Address[22:8] 46Host Rollover Register [22:16] 47Host Transfer Count Register [8:0] 49hst_decode 62hst_oerr 50hst_rst 50hst_uerr 50hstack 59hstreq 50, 59init_req 56Lobound_addr[7:0] 62med_req_lev[4:0] 51medium threshold[4:0] 53nt_cntchng 68o_bspare[3:0] 63Pending Refresh Count [6:0] 76pg_chng 58Prefetch Enable 71Prefetch Next Address [24:17] 70Prefetch Next Address [8:1] 70Prefetch Next Address[24:1] 70ref_decode 63refreq 59Refresh Count [7:0] 75Refresh Enable 76Refresh Now 76reqout 59rfack 59sdram_ type 61sector_req 54sel_agent 58selfscan_mode 61sft_rst 62Spare [3:0] 51start_ack 55start_req 55TA Enable 64TA FIFOempty 64TA FIFOfull 64TA Overrun 64TA Sector Size 64TA Underrun 64ta_crt_req_lev[4:0] 64TA_CURR_PTR[15:0] (BFR) 65TA_CURR_PTR[23:16] (BFR) 65ta_decode 62ta_fftst 64TA_FIFO_Clr 64TA_fifo_errclr 64ta_hi_req_lev[2:0] 63ta_hi_req_lev[4:3] 64ta_med_req_lev[4:0] 63ta_sce_ unlrn 64taack 59tareq 59, 64Thermal Asperity Base Address [15:8] 63Thermal Asperity Base Address [23:16] 63Thermal Asperity Base Address[23:0] 63

Thermal Asperity Request Count 64tras 56trc 56trcd 56trp 56upif_decode 62wt_value[4:0] 68xfr_lnth 58xfr_typ 58

bfr overrun bit (BFR) 70BFR To Host FIFO Words Register (AT IF) 154bfr_oerr bit (BFR) 50, 55bfr_uerr bit (BFR) 50, 54bfr2csn_awptr[19:0] 369bfr2def_ack 368bfr2def_fq_data

[15:0] 369bfr2def_fq_data[15:0] 368bfr2ecc_ack 366bfr2ecc_data 366bfr2ecc_done 366bfr2ecc_req 366bfr2ecc_staddr 366bfr2fmtr_data[15:0] 367bfr2fmtr_oerr 367bfr2fmtr_oerr bit (FMTR) 95bfr2fmtr_sect_ack 367bfr2fmtr_uerr 367bfr2fq_ack 369bfr2hnbs_ensect 369bfr2hns_ld_sectstrt 369bfr2hst_fifo_words[6:0] 364bfr2hst_oerr 364bfr2hst_uerr 364bfr2ta_uerr bit (FMTR) 95bfr2upi_dram_data [15:0] 362bfr2upi_waitclr 362bfrclk 366

BFR block 330ECC block 334FMTR block 328

bfrclk1fBFR block 331

bfrdone 506bfrfault bit (ECC) 119bfrstop No synopen bit (ECC) 115bifr2TA_oerr 369bi-phase method of data coding 406bits (BFR) 68BLKCNT[7:0] bits (ATIF) 156Block Count Register (AT IF) 156Blocksize Greater Than CWS bit (AT IF) 150Blocksize Greater than CWS Mask bit (AT IF) 151BRSTARDYN bit (DSS) 235BRSTBRDYN bit (DSS) 236BRSTCAL 416BRSTCRDYN bit (DSS) 236, 238BRSTDRDYN bit (DSS) 237, 245BRSTERDYN bit (DSS) 246BRSTFRDYN bit (DSS) 239, 247brstreq 362brstshft bit (DSS) 235BRSTXARDYN bit (DSS) 243BRSTXBRDYN bit (DSS) 244BRSTXCRDYN bit (DSS) 245btr2hst_data[15:0] 364btr2hst_sect_ack 364


Buffer Clock Delay Control 288Buffer Clock Register (CLK/APLL) 280Buffer Clock Select bits (CLK/APLL) 281Buffer Correction disabled bit (ECC) 115Buffer Delay Margins 302, 510Buffer Disable bit (ATIF) 181Buffer Done bit (AT IF) 155Buffer mark mode bit (HNS) 201Buffer Pointer Shadow Register (HNS) 197Buffer Read Cycles 303, 511Buffer Read Pointer Preload Enable bit (ATIF) 173buffer reuse bit (HNS) 200Buffer Size Offset Register (HNS) 192Buffer Test 1 Register (BFR) 62Buffer Test 2 Register (BFR) 63Buffer Test 3 Register (BFR) 63bufmark2x bit (HNS) 200Burst A register (DSS Read Only) 243Burst A register (DSS) 235Burst B register (DSS Read Only) 244Burst B register (DSS) 236Burst C register (DSS Read Only) 244Burst C register (DSS) 236, 238Burst Control Register (SVO) 235Burst D register (DSS Read Only) 245Burst D register (DSS) 237Burst E’ Register (DSS Read Only) 246Burst F register (DSS) 238Burst F’ Register (DSS Read Only) 246burst Length bits (BFR) 61Burst Reader State machine 415burst_wait_clk_inv bit (UPI) 290BURSTAHI bits (DSS) 235BURSTBHI bits (DSS) 236BURSTCHI bits (DSS) 237BURSTDHI bits (DSS) 238BURSTEHI bits (DSS) 238BURSTFHI bits (DSS) 239BUSY bit (ATIF) 168byteclk 506

CC_Spare[3:0] bits (BFR) 67Cache Miss bit (HNS) 188Cache Scan Clock Register (CLK/APLL) 283Cache Scan Clock Select bit (CLK/APLL) 283Cache Scan Enable bit (AT IF) 148CacheScan/Buffer Interface signal definitions 369Calculator Inter Sector Gap Register 81Calculator State machine (CALSM) 431Calculator Symbols Per Spoke Register (FMTR) 80calsm[2:0] (FMTR) 97calunderun bit (FMTR) 95Can’t Allocate bit (HNS) 188Can’t Mark bit (HNS) 189CAS latency[1:0] bits (BFR) 56checksum_err bit (FMTR) 92checksumena bit (FMTR) 90chg_req_hi bit (BFR) 73chg_req_md bit (BFR) 73Chunk sync 405chunksync low qual bit (DSS) 227Cleanup Done bit (HNS) 188Clear Busy bit (ATIF) 169Clear DRQ bit (AT IF) 169Clear FIFO Error Register (AT IF) 155

Clear IRQ14 bit (ATIF) 169Clear Shock bit (DSS) 219CLK Invert bit (UPI) 290CLK Invert Completed bit (UPI) 290clk66

MOTOR block 327CLKOUT Driver Enable bit (TMUX) 276Clock/APLL Bits

APLL password[7:0] 284APLL1 Bypass 284APLL1 Power Down 284, 286APLL1 Reset 284APLL1 VCO Frequency Range Select 286apll1sel66 283APLL2 Bypass 284APLL2 Power Down 284, 286APLL2 Reset 284APLL2 VCO Frequency Range Select 286ATA Clk sel[1:0] 281Cache Scan Clock Sel 283Core clock select 279ECC Clock Control 280ECC Clock Select[1:0] 280Emulator clock control 279Emulator clock select 279Emulator Clock Status 279External clock 1 control 280, 281External Clock 2 Control 282, 283External clock 2 control 280, 281External clock2 control 279M Value[4:0] 287M1 Value[4:0] 285, 287M2 Value[2:0] 286Motor Clock Control3 282Motor Serial Clk sel[1:0] 282Motor Serial Clock Control1 282N1 Value[2:0] 285N1 Value[6:0] 287N2 Value[2:0] 285N2 Value[6:0] 288P Value[2:0] 287P1 Value[2:0] 285, 287P2 Value[2:0] 286R/W Channel Clk Ctrl 283r1 285r2 285Reset APLL Clocks 283Servo Clock 1 Select[2:0] 281Servo Clock 2 Select [1:0] 281Servo Clocks Ctrl 281Soft Power On Reset 283uP Core Clock Status 279

CLRSFATSPK bit (DSS) 218cmdqstopint bit (FMTR) 94cnt100r[3:0] (UPI) 291cnt100w[3:0] (UPI) 291cnt40r[5:0] (UPI) 290cnt40w[5:0] (UPI) 290cnt66r[3:0] (UPI) 291cnt66w[3:0] (UPI) 291Code Range End Address Register (BFR) 69Code Range Start Address Register (BFR) 68Command Control High Register (AT IF) 148Command Control Low Register (AT IF) 148Command Enable High Register (AT IF) 147Command Enable Low Register (AT IF) 147Command Queue bit (AT IF) 149


Command Queue Full Mask bit (AT IF) 152Command Queue Stop Pointer 433Command Register (FMTR) 88Commands Done Status bit 433Commutation Phase register 254Compare Window Enable Control bit (MTR) 254Configuration High Register (FMTR) 90Configuration Register (FMTR) 89Configuration Register 0 (HNS) 189Configuration Register 1 (HNS) 189Continuous Test bit (MTR) 259Control Register UPI (Offset 0) 289corbsy bit (ECC) 120Core Clock Freq Select bits (CLK/APLL) 279Core Status Register (BFR) 59coreclk

V850E CORE 339corrdoneint bit (FMTR) 94Corrected bit (ATIF) 169Corrected write data 506Correction DRAM_addr 506Corrupted read data 506cos signxA bit (DSS) 249cos signxB bit (DSS) 249cos signxC bit (DSS) 248cos signxE bit (DSS) 248cos signxF bit (DSS) 248Cos Value For Burst A register (DSS) 239Cos Value For Burst B register 240Cos Value For Burst D register 241Cos Value of burst’ Register (DSS Read Only) 247Cos Value register (DSS) 242COSVALHI bits (DSS) 242Counter Prescale Register [5:0] (MTR) 255CountLBA bit (ECC) 116countLBA bit (ECC) 134CPU Burst Acknowledge bit (BFR) 59CPU Burst Control Register (BFR) 70, 71cpu burst critical threshold bits (BFR) 71cpu burst high threshold bits (BFR) 71cpu burst medium threshold bits (BFR) 71CPU Burst Next Address Register - Page (BFR) 69CPU Burst Next Address Register (BFR) 69cpu burst request bit (BFR) 70CPU Burst Request Level Control Register (BFR) 71CPU Single Acknowledge bit (BFR) 59CPU Single Control Register (BFR) 68CPU Single Next Read Address - Page High Register (BFR) 67CPU Single Next Read Address - Page Low Register (BFR) 67CPU Single Next Read Address Register [23:1] (BFR) 67CPU Single Next Read Address Register High (BFR) 67CPU Single Next Read Address Register Low (BFR) 67CPU Single Request bit (BFR) 68CPU Single Status Register (BFR) 68CPU Single Write Address 1 bits (BFR) 66CPU Single Write Address 1 Register - High Byte (BFR) 66CPU Single Write Address 1 Register - Page (BFR) 66CPU Single Write Address 1 Register (BFR) 66CPU Single Write Address 2 [22:1] (BFR) 67CPU Single Write Address 2 [23:16] bits (BFR) 67CPU Single Write Address 2 Register - High Byte (BFR) 66CPU Single Write Address 2 Register - Page High (BFR) 67CPU Single Write Address 2 Register - Page Low (BFR) 66CPU Single Write Address 2 Register (BFR) 66cpub underrun bit (BFR) 70CPUS Next Read Address [24] bit (BFR) 67

cram entry bits (HNS) 189cram entry number bits (HNS) 188Cram Ready (RO) bit (HNS) 196CRC Enable bit (AT IF) 157CRC Error bit (AT IF) 150CRC Error Mask bit (AT IF) 152CRC Value Registers (AT IF Read Only) 174critical error threshold bits (ECC) 115critical flag reset bit (ECC) 117CRS Decrement Error bit (AT IF) 145CRS Greater than or Equal to Sector Count bit (ATIF Read

Only) 163CRS Invalid bit (ATIF Read Only) 163CRS Overflow Error bit (AT IF) 145CRS Status Register (AT IF) 144CRS[14:8] (AT IF) 143CRS[7:0] bits (ATIF) 143crt_req_lev bit (BFR) 51csn2bfr_hstadr 369curr_acc_ length[0] (BFR) 57curr_acc_lenth [2:1] (BFR) 57curr_agent_num bits (BFR) 59curr_agnt_num bits (BFR) 57Current Agent Address [22:0] bits (BFR) 60Current Agent Address Register (BFR) 60Current Agent Address Register High (BFR) 60Current Agent Address Register- Page Register (BFR) 60Current Agent Number [2:0] (BFR) 60Current Agent Number Being Serviced Register (BFR) 60Current LBA Low Register (HNS) 195Current LSA Register (FMTR, Read Only) 97Current Marked bit (HNS) 188Current Pointer Register (TA) 109Current Read Sectors High Register (AT IF) 143Current Read Sectors Low Register (AT IF) 143current sequential bit (BFR) 57Current Write Sectors Decrement Error 171, 172Current Write Sectors High Register (AT IF) 142Current Write Sectors Low Register (AT IF) 142Current Write Sectors Overflow 171, 173Current Write Sectors Status Register 145, 164, 180, 181Current Write Sectors Status Register (AT IF) 144current_access_type bits (BFR) 57current_pointer bit (TA) 109CWS bits (AT IF) 142CWS Decrement Error bit (AT IF) 144CWS Greater than or Equal to Sector Count bit (ATIF Read

Only) 163CWS Invalid bit (ATIF Read Only) 163CWS Overflow Error bit (AT IF) 144CWS[11:8] AT IF 143

Ddackn assert bit (AT IF) 179dackn assert mask bit (AT IF) 179dackn bit (AT IF) 179dackn de-assert bit (AT IF) 179dackn de-assert mask bit (AT IF) 179DASP Input bit (ATIF Read Only) 172DASP Output bit (ATIF) 172Data Bus Bit 7 Pull Up Enable bit (AT IF) 173Data Bus Pull Up Enable bit (AT IF) 173DATA ECC bit (ATIF) 171Data Error Number bit (ECC) 121Data errs bits (BFR) 72Data Integrity Block, DIB 493Data Mark bit (ATIF) 171


data width 489Data_Request bits (BFR) 54DC Erase bit (DSS) 227DC erase field 406dcachrw bits (BFR) 56Dcerase_qualification mode 405Debug Address High Control Register 0 (BFR) 62Debug Address High Control Register 1 (BFR) 62Debug Address Low Control Register 0 (BFR) 61Debug Address Low Control Register 1 (BFR) 62debug bit (BFR) 61DEBUG INT bit (UPI/Proc) 294debug_int_clr bit (BFR) 61decoder done bit (ECC) 122Decoder Status High Register (ECC) 122Decoder Status Low Register (ECC) 121Decrement Write Command Queue Counter bit (AT IF) 159Decrement/Increment Write Command Queue Register (AT IF) 159def cli req bit (BFR) 75def2bfr_req 368defadr[8:1] 73defect enable bit (BFR) 75defect management 504Defect State machine (DFSM) 431Defect Table Address [24:17] (BFR) 74Defect Table Address Register - Page (BFR) 74Defect Table Address Register (BFR) 73Defect Table Reload Address High [16:9] bits (BFR) 74Defect Table Reload Address Register (BFR) 74Defect Table Reload Page Address[24:17] bits (BFR) 74Defect/Buffer Interface signal definitions 368defectunderun bit (BFR) 95Detect mode bit (HNS) 201Device bit (AT IF) 162Device DMA Enable bit (ATIF) 170dfctena bit (FMTR) 89Diag Enable bit (AT IF) 147DIB and DATA Errors Register (BFR) 72DIB Check bit (ECC) 116, 134DIB Control bits (ECC) 116DIB Control Register (AT IF) 159DIB Dummy bit (ECC) 116, 134DIB Enable bit (AT IF) 160DIB error bit (ECC) 124DIB Error Mask bit (AT IF) 151DIB errs bits (BFR) 72DIB Force bit (ECC) 116, 134DIB Generation bit (ECC) 134DIB in Buffer bit (ECC) 134DIB Internal Status Register 134DIB LBA Error bit (AT IF) 150DIB LBA Error Latched LBA High Register (AT IF) 160DIB LBA Error Latched LBA Register (AT IF) 160DIB Memory Error Latched LBA Register (AT IF Read Only) 160DIB Memory Fail Error bit (AT IF) 150DIB Memory Fail Error Mask bit (AT IF) 151DIB Read Operation 116DIB Reset bit (ATIF) 159DIB Write Operation 116DIBerror bit (ECC) 122DIBrd fault bit (ECC) 120DIBwrfault bit (ECC) 120didreuse bit (HNS) 200direqwr 506direqwr bit (FMTR) 89DIS_SERLCLK bit (MTR) 263

Disable Abort bit (AT IF) 157Disable Auto CHS Command bit (AT IF) 146Disable CHS Increment bit (AT IF) 149disable error counter bit (ECC) 118Disable LoadSA bit (HNS) 189Disable/Brake Phase Output Control bit 253Disk Active bit (HNS) 198Disk Scan 505Disk Word Starting Address Level 1 Register (ECC) 123Disk Word Starting Address Level 2 Register (ECC) 123Disk Word Starting Address Level 3 Register (ECC) 123DISSERCLK (MTR) 263diswg bit (FMTR) 89DMA bit (AT IF) 148DMA Configuration bits (ATIF) 171DMA Request/Acknowledge Status Register (AT IF) 179DMACK Test bit (ATIF Read Only) 180DMACKN interrupt Status Mask Register (AT IF) 179DMACKN Interrupt Status Register (AT IF) 179dmareqo bit (AT IF) 179DMARQ Output Enable bit (AT IF) 148DMARQ Test bit (ATIF Read Only) 180dmarqena bit (AT IF) 179Don’t Decrement CRS Control Bit (ATIF) 173Don’t Update Auto Read CHS Register bit (ATIF) 173don’t_load syndrome bit (ECC) 118Double Error bit (DSS) 232double-burst ECC algorithm 504dozena bit (FMTR) 85DRAM 361DRAM Interface Control Register (BFR) 56DRAM Interface Status Register (BFR) 55DRAM Read Timing 300, 508DRAM Reads For 2 Channels 303, 511DRAM State Machine 1 States Register (BFR) 57DRAM State Machine 2 States Registers 57DRAM State Machine Timing Control Register (BFR) 56DRAM Write Timing 301, 509dram_state machine state[19:0] (BFR) 57drdtp bit (BFR) 56DRIVE ID bit (ATIF) 170Drive ID bit (ATIF) 172Drive ID/Slave Busy Register (AT IF) 172Drive Ready bit (ATIF) 168Driver Interrupt Threshold [5:0] (MTR) 255Driver Interrupt Threshold Register (MTR) 255DRQ bit (ATIF) 168DSS BIts

cos signxB 248DSS Bits

6burst global err ena 218AM678SEL 233AMTOL 233Auincaddr 230BCV Bad 232BCV Correct Off 233BCV Dat 226BCV dat err 232BCV Data [6:0] 233BCV data fault delay 225BCV disable 2 bit pad 218BCV ECC[4:0] 234BCV Enable 233BCV Error 234BCV not ready 234BCV time-out 226, 232BCV time-out fault delay 225


BCV567sel 233BCVAM error 232BCVAM[7:0] 232brstardyn 235brstbrdyn 236brstcrdyn 236brstdrdyn 237brsterdyn 238brstfrdyn 239brstshft 235brstxardyn 243brstxbrdyn 244brstxcrdyn 245brstxerdyn 246brstxfrdyn 247bursta[11:0] 235burstb[11:0] 236burstc[11:0] 236burstd[11:0] 237burste[11:0] 238burstf[11:0] 239burstxa[11:0] 243burstxb[11:0] 244burstxc[11:0] 244burstxd[11:0] 245burstxe[11:8] 246burstxf[11:0] 246chunksync low qual 227chunksync quality fault delay 226clear servo fault at spoke 218clear shock 218cos signxA 248cos signxA through F bits 248cos signxC 248cos signxD 248cos signxE 248cosval bursta[11:0] 239cosval burstb[9:0] 240cosval[9:0] 242cosvalx[11:0] 247dc erase 227dc erase fault delay 226Double Error 232Enab Int 208Enable Sector TImer 208End Sector Time endtim[12:0] 209Find Mode 217flags[3:0] 231FMTR Done 218Force 227force brstrdy 235force servo fault error 217Forced fault window 218Formatter Spoke [12:0] 214Freeze Sector Timer 218head compare ena 217head dat err 226head dat err fault delay 225head miscomp 226head miscomp fault delay 225headcomp[3:0] 217Load Sector Timer Delay [7:0] 212lsb dat err 226lsb dat fault delay 225lsb miscomp 227lsb miscomp fault delay 226

lsb soft err 227lsb soft err fault delay 226LSB4bit 217lsbcmpen[1:0] 217lsbnum[3:0] 216Map 217mapflt 226mask global BCV Dat error 220mask global BCV time-out 221mask global chunksync quality 222mask global head dat err 220mask global head miscomp 220mask global lsb miscomp 222mask global lsb soft err 222mask global mapflt 220mask global SAM low qual 221mask global SAM time-out 221mask global shock 220mask global speed 220mask global spoke num miscomp 221mask global TA 220mask global track dat err 221mask global track miscomp 221mask global track soft err 222Mask shockfault shock 223mask svofault BCV Dat err 223mask svofault BCV time-out 223mask svofault chunksync quality 224mask svofault dc erase 224mask svofault head dat err 223mask svofault lsb dat err 223mask svofault lsb miscomp 224mask svofault lsb soft err 224mask svofault preamble 224mask svofault SAM low qual 223mask svofault SAM time-out 223mask svofault speed 223mask svofault spoke num dat err 223mask svofault spoke num miscomp 223mask svofault TA 223mask svofault track dat err 223mask svofault track miscomp 223mask svofault track soft err 224Maximum Spoke Number [7:0] 215New Sector Timer Value newstval[12:0] 210Offsena 211preamble 227preamble det 231preamble fault delay 226Preamble_low 219PRS Spoke Compared History[15:0] 216prs spoke ena 218PRSPOLY[7:0] 215Restart WCS 231RWgate_ ena 218SAM low qual 226SAM low qual fault delay 225SAM timeout 226SAM time-out fault delay 225SAM to SAM Time samtosam[12:0] 212Sector Timer Snapshot Value [12:0] 213self-servo write enable 218Servo Interrupt Off Time[12:0] 210Servo Interrupt Time [12:0] 208shock 226Shock fault stop Formatter 231shock pol 218


sin signxA 248sin signxA through F bits 248sin signxB 248sin signxC 248sin signxD 248sin signxE 248Single Error 232sinval bursta[11:0] 239sinval burstb[9:0] 240sinval[9:0] 243sinvalx[11:0] 247Skip Carry [6:0] 213Skip ena 218skip first SAM 217Skip[6:0] 234Soft err control[1:0] 219speed 226speed fault delay 225speedhib[7:0] 220speedlob[5:0] 220spknum[7:0] 215spoke gate 231spoke mask[7:0] 215spoke num dat 226spoke num dat fault delay 225spoke num miscomp 226spoke num miscomp fault delay 225spoke soft reset 218Sync. Global Error or 0 228Sync. Global Error or bit 15 228Sync. SAM found 231Sync. Servo fault 231Sync. svo fault stop fmt 231TA 226TA fault delay 225TA in Burst 231, 237, 239, 245, 247TAinBCV 234test brstcal 235Test Clock 234Test Load 234test mode 234testaddr[5:0] 231Times Up Reload Value timeup[7:0] 208Times Up Time timuptim[12:0] 210Track Comp En[1:0] 219track dat err 226track dat fault delay 225track miscomp 226track miscomp fault delay 225Track Number A Compare Value[15:0] 229Track Number B Compare Value[15:0] 229track soft err 227track soft err fault delay 226TRACKID16 218trknum[14:0] 228uP rdwcsena 230vheadnum[3:0] 216vmask global dc erase 222vmask global force 222vmask global preamble 222vmask global spoke num dat err 221vNew Skip Value[6:0] 213vSpoke Counter [7:0] 214vvmask global lsb dat err 220WCS ena 231wcsaddr[5:0] 230

wcsdat[15:0] 230Zero Phase Start 231

dwrtp bit (BFR) 56

EECC Acknowledge bit (BFR) 59ecc action bit (ECC) 117ECC Address Map 111ECC Agent State Machine State Register 71ECC Bits

accumulated error reset 117all done (3rd Level) 124allerrnum[3:0] 121any error 121bfrfault 119bfrstop Nosynopen 115Buffer Correction Disabled 115corbsy 119CountLBA 116countLBA 134critial error flag reset 117critical error flag 135dataerrnum[3:0] 121DIB Check 116DIB check 134DIB Dummy 116, 134DIB error 124DIB force 116, 134DIB Generation 116DIB generation 134DIB in Buffer 134DIB In Buffer Ena 116DIBerror 121DIBrd fault 119DIBwrfault 119disable error counter 117dont_load syndrome 117dskadr1[15:8] 123dskadr1[23:8] 123dskadr2[15:8] 123dskadr2[23:8] 123dskadr3[15:8] 123dskadr3[19:8] 123EACC [11:0] 120EACC [7:0] 120ecc action 117ecc fault 124eccerror 119eccfault 121eccxc0 [7:0] 133eccxc0[10:0] 133eccxc1[10:0] 133eccxc1[7:0] 133eccxc2[10:8] 133eccxc2[7:0] 133econmod 117econmod enable 115EHIST [15:0] 121error 124error in ecc 121, 124error threshold [4:0] 115erruncorrclr 117EUNCORR [7:0] 121fault clear 117FIFO test mode 117Firmware Correction 115Firmware Status clr 117


fwfault 119LBAfault (DIB error read) 119mcritical error threshold 115memfault 119miscorr-fault 119Multi Media Support 115Mux Select 117No. DIB Errors 119Number of Symbol errors in Data and XC 124Number of Word Errors [4:0] 124PLBA [15:0] 118preloadn 115Pseudo LBA Value [15:0] 118Pseudo LBA Value [7:0] 118raw uncorrectable 124raw-uncorr 121RLBA1 [15:0] 119RLBA1 [7:0] 119RLBA2 [15:0] 119Sector LBA Number [15:0] 122Sector LBA Number [7:0] 122, 125, 126soft reset 117Stack 10 Sector LBA Number [15:0] 125Stack 11 Sector LBA Number [15:0] 125Stack 12 Sector LBA Number [15:0] 126Stack 2 Sector LBA Number [15:0] 125Stack 20 Sector LBA Number [15:0] 126Stack 21 Sector LBA Number [15:0] 126Stack 22 Sector LBA Number [15:0] 126Stop on 1st Uncorr err 115synclose 119syndrome open 117tdata[15:0] 134tdata[7:0] 134total error number 124uncorrectable error 121, 124uncorrfault 119W/R 121, 124xcerror 119

ECC Block I/O 494ECC Clock Register (CLK/APLL) 280ECC Clock Select bits (CLK/APLL) 280ECC Control Register (BFR) 72ECC Control Register 0 (ECC) 116ECC Control Register 1 (ECC) 117ECC Control Register 2 (ECC) 118ECC Correction Address - High Byte Register (BFR) 72ECC Correction Address Register (BFR) 72ECC Cross Check Syndrome 1 Register (ECC) 133ECC Cross Check Syndrome 2 Register (ECC) 133ECC Cross Check Syndrome register (ECC) 133ECC Fault bit (ECC) 122, 124ECC On The Fly Disable (LEO Mode) Operation 504ECC On The Fly Enable Operation 501ECC polynomial 493ECC Request bit (BFR) 72ECC Request Level High Register (BFR) 73ECC Request Level Low Register (BFR) 73ECC Stack 01 Register (ECC) 124ECC Stack 02 Register (ECC) 125ECC Stack 10 Register (ECC) 125ECC Stack 11 Register 125ECC Stack 12 Register (ECC) 126ECC Stack 20 Register (ECC) 126ECC Stack 21 Register (ECC) 126ECC Stack 22 Register (ECC) 126

ECC Status Register (BFR) 72ECC Status Register 0 (ECC) 119ecc_enable bit (BFR) 73ecc_sel_ack bit (BFR) 72ecc2bfr_caddr 366ecc2bfr_data 366ecc2bfr_ndaterr 366ecc2bfr_ndiberr 366ecc2bfr_rdwrn 366eccack 506eccclk

ECC block 333eccdisable bit (FMTR) 90eccdone 502eccdout 506eccen 506eccerrdet 507eccerrdetint bit (FMTR) 94eccerror bit (ECC) 120eccfault bit (FMTR) 92eccfaultdone 507eccreq 505eccrun 507ecctime 506Eight/Twelve Pole Mode bit (MTR) 253Embedded Read Channel bit (UPI) 293Embedded Read Channel Version bits (UPI) 293Emulator Clock Control bit (CLK/APLL) 279Emulator Clock Register (CLK/APLL) 279Emulator Clock Select bits (CLK/APLL) 280Emulator Clock Select Enable bit (CLK/APLL) 279Emulator Clock Status bit (CLK/APLL Read Only) 279EMULCLK pin signal 339enaanyerror bit (FMTR) 93Enab Int bit (DSS) 208Enab Sector Timer bit (DSS) 208Enable AV Clock Output bit (TMUX) 276Enable AV Clock Pullup bit (TMUX) 276Enable DMA Delay bit (AT IF) 146Enable to read back WCS RAM bit (DSS) 230enacmdqstopnt bit (FMTR) 93enacorrdone bit (FMTR) 93enaeccerrdet bit (FMTR) 93enafmtstop bit (FMTR) 93enataafteram bit (FMTR) 93enatabefoream bit (FMTR) 93enataexceedlimit bit (FMTR) 93enauncorrdone bit (FMTR) 93encodmod enable bit (ECC) 115enconmod bit (ECC) 118End Formatter Queue Pointer Register (TA) 107End of Command bit (AT IF) 150End of Command Mask bit (AT IF) 152End of Command Needs Service bit (AT IF) 150End of Command Needs Service Mask bit (AT IF) 152End Sector time 410End Sector Time Register 209Endec bypass mode 404ENDOFSPOKE_DELAY Register 87ENDOFSPOKE_DELAY Register (FMTR) 87endptr bits (TA) 107entry [5:0] (HNS) 187Entry Requested [4:0] (HNS) 196Entry Valid bit (HNS) 199errclr bit (FMTR) 89Error bit (ATIF) 169Error bit (ECC) 124


Error Clear bit (BFR) 71Error location 0 bits (ECC) 132Error Mask Register (FMTR) 91Error Register (FMTR) 92error threshold bits (ECC) 115erruncorrclr bit (ECC) 117exceed limit bit (FMTR) 92Exclude DevCtl BCH (AT IF) 178Exclude Reserved Bits 9AT IF) 178External Busy Status Register (UPI Read Only Offset B) 292External Clock 1 Control bit (CLK/APLL) 280, 281, 282External Clock 2 Control bit 279External Clock 2 Control bit (CLK/APLL) 280, 281, 283External Clock 2 Control bit (Clock/APLL) 282

Ffault clear bit (ECC) 118ffdone bit (FMTR) 95FIFO 55FIFO Empty +1 bit (AT IF) 155FIFO Empty bit (AT IF) 155FIFO Empty bit (BFR) 50FIFO empty bit (BFR) 70FIFO empty control bits (AT IF) 154FIFO Error bit (AT IF) 150FIFO Full - 1 bit (AT IF) 155FIFO Full bit (AT IF) 155FIFO Full bit (BFR) 50FIFO full bit (BFR) 70FIFO full control bits (AT IF) 154FIFO Overrun Error bit (AT IF) 155FIFO Ready Control bits (AT IF) 155FIFO Ready Control Register (AT IF) 155FIFO Reset bit (BFR) 55FIFO Status Control Register (AT IF) 154FIFO Status Register (AT IF) 154FIFO Test Mode bit (ECC) 117FIFO Underrun Error bit (AT IF) 155Fifo_flush bit (BFR) 71Find Mode bit (DSS) 217Firmware Correction bit (ECC) 115firmware DMARQ bit (AT IF) 180Firmware fault bit (ECC) 119Firmware Force State Machine Register (HNS) 195Firmware IORDY bit (AT IF) 180Firmware Status clr bit (ECC) 117First LSA Of The Track register 87First LSA To Transfer Register (TA) 106Flag Reserve bit (HNS) 198FLAGS bits (DSS) 231Flags register 231Flags Shadow Register (HNS) 198Flags Shadow Register Clear (HNS) 199Flash output mode 404fm2bfr_dibenable 367fmt2bfr 367fmtbusy bit (FMTR) 95Fmtena bit (BFR) 55fmtg cli req bit (BFR) 75fmtq2bfr_naddr_ld 369FMTR Bits

abortnow 88abortxfr 88, 95amsearchdly[3:0] 83amtimout 92, 95amtimout[5:0] 82

anyerrorint 94bcv 89bfr2fmtm_uerr 95bfr2ta_verr 95bfrzfmtr_oerr 95calcisg[7:0] 81calsm[2:0] 97calunderun 95checksum_err 92corrdoneint 94currentlsa[15:8] 97currentlsa[7:0] 97datasize [7:0] 82datasize[12:0] 82defect_ underun 95dfctena 88direqwr 88diswg 88dozena 85eccdisable 89eccerrdetint 94eccfault 92enaanyerror 93enacmdqstopnt 93enacorrdone 93enaeccerrdet 93enafmtstop 93enata befoream 93enata exceed limit 93enataafteram 93enauncorrdone 93endofspoke_delay[7:0] 87errclr 88ffdone 95fmtbusy 95fmtreset 88fmtrslp 89fmtrsm[3:0] 97fmtstart 88fmtstopint 94forcedoze 85fqidle 95iboffena 85ignpreflt [3:0] 81incpage_ ena 89indexcnt[3:0] 96indextimout 92indxtoena 89lupcnt0 95maskwg 89maxindex [3:0] 81maxsplit[12:0] 84maxsplit[7:0] 84maxsplitena 89minsplit[7:0] 85minsplitena 89moving_ avg 90nextlsa[15:0] 96nextlsa[7:0] 96nobufxfr 89numtacnt[7:0] 105ovlaprgena 89ovlp_amsearchdly[5:0] 86ovlprgrestart_adj[3:0] 84ovlprgstop[5:0] 84pabspk[2:0] 86pfacthiwr 89


pllafter-wdgena 90pllaftrwdg[5:0] 88postamblereg[4:0] 87preaflt 95preafltena 89q_paused 95rd_svo_ after_ bcvwr 90rdisgreg[7:0] 83rdskipadj[5:0] 82rgdlayreg[7:0] 83scan_rep_cntr_reg[2:0] 101scanhold[7:0] 101scanhold[9:0] 101scanlimit[7:0] 100scanlimit[9:0] 100secsize [12:8] 80secsize [7:0] 80sectrans[10:0] 88sectrans[7:0] 88sectrdns_invalid 88selfscan 89selfscan0_1[15:0] 98selfscan2_3[15:0] 98selfscan4_5[15:0] 98selfscan8_7[15:0] 99selfscan8_9[15:0] 99selfscanA_B[15:0] 99selfscanC_D [15

0] 100selfscanC_D[15:0] 100selfscanE_F [15:0] 100selfscanE_F[15:0] 100seriousflt 92settledone 88skewreg[7:0] 85skpllreg[5:0] 81startfq 88stopamtimout 91stopatlimit 91stopchecksum 91stopeccerrflt 91stopfq 88stopindexto 91stoppreaflt 91stopseriousflt 91stopsvofltrd 91stopsvofltwr 91stopwgwedge 91svoflterr [1:0] 92symbolcntr[12:0] 97Symbolcntr[7:0] 97sympwdg [12:0] 80sympwdg [7:0] 80taafteram 94tabefoream 94tacthird 89taexceedlimit 94tarecmax[7:0] 105testena 96testforceam 96testload 96testrg 96testwg 96trak1stlsa[15:0] 87uncorrdoneint 94wdsecsize[11:0] 86

wdsecsize[7:0] 86wgextend[7:0] 87wgpreaerr 92wgunderwg 92wrisgreg[7:0] 83wrpll[5:0] 81xtermode 90

FMTR Done bit (DSS) 218FMTR Holdoff Timer Register (BFR) 55Fmtr. Cmd. Queue Current Entry Register (BFR) 75fmtr_oerr bit (BFR) 54fmtr_uerr bit (BFR) 54fmtr2bfr_data_xfer 367fmtr2bfr_fifo_rst 367fmtr2bfr_sect_req 367fmtr2btr_data[15:0] 367fmtragterrclr bit (BFR) 55fmtreset bit (FMTR) 89fmtrslp bit (FMTR) 90fmtrsm[3:0] bits (FMTR) 97FMTRSPK bits (DSS) 214fmtstart bit (FMTR) 89fmtstopint bit (FMTR) 94Force bit (DSS) 227Force Brstrdy bit (DSS) 235Force DMARQ bit (AT IF) 180force doze bit (FMTR) 85force hns reset bit 195force host read command bit (HNS) 196force host write cmd bit (HNS) 195Force IODRY bit (AT IF) 180force no xfer read bit (HNS) 195force scan room bit (HNS) 195Force Sequencer State[2:0] (MTR) 254Force Servo fault bit (DSS) 218force special read (no transfer) bit (HNS) 195Forced Fault Window bit (DSS) 218Format Enable bit (AT IF) 147Formatter Acknowledge bit (BFR) 59Formatter Address [22:1] bits (BFR) 52Formatter Address page [22:1] 52Formatter Address Register 52Formatter Address Register (BFR) 52Formatter Cmd. Queue Enable bit (BFR) 75Formatter Command Queue Address bits (BFR) 75Formatter Command Queue Address Register (BFR) 74Formatter Command Queue Control Register 75Formatter Command Queue Status Register (BFR) 75Formatter Command Queue/Defect Acknowledge bit (BFR) 60Formatter Control Register (BFR) 55Formatter DIB Page Register (BFR) 54Formatter FIFO Empty bit (BFR) 54Formatter FIFO Full bit (BFR) 54Formatter Interrupt status bit (UPI) 293Formatter Queue Interface signal definitions 369Formatter Reload Address Register (BFR) 53Formatter Reload Page bits (BFR) 53Formatter Request Level Control Register (BFR) 53Formatter Rollover Address Register (BFR) 53Formatter Rollover Page bits (BFR) 53Formatter Spoke Register (DSS) 214Formatter State machine (FMTRSM) 431Formatter Status Register (BFR) 54Formatter Transfer Count Register (BFR) 54Formatter/Client Interface 367Foundry bits (UPI) 293fq2bfr_ptr [8:3] 369


fq2bfr_req 369fqidle bit (FMTR) 95FRMTSPK bits (DSS) 214Full Hit bit (HNS) 188FW Buffer Auto Write Register (HNS) 194FW Command LBA High Register (HNS) 193FW Command LBA Low Register (HNS) 193FW REQUEST CRAM ENTRY FOR R/W register 196FW Sector Count Register (HNS) 193FW Update bit (HNS) 198fwnoxfrd bit (HNS) 200fwpartw2 bit (HNS) 200fwvideord bit (HNS) 190fwvideosel bit (HNS) 190fwwrroom bit (HNS) 200FZSTTIMER bit (DSS) 219

GGalois Field 493gate_svoint bit (BFR) 68Gated Serial Clock bit (MTR) 260genesison bit (HNS) 189Glitch Filter on HRSTN Enable bit (ATIF) 173Global Error Mask Bits For Sync. Servo register 222Global Error Mask Bits for Sync. Servo register 220Global Error Mask bits for Sync. Servo register 221Global Errors 1 for Sync. Servo register 226Global Errors 2 for Sync. Servo register 226Global Errors 3 for Sync. Servo register 227Gray code 405grown defects 504

Hhand shaking 538HardSegmentation bit (HNS) 189hardware fault 503HD10_Port37 bitt (Test/Debug) 277HD11_Port22 bitt (Test/Debug) 277HD12_Port24 bitt (Test/Debug) 277HD7_Port39 bitt (Test/Debug) 277HD9_Port36 bitt (Test/Debug) 277Head Compare Enable bit (DSS) 217Head Compare Register (DSS) 217head dat err bit (DSS) 226head miscomp bit (DSS) 226Head Rollover bits (AT IF) 165Head Rollover Register (AT IF) 165headnum bits (DSS) 216hi_req_lev bit (BFR) 51High Buffer Pointer Offset Register (HNS) 192High Byte of Sin Value of X Register (DSS) 248High Byte of Sine Value of Burst Register (DSS) 248Hitachi Combo Interface 440hldoff_t_ldval bits[7:0] (BFR) 55hlowcrs bit (HNS) 189HNS Bits

addcwspend 201addcwsval[7:0] 201Allocate mode 200allocvldoena 189alloreuse 200Auto Allocate (For Writing) 186Auto Mark (For Writing) 186Auto Partial Transfer 186Auto Read Transfer 186Auto Reuse Bfr (For Writing) 186

Auto Reuse LBA (For Writing) 186Auto Scan 186Auto Trim (For Writing) 186Awconflict 189bcqentry/awptr[13:0] 190bcqflags[2:0] 191Buffer mark mode 200buffer reuse 200bufmark2x 200bufsizeo[14:0] 192Cache Miss 187Can’t Allocate 187Can’t Mark 189Cleanup Done 187Clear Disk Active 199Clear Flag Reserve 199Clear FW Update 199Clear Locked 199Clear Mark 199Clear Not Dirty 199Clear Release Interrupt 199Clear Unavailable 199Clear Video data 199Clear Write Pending 199cram entry number[5:0] 188cram entry[5:0] 188CRAM Ready (Read Only) 196current marked 188currlba[26:0] 195Detect mode 200didreuse 200Disable Load LSA 189Disk Active 198elease Entry 187Entry Requested[4:0] 196entry valid 198entry[5:0] 186Flag Reserve 198force hns reset 195force host read command 195force host write cmd 195force no xfer read 195force partial write 195force scan room 195Full Hit 187FW Update 198fwbufautowr[13:0] 194fwcmdlba[27:0] 193fwnoxfrd 200fwpartw2 200fwseccnt[15:0] 193fwvideosel 189fwwrroom 200genesison 189HardSegmentation 189highbptro[14:0] 192hlowcrs 189hnscws[13:0] 190hnslp 201hnssmctl[4:0] 203hnssmstp[4:0] 204hnsstpena 204hxferdone 189Just Mark 187LBA mark mode 200lbareus 200lcachedsect[13:0] 191


Locked 198lowbptro[13:0] 192lowbptroffset[15:8] 192Mark 198Mark active mode 200Mask Cache Miss 187Mask Can’t Allocate 187Mask Cleanup done 187Mask Full Hit 187Mask Just Mark 187Mask Partial Hit 187Mask Release 187Mask WrScanDn 187maxentryaddr[5:0] 186misslba [27:0] 187Partial Hit 187Rd transfer mode 200Read/-Wr 196Release Interrupt 198scanactive valid 186Scanactv mode 200sectorsavail[13:0] 200shdwbptr[13:0] 197shdwoffs[13:0] 198shdwsize[13:0] 197shdwstlba[26:0] 196shdwvalid[13:0] 196skip valid 188sleepena 201smentryaddr[5:0] 186srchlba[27:0] 194svbufautowr[13:0] 199testmuxsel1[4:0] 202testmuxsel2[4:0] 202Transfer active 200trgcount[13:0] 191Unavailable 198Video data 198video read ena 189Write Pending 198WrScanDn 187wrxpndena 189wvideord 189

HNS Buffer Write Command Que Flags Register (Read Only) 191HNS Buffer Write Command Queue Register 190HNS CWS Register 190HNS Interrupt Mask bit (AT IF) 152HNS Mark Mask bit (AT IF) 152HNS State Machine Control register 203HNS State Machine Stop Register 204hnslp bit (HNS) 201hnssmsct[4:0] (HNS) 203hnssmstp bits (HNS) 204hnsstpena bit (HNS) 204Host Acknowledge bit (BFR) 59Host Address Register - Low (BFR) 46Host Address Register - Page (BFR) 46Host Address Register bits [22:1] (BFR) 46Host Address Register High (BFR) 46Host Command Register (AT IF Read Only) 169Host Control Register (BFR) 50Host Cylinder Number [15:0] (AT IF) 162Host Cylinder Number [7:0] (AT IF) 162Host Cylinder Number [7:0] bits (AT IF) 162Host Cylinder Number High Register (AT IF) 162Host Cylinder Number Low Register (AT IF) 162

Host Device/Control Register (Read Only) 170Host Drive Head Number Register (AT IF) 162Host Enable bit (BFR) 50Host Error Register 170Host Features Register (AT IF) 170Host Head Number bits (AT IF) 162Host Interface Signal Descriptions 361Host Interrupt status bit (UPI) 293Host Reload bits [23:16] (BFR) 47Host Reload Register 47Host Reload Register - Page (BFR) 47Host Reload Register [15:9] bits (BFR) 47Host Request bit (BFR) 50Host Request Control Register (BFR) 51Host Reserved Bits (AT IF) 178Host Reset Interrupt Status bit (UPI) 293Host Rollover Address bit (BFR) 46Host Rollover Address Register (BFR) 46Host Rollover Register [23:16] (BFR) 47Host Sector Count [7:0] bits (AT IF) 162Host Sector Count bit-8 163Host Sector Count High Register (AT IF) 163Host Sector Count Low Register (AT IF) 162Host Sector Number bits (AT IF) 161Host Sector Number Register (AT IF) 161Host State Machine Register (BFR) 51Host Status Register (AT IF) 168Host Status Register (BFR) 50Host Transfer Count Register - High Byte (BFR) 49Host Transfer Count Register (BFR) 49hregrUdat 361hst_addr_ack 361hst_dat_ack 361hst_end_addr 361hst_oerr bit (BFR) 50hst_pg_chng 361hst_rd_dat 361hst_req_lev 361hst_rst bit (BFR) 50hst_seq_brst 361hst_strt_addr 361hst_uerr bit (BFR) 50hst_wr_dat 361hst_xfr_lnth 361hst_xfr_typ 361hst2bfr_cmd_datn 364hst2bfr_data[15:0] 364hst2bfr_data_xfer 364hst2bfr_sect size[8:0] 364hst2bfr_sect_req 364hst2bfr_wr_rdn 364hst2btr_acmd_pls 364hst2btr_fiforst 364hstclk 364hstreq 361hstsel 361hxferdone bit (HNS) 189

II/O Configuration Register (MTR) 264iboffena bit (FMTR) 85ICE 339ID Not Found bit (ATIF) 171Idle mode 402Idle wakeup/recovery 357Idle, Halt, and Stop 357ifclk1f


ATA block 335ifclk1g

ATA block 336ifclk2f

ATA block 337ignpreflt[3:0] (FMTR) 81Inc CHS bit (ATIF) 169Incpage_ena bit (FMTR) 90Increment Write Command Queue Counter bit (AT IF) 159Index bit (ATIF) 169Index Counter Register (FMTR Read Only) 96indextimout bit (FMTR) 92indxtoena bit (FMTR) 90init_req bit (BFR) 56Initial Lupcnt Register (TA) 109Inter Sector Gap for Read Register (FMTR) 83Inter Sector Gap for Write Register (FMTR) 83Interface Control Register (AT IF) 169Interface CRC Error Bad Block bit (ATIF) 171Internal Formatter States 1 Register (Read Only) 97Internal Sector Count Low Register (AT IF) 168Interrupt Delay Done bit (AT IF) 150Interrupt delay Done Mask bit (AT IF) 152Interrupt Mask 1 Register (AT IF) 151Interrupt Mask 2 Register (AT IF) 151Interrupt Mask 3 Register (AT IF) 152Interrupt Mask Register (FMTR) 93Interrupt Mask Register (HNS) 187Interrupt Register (FMTR) 94Interrupt Register (UPI Offset C) 293Interrupt Request Disable bit (ATIF) 170Interrupt Status 1 Register (AT IF) 149Interrupt Status 2 Register (AT IF) 150Interrupt Status 3 Register (AT IF) 150Interrupt Status Register (HNS) 187intseccnt[7:0] bits (AT IF) 168IO Control Register (AT IF) 173IO Interface Control Clamp bit (ATIF) 173IORDY Address Only bit (ATIF) 171IORDY Inhibit bit (ATIF) 171IORDY Timeout Inhibit bit (ATIF) 171IORN Glitch Filter Enable bit (ATIF) 174IOWN Glitch Filter Enable bit (ATIF) 174IRQ14 Delay Counter bits (AT IF) 159IRQ14 Delay Counter Register (AT IF) 159

JJUMP instructions 411Just Mark bit (HNS) 188

KK7 Read Cycle 299K7 Read/Write Cycle 298

LLAST bit (AT IF) 148Last Hit Entry Register (HNS) 186Last Marked Entry Register (HNS) 188LBA 493LBA mark mode bit (HNS) 201LBA Mode bit (AT IF) 162LBA Offset Shadow Register (HNS) 198LBAfault bit (ECC) 120lbareuse bit (HNS) 200LBS Number register (DSS) 216ldcrs0ena bit (HNS) 189

LEO Mode 504Leo mode 503Level 1 High Page Address 123line sparing technique 504Load AUTORD LBA bit (AT IF) 169Load Cached Sectors Register 191Load down counter bits (MTR) 263Load Sector Timer Delay Register 212Load Up and Down counters bit (MTR) 253lock/APLL Bits

Buffer Clock Select [1:0] 280Locked bit (HNS) 199Logical 153Logical Block Address 1-4 Register (AT IF) 165Logical Block Address 3 Register (AT IF) 166Logical Block Address 4 Register (AT IF) 166logical block addresses 504Logical ECC Count bits (AT IF) 153Logical ECC Count Register (AT IF) 153Logical ECC Count Register (ECC) 153Logical Long bit (AT IF) 148Logical Sector Address 493Logical Sector Address Manager (LSAM) 431Loop Counter register (TA) 106Loop Interrupt bit (AT IF) 150Loop Interrupt Enable bit (AT IF) 149Loop Interrupt Mask bit (AT IF) 151Low Buffer Pointer Offset Register (HNS) 192Low Byte of Burst C register 236lsb dat err bit (DSS) 226lsb miscomp bit (DSS) 227lsb soft error bit (DSS) 227LSB4bit (DSS) 217LSBCMPEN bits (DSS) 217LSBNUM bits (DSS) 216Lucent and NEC APLL Password Register 284Lucent APLL1 and APLL2 Frequency Control Register 285Lucent APLL1 and APLL2 Test Register 284Lucent APLL1 Frequency PM Control Register 285Lucent APLL2 Frequency PM Control Register 286lupcnt0 bit (FMTR) 95lupcount[10:8] bits (TA) 107lupint_invalid bit (TA) 106

MM Value bits (Clock/APLL) 287, 288M1 Value (APLL1) 285M1 Value bits (Clock/APLL) 285M2 Value bit (APLL) 286M2 Value bits (Clock/APLL) 285Main Serial Channel bit (MTR) 260Main Serial Transfer Busy bit (MTR) 260MAP bit (DSS) 217mapflt bit (DSS) 226Mark active mode bit (HNS) 200Mark bit (HNS) 199Mask Global BCV Dat Err bit (DSS) 221Mask Global BCV Time-out bit (DSS) 221Mask Global CHUNKSYNC Quality bit (DSS) 222Mask Global DCERASE bit (DSS) 222Mask Global Force bit (DSS) 222Mask Global Head Data Error bit (DSS) 221Mask Global Head Miscompare bit (DSS) 220Mask Global LSB Data Error bit (DSS) 220Mask Global LSB Miscomp bit (DSS) 222Mask Global LSB Soft Error bit (DSS) 222Mask Global Mapflt bit (DSS) 220


Mask Global PREAMBLE bit (DSS) 222Mask Global SAM Low Qual bit (DSS) 221Mask Global SAM Time-out bit (DSS) 221Mask Global Shock bit (DSS) 221Mask Global SPEED bit (DSS) 221Mask Global Spoke Num Dat Err bit (DSS) 221Mask Global Spoke Num Miscomp bit (DSS) 221Mask Global TA bit (DSS) 221Mask Global Track Dat Err bit (DSS) 222, 224Mask Global Track Miscomp bit (DSS) 222Mask Global Track Soft Error bit (DSS) 222Mask Shockfault Shock bit (DSS) 223Mask Svofault BCV Dat Err bit (DSS) 223Mask Svofault BCV Time-out bit (DSS) 224Mask Svofault CHUNKSYNC Quality bit (DSS) 225Mask Svofault DCERASE bit (DSS) 225Mask Svofault Head Data Error bit (DSS) 223Mask Svofault Head Miscompare bit (DSS) 223Mask Svofault LSB Data Error bit (DSS) 223Mask Svofault LSB Miscomp bit (DSS) 225Mask Svofault LSB Soft Error bit (DSS) 224Mask Svofault PREAMBLE bit (DSS) 225Mask Svofault SAM Low Qual bit (DSS) 224Mask Svofault SAM Time-out bit (DSS) 224Mask Svofault SPEED bit (DSS) 223Mask Svofault Spoke Num Dat Err bit (DSS) 224Mask Svofault Spoke Num Miscomp bit (DSS) 224Mask Svofault TA bit (DSS) 223Mask Svofault Track Miscomp bit (DSS) 224Mask Svofault Track Soft Error bit (SVO) 224maskwg bit (FMTR) 90Max Index and Ignore Preaflt Register (FMTR) 81Maximum LBA 1-4 Register (AT IF) 166Maximum LBA 3 Register (AT IF) 166Maximum LBA 4 Register (AT IF) 167Maximum LBA in CHS Mode Register (AT IF) 167Maximum LBA in CHS Mode Register 2 (AT IF) 167Maximum LBA in CHS Mode Register 3 (AT IF) 167Maximum LBA in CHS Mode Register 4 (AT IF) 167Maximum LBA2 Register (AT IF) 166Maximum Number Of Entry Addresses Register 186Maximum Split Register 84Maximum Spoke Number Register 215maxindex[3:0] (FMTR) 81maxsplitena bit (FMTR) 90med_req_lev bit (BFR) 51memfault bit (ECC) 119Memory Error Latched LBA High Register (AT IF) 160Mighty Interface 434Minimum Split Register (FMTR) 85minsplitena bit (FMTR) 89Miscellaneous Control Register (TMUX Offset 4) 276miscorrfault bit (ECC) 120Miss LBA Low Register 187Mode Bits (Test/Debug) 276Mode/Status Register (HNS Read Only) 200mode_cmd 402mode_ena 402Moray generation interface 489Motor 282Motor Block Interrupt Enable bit 253Motor Block Soft Reset bit 253Motor Block Test Mux 462Motor Chip Interfaces

Hitachi Combo 461Mighty 460

Qombo 460Motor Clock Control2 bit (Clock/APLL) 282Motor Clock Control3 bit (Clock/APLL) 282Motor Clock Register (Clock/APLL) 282Motor Clock Serial Control bit (CLK/APLL) 282Motor Commutation Logic 434Motor Core Control Register 1 252Motor Core Control Register 2 253Motor Interrupt Block 434Motor Main Serial Address Register 261Motor Main Serial Data Register 260Motor Phase Timing 315, 523Motor PWM Invert 253Motor PWM Logic 317, 525Motor PWM Logic Block 434Motor PWM Threshold [7:0] 256Motor Run Logic Timing 316, 524Motor see also MTRMotor Serial Clock Select bits (CLK/APLL) 282Motor Serial Data/Address bits 261, 262moving_avg bit (FMTR) 90MSC R/W Bit (MTR) 260mtq2bfr_ 369MTR Bits

Accelerate/ Once Around Mode 252BEMF Window Threshold [5:0] 255Brake Phase Output Control 253Compare Window Enable Control 253Continuous Test 259Counter Prescale [5:0] 255DIS_ SERCLK 263Disable Phase Output Control 253Driver Interrupt Threshold [5:0] 255Eight/ twelve Pole Mode 252Force Sequencer State [2:0] 254Gated Serial Clock 259LD_DN_CNTR[2:0] 263Load Up/Down Counters 252Main Serial Channel 259Main Serial Xfer Busy 259Motor Block Interrupt Enable 253Motor Block Soft Reset 253Motor Main Serial Address[4:1] 261Motor Main Serial Address[7:1] 261, 262Motor Main Serial Data[7:0] 260Motor PWM Invert. 252Motor PWM Threshold [7:0] 256MSC R/W bit 259MTRICSEL[1:0] 264Pass Through Enable 253PESPWM Invert 255PESPWM Threshold [7:0] 258PWM Auto Update Enable 257PWM Tiiming Value [11:0] 257PWM Value [13:0] 257Qom_mtrint_sel 258Read Sense Phase [2:0] 254Read Stop 259Read/Write 261, 262Run Count State 254Run Or Commutation Enable 253Sample Test 259SC1_MSCLK[1:0] 264SC2_MSDAT[1:0] 264SC3_MSENA[1:0] 264sel_Smode 258SENU Lead edge 255


SENU_RW[1:0] 265SENV_NST[1:0] 265Serial Address Size 259SIPWM_div 258Smode_oe 258State Advance Threshold Bits [5:0] 255Test Mux Control[2:0] 252Test Out Mux High [15:8] 259Test Out Mux Low [7:0] 259Top Level State Control 253VCM Ser Xfer Busy 259VCM Serial Channel 259VCMSERDAT[15:0] 262VIPWM half clock control 256VIPWM Invert 252VIPWMH Threshold Value [5:0] 256VIPWMH_SVDAT & VIPWML & SIPWM 265VIPWML Duty Cycle Control [1:0] 256Watchdog Timer Access Control[15:14] 264Watchdog Timer Password[13:0] 263WD_POL 263WDCNTR[15:0] 262WDCNTR[15:8] 263WDENA 263WDTST 263

mtrclk1gMOTOR block 327

mtrclk2gMOTOR block 328

MTRICSEL[1:0] 265Multi Media Support bit (ECC) 115MULTIPLE bit (AT IF) 148Multiword DMA Timing 309, 517Mux Selection bits (ECC) 117

NN Value bits (Clock/APLL) 287N2 Value bits (Clock/APLL) 288NEC APLL1 and APLL2 Control Register 286NEC APLL1 Frequency Control 1 Register 287NEC APLL1 Frequency Control 2 Register 287NEC APLL2 Frequency Control 1 Register 287NEC APLL2 Frequency Control 2 Register 288New Command bit (AT IF) 149New Command Mask bit (AT IF) 151New Sector Timer Value Register (DSS) 210New Skip Value Register 213NEWSKVAL bits (DSS) 213newstval[12:8] (DSS) 212Next Entry Formatter Queue Pointer Register (TA) 107Next Logical Sector Address Register (FMTR Read Only) 96nextptr[5:0] bits (TA) 107nobufxfr bit (FMTR) 90nt_cntchng bit (BFR) 68number of DIB errors bit (ECC) 120Number of Symbol Errors in Data and XC bits (ECC) 124numdaterr 506numdiberr 506numtacnt bit (TA) 105

OOFFSENA bit (DSS) 212Others bitt (Test/Debug) 277Over Max LBA bit (AT IF) 150Over Max LBA Mask bit (AT IF) 151Overlap AM Search Delay Register (FMTR) 86

Overlap Read Gate Restart Adjust Register (FMTR) 84Overlap Read Gate Stop Register (FMTR) 84ovlaprgena bit (FMTR) 90ovlp_amsearchdly[5:0] (FMTR) 86

PP Value bits (Clock/APLL) 287, 288P1 Value bit (APLL1) 285P2 Value bit (APLL2) 286Package Specifications 344Parallel Fettweiss Algorithm 491Partial Hit bit (HNS) 188Pass Through Enable bit (MTR) 254Pause At Next Pointer Register (TA) 108PAUSE Register (TA) 108PDIAG Input bit (ATIF Read Only) 172PDIAG Output bit (ATIF) 172PDIAG/DASP/JUMPER Register 172Pending Refresh Count bits (BFR) 76PESPWM Polarity Invert bit (MTR) 255PESPWM Threshold Register (MTR) 258PESPWM Threshold Value [7:0] 258pfacthiwr bit (FMTR) 90pg_chng bit (BFR) 58Physical ECC Count bits (AT IF) 153Physical ECC Count Register (AT IF) 153Physical Long bit (AT IF) 148PLBA [7:0] 118PLL Write Register (FMTR) 81pllafterwdgena bit (FMTR) 90POSTAMBLEREG register 87POSTAMBLEREG Register (FMTR) 87postamblereg[4:0] bits (FMTR) 88Power Down Enable bit (ATIF) 174Power Down Enable bits (Test/Debug) 277Power Down Register 174Power Management Support 357Power on Reset Last bit (ATIF) 170Pre Spoke Low Register (DSS) 214preaflt bit (FMTR) 95preafltena bit (FMTR) 90preamble bit (DSS) 227preamble field 406Preamble Length After Wedge Register (FMTR) 88Preamble_low bits (DSS) 219preambledet bit (DSS) 231Prefetch Enable bit (BFR) 71Prefetch Next Address Register 70Prefetch Next Address Register - Page (BFR) 70preloadn bit (ECC) 115Prescale Counter register (MTR) 255Programmed I/O Timing 308, 516Programmed LBA Register (ECC) 118PRS Polynomial Register 215prs spoke ena bit (DSS) 218PRS Spoke History Register 216PRSSPKHIST bits (DSS) 216pseudo OTF correction 502Pseudo Slave Mode bit (ATIF) 171Pull-up and Pull-down Control bit (TMUX) 276

Qq_paused bit (FMTR) 95Qom_mtrint_sel bit (MTR) 258Qombo Interface 438


RR/W Channel Clock Control bit (CLK/APLL) 283RAM bit (UPI) 292raw mode/sync mode bit (TA) 104Raw Uncorrectable Error bit (ECC) 122, 124Rawdata Timing 312, 520rawtadelay bits (TA) 104Rd transfer mode bit (HNS) 201rd_svo_after_bcvwr bit (FMTR) 90rdwrdir 505Read DMA Enable bit (AT IF) 147Read Gate Delay Register (FMTR) 83Read IRQ14 Delay bits (AT IF) 158Read IRQ14 Delay Register (AT IF) 158Read Multiple Enable bit (AT IF) 147Read Sectors Enable bit (AT IF) 147Read Sense Phase[2:0] (MTR) 254Read Skip Adjust Register (FMTR) 82Read Stop bit 259Read Transfer Done bit (AT IF) 149Read Transfer Done Mask bit (AT IF) 151Read Wait Count 40 Register (UPI Offset 3) 290Read Xfer Trigger Count register (HNS) 191Read/-Wr bit (HNS) 196Read/Write bit (MTR) 261Read/Write Channel Clock Register 283Ready-to-Pause Time Register (AT IF) 158Refresh Acknowledge bit (BFR) 60Refresh Control Register (BFR) 76Refresh Count Register (BFR) 75Refresh Enable bit (BFR) 76Refresh Now bit (BFR) 76Refresh Status Register (BFR) 76Refresh Timing 301, 509refreshclk

BFR block 333Register

Memory Map 24Register LBA Value Level 1 (ECC) 119Register LBA Value Level 2 (ECC) 119Registers

16-Bit Error Mask 12916-bit Error Mask 12980D7h ECC_REQ

ECC Request Level High 73ACPCLK Atlas Core Processor Clock 279ADDCRS Add to Current Read Sectors 144ADDCWS Add to Current Write Sectors 143ADDHNSCWS Add HNS CWS 201ADDLUP Add to Loop Counter 107ADDLUPPTR Add To Loop Count At Pointer Value 108ADGCTRL ADRGEN Control 61AMSEARCHDLY AM Search Delay 83AMTIMOUTREG AM Timeout 82ARBCTRLI Arbiter Control 58ARBCTRLLO Arbiter Control Low 58ARBSTAT Arbiter Status 59ARBSTATLO Arbiter Status Low 59ARDLBA1-4 Auto Read LBA1 through 4 161ARDLBA2 Auto Read LBA2 161ARDLBA3 Auto Read LBA3 161ARDLBA4 Auto Read LBA4 161ASHDWCMD Auto Shadow Command 164ASHDWCYLHI Auto Shadow Cylinder High 164ASHDWCYLLO Auto Shadow Cylinder Low 164

ASHDWHEAD Auto Shadow Head Number 163ASHDWSECCNT Auto Shadow Sector Count 164ASHDWSECNUM Auto Shadow Sector Number 163ASICRST ASIC Reset Register 283AT_PDENAL AT I/O Cell Power Down Enable Low 277ATACLK ATA Clock 281ATCONFIG AT Interface Configuration 171ATORLO Auto Read Address 47ATORPG Auto Read Address Register - Page 48ATOWHI Auto Write Address Register - High Byte 48ATOWLO Auto Write Address 48ATOWPG Auto Write Address Register - Page 48ATOWRLDHI Auto Write Reload Register 49ATOWRLDPG Auto Write Reload Register Page 49ATOWROLHI Auto Write Rollover Address Register 48ATOWROLPG Auto Write Rollover Page 49Auto Read Address Register - High Byte 47AUTOCTL Auto Control 145AUTOENA Auto Enable 186AUTORDEN Auto Read Enable 146BCHCMD_STAT Command-Status 177BCHCTL BCH Control 178BCHCYLHI BCH Cylinder High 177BCHCYLLO BCH Cylinder Low 176BCHDEVCTL_ALTSTAT BCH Device Control-Alternate

Status 175BCHDRVHD BCH Drive Head 177BCHFEATR_ERR BCH Feature/Error 175BCHSECCNT BCH Sector Count 176BCVAM BCV AM Pattern 232BCVAMCTL BCV AM Control 233BCVCTRL1 233BCVCTRL2 BCV Control 2 234BCVSTAT BCV Status For Synchronous Servo 232BEMFTHR BEMF Window Threshold 255BFRCLK Buffer Clock 280BFRTEST1-3 Buffer Test 1 through 3 62BFRTEST2 Buffer Test 2 63BFRTEST3 Buffer Test 3 Register 63BLKCNT Block Count 156BUFSIZE0 Buffer Size Offset 192BURSTA Burst A 235BURSTB Burst B 236BURSTC Burst C 236, 238BURSTCHI High Byte of Burst C 236BURSTCTL Burst Control 235BURSTD Burst D 237BURSTF Burst F 238BURSTXA Burst A 243BURSTXB Burst B 244BURSTXC Burst C 244BURSTXD Burst D 245BURSTXE Burst E’ 246BURSTXF Burst F’ 246BYTECNT FORMAT (Selfscan) 102CALCISG Calculator Inter Sector Gap 81CLRFIFOERR Clear FIFO Error 155CMDCTLHI Command Control High 148CMDCTLLO Command Control Low 148CMDENHI Command Enable high 147CMDENLO Command Enable Low 147CMDREG Command 88CODERANGEEND Code Range End Address 69CODERANGESTART Code Range Start Address 68COMPHASE Commutation Phase 254CONFIG0 Configuration Register 0 189CONFIG1 Configuration 1 (HNS) 189


CONFIGREG Configuration 89CONFIGREGHI Configuration High 90COSVAL Cos Value 242COSVALA Cos Value For Burst A 239COSVALB Cos Value For Burst B 240COSVALD Cos Value For Burst D 241COSVALX Cos Value of burst’ 247COUNTER Watchdog Counter 263CPUBCTRL CPU Burst Control 70, 71CPUBNXTPG CPU Burst Next Address Register - Page 69CPUBREQLVL CPU Burst Request Level Control 71CPUSCTRL CPU Single Control 68CPUSSTAT CPU Single Status 68CPUSWAR1 CPU Single Write Address 1 66CPUSWAR1HI CPU Single Write Address 1 Register - High

Byte 66CPUSWAR1PG

CPU Single Write Address 1 Page 66CPUSWAR2 CPU Single Write Address 2 66CPUSWAR2HI CPU Single Write Address 2 Register - High 66CPUSWAR2PGHI CPU Single Write Address 2 Register - Page

High 67CPUSWAR2PGLO CPU Single Write Address 2 Register - Page

Low 66CRCVAL CRC Value 174CRSHI Current Read Sectors High 143CRSLO Current Read Sectors Low 143CRSSTAT CRS Status 144CSCCLK Cache Scan Clock 283CSTAT Core Status 59CURAGNTAR Current Agent Address 60CURAGNTARHI Current Agent Address Register - High Byte 60CURAGNTARPG Current Agent Address Register - Page 60CURAGTNUM Current Agent Number Being Serviced 60CURRENT_PTR 109CURRENTLSA Current LSA 97CURRLBALO Current LBA Low 195CWSHI Current Write Sectors High 142CWSLO Current Write Sectors Low 142CWSSTAT Current Write Sectors Status 144DATASIZE Sector Data Size 82DEBUGADR0HI Debug Address High Control 0 62DEBUGADR0LO Debug Address Low Control 0 61DEBUGADR1HI Debug Address High Control Register 1 62DEBUGADR1LO Debug Address Low Control 1 62DECSTATH Decoder Status High 122DECSTATL 121DEFADR Defect Table Address 73DEFADRPG Defect Table Address - Page 74DEFRLD Defect Table Reload Address 74DIBCTL DIB Control 159DIBERRS/DATAERRS DIB and DATA Errors 72DIBINTERNAL DIB Internal Status 134DIBLERRLBA DIB LBA Error Latched LBA 160DIBLERRLBAHI DIB LBA Error Latched LBA Register High 160DIBMERRLBA DIB Memory Error Latched LBA 160DIBMERRLBAHI DIB Memory Error Latched LBA High 160DMACKINTMSK DMACKN interrupt Status Mask 179DMACKNINT DMACKN Interrupt Status 179DMAREQCK DMA Request/Acknowledge Status 179DRAMCTRL DRAM Interface Control 56DRAMSTAT DRAM Interface Status 55DRAMSTATE1 DRAM State Machine 1 States 57DRAMSTATE2 DRAM State Machine 2 57DRAMTIMING DRAM State Machine Timing Control 56DRINTTHR Driver Interrupt Threshold 255

DSKADR1 Disk Word Starting Address Level 1 123DSKADR2 Disk Word Starting Address Level 2 123DSKADR3 Disk Word Starting Address Level 3 123EACC Accumulated Sector In Error Counter 120ECC Syndrome 127ECC_REQ ECC Request Level High 73ECC_REQ_LEV Request Level Low 73ECCAGNTSM ECC Agent State Machine State 71ECCCLK ECC Clock 280ECCCORADR ECC Correction Address 72ECCCORADRHI ECC Correction Address - High 72ECCCTRL ECC Control 72ECCSTAT ECC Status 72ECCXC0 ECC Cross Check Syndrome 0 133ECCXC1 ECC Cross Check Syndrome 1 133ECCXC2 ECC Cross Check Syndrome 2 133ECONFIG0 115ECTRL0 116, 117, 118EHIST Accumulated Error Number History 121EMUCLK Emulator Clock 279ENDOFSPOKE_DELAY 87ENDPTR End Formatter Queue Pointer 107ENDSTIM End Sector Time 209ENDSTIMHI 209ERREG Error Register 92ERRMSKREG Error Mask 91ESTAT0 ECC Status 0 119EUNCORR Accumulated Uncorrectable Sector Count 121FIFORDYCTL FIFO Ready Control 155FIFOSTAT FIFO Status 154FIFOSTATCTL FIFO Status Control 154FIFOWORDS BFR To Host FIFO Words 154FLAGS 231FLSA 1st LSA To Transfer 106FMTADR Formatter Address 52FMTADRPG Formatter Address 52FMTCTRL Formatter Control 55FMTQENTRY Fmtr. Cmd. Queue Current Entry 75FMTR_HOLDOFF_TIMER 55FMTRDIBPG Formatter DIB Page 54FMTRLD Formatter Reload Address 53FMTROL Formatter Rollover Address 53FMTRQBASE Formatter Command Queue Address 74FMTRQCTRL Formatter Command Queue Control 75FMTRQSTAT Formatter Command Queue Status 75FMTRREQLVL Formatter Request Level Control 53FMTRSPK Formatter Spoke 214FMTSTAT Formatter Status 54FWBUFAUTOWR FW Buffer Auto Write 194FWCMDLBAHI FW Command LBA High 193FWCMDLBALO FW Command LBA Low 193FWCRAMREQ FW REQUEST CRAM ENTRY FOR R/W 196FWFRCECMD Firmware Force State Machine 195FWSECCNT FW Sector Count 193HARHI Host Address Register High 46HARLO Host Address Low 46HARPG Host Memory Page Address 46HCTRL Host Control 50HEADCOMP Head Compare 217HEADROLL Head Rollover 165HIGHBPTRO High Buffer Pointer Offset 192HNSBCQ HNS Buffer Write Command Queue 190HNSBCQFLAGS HNS Buffer Write Command Que Flags 191HNSCWS HNS CWS 190HNSSMCTL HNS State Machine Control 203HNSSMSTOP HNS State Machine Stop 204HRLDHI Host Reload 47


HRLDPG Host Reload Page 47HROLHI Host Rollover Address High 46HST_REQ_CTRL Host Request Control 51HST_STATE_MACHINE Host State Machine 51HSTAT Host Status 50HSTCMD Host Command 169HSTCYLHI Host Cylinder Number High 162HSTCYLLO Host Cylinder Number Low 162HSTDEVCTL Host Device/Control 170HSTDRVHD Host Drive Head Number 162HSTERR Host Error 170HSTFEATR Host Features 170HSTSECCNTHI Host Sector Count High 163HSTSECCNTLO Host Sector Count Low 162HSTSECNUM Host Sector Number 161HSTSTAT Host Status 168HXFERCNTHI Host Transfer Count Register - High Byte 49HXFERCNTLO Host Transfer Count 49IDSLVBSY Drive ID/Slave Busy 172IFCTL Interface Control 169IFMTRS1 Internal Formatter States 1 (FMTR) 97INDEXCNT Index Counter 96INITIAL_LUPCNT Initial Lupcnt 109INTERRUPT Interrupt Status (HNS) 187INTERRUPTMASK Interrupt Mask (HNS) 187INTMASK Interrupt Mask 93INTMSK1 Interrupt Mask 1 151INTMSK2 Interrupt Mask 2 151INTMSK3 Interrupt Mask 3 152INTREG Interrupt 94INTSECCNTLO Internal Sector Count Low 168INTST1 Interrupt Status 1 149INTST2 Interrupt Status 2 150INTST3 Interrupt Status 3 150IOCONFIG I/O Configuration 264IOCTL IO Control 173IRQDLYCNTR IRQ14 Delay Counter 159LASTHITENT Last Hit Entry (HNS) 186LASTJMARK Last Marked Entry 188LBA1-4 Logical Block Address 1-4 165LBA3 Logical Block Address 3 166LBA4 Logical Block Address 4 166LCACHEDSECT Load Cached Sectors 191LOADSECT Load Sector Timer Delay 212LOGECCCNT Logical ECC Count 153Logical Block Address 2 Register (AT IF) 166LOWBPTRO Low Buffer Pointer Offset 192LPLL1PM Lucent APLL1 Frequency PM Control 285LPLL2PM Lucent APLL2 Frequency PM Control 286LPLLTST Lucent APLL1 and APLL2 Test 284LSA FORMAT (Selfscan) 102LSBNUM LBS Number 216LUFREQS Lucent APLL1 and APLL2 Frequency Control 285LUPCOUNT Loop Counter 106MAXCHSLBA Maximum LBA in CHS Mode 167MAXCHSLBA2 Maximum LBA in CHS Mode 2 167MAXCHSLBA3 Maximum LBA in CHS Mode 3 167MAXCHSLBA4 Maximum LBA in CHS Mode 4 167MAXENTRYADDR Maximum Number Of Entry Addresses 186MAXLBA1-4 Maximum LBA 1-4 166MAXLBA2 Maximum LBA2 166MAXLBA4 Maximum LBA 4 167MAXSPKNU Maximum Spoke Number 215MAXSPLIT Maximum Split 84MINSPLIT Minimum Split 85MISS_LBALO Miss LBA Low 187

MODE/STAT Mode/Status Register 200MSERADR Motor Main Serial Address 261MSERDAT Motor Main Serial Data 260MTRCLK Motor Clock 282MTRCORE1 Motor Core Register 1 252MTRCORE2 Motor Core Control Register 2 253Muxed ECC Syndrome and Error Parameters 127MXIDX/IPFLTMax Index and Ignore Preaflt 81NEC1FREQ1 NEC APLL1 Frequency Control 1 287NEWSKVAL New Skip Value 213NEWSTVA New Sector Timer Value 210NEXTLSA Next Logical Sector Address 96NEXTPTR Next Entry Formatter Queue Pointer 107NPLL1N NEC APLL1 Frequency Control 2 287NPLL2M NEC APLL2 Frequency Control 1 287NPLL2N NEC APLL2 Frequency Control 2 288NPLLCNTL NEC APLL1 and APLL2 Control 286NXTDATADR CPU Single Next Read Address 67NXTDATADRHI CPU Single Next Read Address High 67NXTDATADRL CPU Single Next Read Address Register Low 67NXTDATADRPGHI CPU Single Next Read Address - Page

High 67OVLP_AMSEARCHDLY Overlap AM Search Delay 86OVLPRGRESTART_ADJ Overlap Read Gate Restart Adjust 84OVLPRGSTOP Overlap Read Gate Stop 84PAUSE 108PAUSE _ AT _ PTR Pause At Next Pointer 108PDIAGDASP PDIAG/DASP/JUMPER 172PESPWM Threshold 258PHYECCCNT Physical ECC Count 153PLBA Programmed LBA (ECC) 118PLLAFTRWDG Preamble Length After Wedge 88PLLPASWD Lucent and NEC APLL Password 284POSTAMBLEREG 87PREFETCHNXT Prefetch Next Address 70PREFETCHNXTPG Prefetch Next Address Register - Page 70PRESCCNTR Prescale Counter 255PRSPOLY PRS Polynomial 215PRSSPKHIST PRS Spoke History 216PWRDN Power Down 174RDIRQDLY Read IRQ14 Delay 158RDISGREG Inter Sector Gap for Read 83RDSKIPADJ Read Skip Adjust 82RERDCTL Re-Read Control 173RESUME (TA) 108RFCNT Refresh Count 75RFCTRL Refresh Control 76RFSTAT Refresh Status 76RGDLAYREG Read Gate Delay 83RLBA1 Register LBA Value Level 1 119RLBA2 Register LBA Value Level 2 119RWCCLK Read/Write Channel Clock 283RWCTL RW Control 85SAM2SAM SAM to SAM Timer Register 212SCAN_REP_CNTR_REG Selfscan Repeat Pattern Control 101SCANHOLD Scan Error Count Holding 101SCANLIMIT Scan Error Limit 100SDMACTL SDMA Control 157SDMAMODE SDMA Timing Mode 157SECPERCYL1-3 Sectors Per Cylinder 1-3 165SECPERCYLHI Sectors Per Cylinder High 165SECPERTRK Sector Per Track 165SECROLL Sector Rollover 164SECSIZE Sector Size 80SECTORSAVAIL Sectors Available Loaded to Host 200SECTRANS Sectors Transferred 88SECTSIZEHI Sector Size High 152


SECTSIZELO Sector Size Low 152SELFSCAN0_1, E_F Selfscan Word 0_1 through E_F 98SELFSCAN4_5 Selfscan Word 2 98SELFSCAN6_ Selfscan Word 3 99SELFSCAN8_9 Selfscan Word 4 99SELFSCANA_B Selfscan Word 5 99SELFSCANC_D Selfscan Word 6 100SELFSCANE_F Selfscan Word 7 100SELFSCANREGHI Selfscan High 98SGLOBALERR1 Global Errors 1 for Sync. Servo 226SGLOBALERR2 Global Errors 2 for Sync. Servo 226SGLOBALERR3 Global Errors 3 for Sync. Servo (Read Only) 227SGLOBALMASK1 Global Error Mask Bits for Sync. Servo 220SGLOBALMASK2 Global Error Mask bits for Sync. Servo 221SGLOBALMASK3 Global Error Mask Bits For Sync. Servo 222SHDWBPTR Buffer Pointer Shadow 197SHDWCWSHI Shadow of CWS High 145SHDWCWSLO Shadow of CWS Low 145SHDWFLAGCLR Flags Shadow Register Clear 199SHDWFLAGS Flags Shadow 198SHDWOFFS LBA Offset Shadow 198SHDWSIZE Segment Size Shadow 197SHDWSTLBA Start LBA Shadow 196SHDWVALID Valid LBA Shadow 196SIGNVALX Sin Value of X 248SIGNVALXHI High Byte of Sin Value of X 248SINVAL Sin Value 243SINVALA Sine Value For Burst A 239SINVALB Sine Value For Burst B 240SINVALC Sine Value For Burst C 241SINVALX Sin Value of Burst’ 247SINVALXHI High Byte of Sine Value of Burst 248SIPWM Div 258SIPWMTHR SIPWM Threshold 256SKEWREG Spoke Skew 85SKIPCARRY Skip Carry 213SKIPENTRY (HNS) 188SKPLLREG Skip PLL 81SLEEPSET Sleep Set 201SMCTL State Machine Control 156SMENTRYADDR State Machine Entry Address Register 186SMSTOP State Machine Stop 156SMV Set Multiple Value 156SONICRESET Sonic PORN, Hard and Soft Reset Interrupt

Register 174SONICTEST1 Sonic Test 1 180SONICTEST2 Sonic Test 2 181SPARELOGIC Spare Logic 51SPAREOUT Spare Logic 135SPEEDHIB Speed High Boundary 220SPEEDLOB Speed Low Boundary 220SPKCTL1 Spoke Control 1 217SPKCTL2 Spoke Control 2 218SPKCTL3 Spoke Control 3 218SPKCTL4 Spoke Control 4 219SPKMSK Spoke Mask 215SPKNUM Spoke Number 215SPKSTATUS Spoke Status 231SPOKECNT Spoke Counter 214SR2DATHI Serial 2 Data High 296SRCHLBAHI Search LBA High 194SRCHLBALO Search LBA Low 194SRDATLO Serial Data Low 296SRXERCTL Serial Transfer Control 296SSVODLYCTL1 Servo Delay Control 1 for Sync. Servo 225SSVODLYCTL2 Servo Delay Control 2 for Sync. Servo 225

SSVODLYCTL3 Servo Delay Control 3 for Sync. Servo 226SSVOFLTMASK1 Servo Fault Mask Bits For Sync. Servo 223SSVOFLTMASK2 Servo Fault Mask bits for Sync. Servo 223SSVOFLTMASK3 Servo Fault Mask bits for Sync. Servo 224STACK00 124STACK02 ECC Stack 02 125STACK0H Stack 01 124STACK10 ECC Stack 10 Register 125STACK11 ECC Stack 11 Register 125STACK12 ECC Stack 12 126STACK20 ECC Stack 20 126STACK21 ECC Stack 21 126STACK22 ECC Stack 22 126STADVTHR State Advance Threshold 255STASTTIM Start Sector Time 209STATREG Status 95STSNAP Sector Timer Snapshot 213SVBUFAUTOWR Saved Buffer Auto Write Pointer 199SVITIM Servo Interrupt Time 208SVOCLK Servo Clock 281SVOINTOFF Servo Interrupt Off Time 210SymbolCNTR Symbol Counter 97SYMPWDG Calculator Symbols Per Wedge 80TA Thermal Asperity Address 63TA_CURR_PTR_LO 65TA_CURR_PTR_PG 65TACRLLO Thermal Asperity Control Low 64TACTRL Thermal Asperity Control 64TALO Thermal Asperity Base Address Low 63TAPG Thermal Asperity Base Address Register Page 63TARECCONFIG TA Record Configuration 104TARECMAX TA Record Maximum 105TAREQLEV0 Thermal Asperity Request Level 0 63TAREQLEV1 Thermal Asperity Request Level 1 64TASTAT Thermal Asperity Status 64TASTRLENGTH TA STR Length 106TASTRLSA TA Strobe LSA 105TASTRSYMBOL TA Strobe Symbol 105TDATA Test Data To FIFO (ECC) 134Test Out Mux 259TESTADDR Test Address 231TESTMUXSEL1 Test Mux Select 1 202TESTMUXSEL2 Test Mux Select 2 (HNS) 202TESTREG Formatter Test Register 96TESTSKP TEST Skip (DSS) 234TIMEUPLO Times-Up Reload Value 208TMUX_MISC Miscellaneous Control 276TMUX_STATCTL Status & Control 276TMUX_TSTIO1CTL Test IO 1 Control 270TMUX_TSTIO1SEL Test IO 1 Select 266TMUX_TSTIO2CTL Test IO 1 Control 275TMUX_TSTIO2SEL Test IO 2 Select 271TNACTL2 TNA Control Register 2 212TOTALERRSECTotal Error Sector 135TRAK1STLSA 1st LSA Of The Track 87TRGCOUNT Read Xfer Trigger Count 191TRKACMPHI 229TRKACMPLO 229TRKBCMP Track Number B Compare 229TRKBCMPHI Track Number B Compare High 229TRKNUM Track Number 228TRKNUM32 Track Number 32 228TRPTIME Ready-to-Pause Time 158TSTCNTL Test IO Mux Control (MTR) 259TSTCTL TEST Control (DSS) 234UNCORR_PTR 109UPI_ SVOWAITR Servo Read Wait Count 292


UPI_ SVOWAITW Servo Write Wait Count 292UPI_ WAITAVR AV Read Wait Count 292UPI_ WAITAVW AV Write Wait Count 291UPI_CTL Control 289UPI_EXTBSYSTAT External Busy Status 292UPI_INTRPT Interrupt 293UPI_VERHI Version High Byte 293UPI_WAIT100 Wait Count 100 291UPI_WAIT40R Read Wait Count 40 290UPI_WAIT40W Write Wait Count 40 290UPI_WAIT66 Wait Count 66 291UPIF UP IF Status 62VCCPMVALH Voice Coil PWM Value High 258VCMAU VCM Auto Update Enable 257VCMSERPL VCM Serial Port 262VCPVMTIMH Voice Coil PWM Timing Value High 257VCPWMTIM Voice Coil PWM Timing 257VCPWMVALL Voice Coil PWM Value 257VIPWMH Threshold 256VIPWML Threshold Register (MTR) 256WCQDECINC Decrement/Increment Write Command Queue 159WCSADDR WCS Address 230WCSCONF WCS Configuration 230WCSDAT WCS Data 230WDSECSIZE Word Sector Size 86WDXFRCNTRHI Word Transfer Counter High 154WDXFRCNTRLO Word Transfer Counter Low 153WGEXTEND WG Extend At End Of Sector 87WRIRQDLY Write IRQ14 Delay 159WRISGREG Inter Sector Gap for Write 83WRPLLREG PLL Write 81WTCHPSWD Watchdog Password 263XFERCNT Formatter Transfer Count 54ZEROXTND Zero Extend 86

Registers CPUBNXT CPU Burst Next Address 69Registers PRESPK Pre Spoke 214Release Entry bit (HNS) 188Release Interrupt bit (HNS) 198Release Version bits (UPI) 293reqout bit (BFR) 59Re-Read Control Register 173Reset APLL Clocks bit (CLK/APLL) 283Reset interrupt bit (AT IF) 175Reset Interrupt Mask bit (AT IF) 174Restart WCS bit (DSS) 231RESUME (Write Only FMTR) 108Run Count State bit (MTR) 254Run or Commutation Enable bit (MTR) 254RW Control Register (FMTR) 85rwclk 367, 401

BFR block 332ECC block 334FMTR block 330SERVO block 326

RWDATA pins 489RWgate_ena bit (DSS) 218

SSAM 405SAM detection quality 490SAM Low Qual bit (DSS) 227SAM Timeout bit (DSS) 227SAM to SAM bits (DSS) 212SAM to SAM Timer Register 212Sample Test bit (MTR) 259Saved Buffer Auto Write Pointer Register 199

SC1_MSCLK[1:0] 264SC2_MSDAT[1:0] (MTR) 264SC3_MSENA[1:0] (MTR) 264Scan Error Count Holding Register (FMTR) 101Scan Error Limit Register (FMTR) 100scanactive valid bit (HNS) 187Scanactv mode bit (HNS) 201SCLK Timing 314, 522SDATA Read Timing 314, 522SDATA Write Timing 314, 522sdma 3.5 bit (AT IF) 157SDMA Control Register (AT IF) 157SDMA Timing Mode bits (AT IF) 157SDMA Timing Mode Register (AT IF) 157SDMA Transfer bit (AT IF) 157SDRAM Bus 538SDRAM Clock Delay Control 288sdram_type bit (BFR) 61SDRAM1 bits (UPI) 289Search LBA High Register (HNS) 194Search LBA Low Register (HNS) 194Sector Count Greater Than CRS bit (AT IF) 145Sector Count Greater Than CWS bit (AT IF) 144Sector Data Size Register 82Sector Last Enable bit (AT IF) 149Sector Per Track Register (AT IF) 165Sector Rollover bits (AT IF) 164Sector Rollover Register (AT IF) 164Sector Size High Register (AT IF) 152Sector Size Low Register (AT IF) 152Sector Size Register (FMTR) 80Sector start_addr 506Sector Timer Snapshot Register 213Sector_Request bits (BFR) 54Sectors Available Loaded to Host Register 200Sectors Per Cylinder High Register (AT IF) 165Sectors Per Cylinder Registers (AT IF) 165Sectors Transferred Register (FMTR) 88SECTSIZE[7:0] bits (AT IF) 152SECTSIZE[8] bit (AT IF) 153Seek Complete bit (ATIF) 168Segment Size Shadow Register (HNS) 197sel_agent bits (BFR) 58selfscan bit (FMTR) 90Selfscan Bits

BYTE1 102BYTE2 102BYTE3 102BYTE4 102bytecntr[12:10] 102bytecntr[9:2] 102LSA[11:8] 102LSA[7:0] 102

Selfscan Repeat Pattern Control Register (FMTR) 101Selfscan Word 0 Register (FMTR) 98Selfscan Word 1 Register (FMTR) 98Selfscan Word 2 Register (FMTR) 98Selfscan Word 3 Register (FMTR) 99Selfscan Word 4 Register (FMTR) 99Selfscan Word 5 Register (FMTR) 99Selfscan Word 6 Register 9FMTR) 100Selfscan Word 7 Register (FMTR) 100selfscan_mode bit (BFR) 61Self-Servo Write Enable bit (DSS) 218SENU, SENV, SENW 436SENU_RW [1:0] (MTR) 265senule bit (MTR) 255


SENV_NST[1:0] (MTR) 265SER Bits

SER2 Busy (Read Only) 296Serial 2 Address [6:0] 296Serial Data [7:0] 296Write or Read Indicator 296

SERBSY bit (SER) 296serclkg

SERIAL block 337Serial Address bits [6:0] (SER) 296Serial Address Size bit (MTR) 260Serial Data High Register (SER) 296Serial Data Low Register (SER) 296Serial Interface Read/Write To A Register 313, 521Serial see also SERSerial Transfer Control Register (SER) 296seriousflt bit (FMTR) 92servo address mark 406Servo Burst Data 406Servo Bursts 405Servo Clock 1 Select bits (CLK/APLL) 281Servo Clock 2 Select bits (CLK/APLL) 281Servo Clock Register (CLK/APLL) 281Servo Clocks Control bit (CLK/APLL) 281Servo Delay Control 1 for Sync. Servo register 225Servo Delay Control 2 for Sync. Servo register 225Servo Delay Control 3 for Sync. Servo register 226Servo Fault Mask bits for Sync. Servo bit 224Servo Fault Mask Bits For Sync. Servo register 223Servo Fault Mask bits for Sync. Servo register 223Servo Interrupt Off Time Registers 210Servo Interrupt Status bit (UPI) 293Servo Interrupt time 410Servo Interrupt Time Register 208SERVO mode 489Servo Read Wait Count Register (UPI Offset 8) 292Servo Write Wait Count Register (UPI Offset 8) 292servoclk1

MOTOR block 327serwrrd ind bit (SER) 296Set Busy bit (AT IF) 169Set DRQ bit (ATIF) 169Set IRQ14 bit (ATIF) 169Set Multiple Value Register (AT IF) 156settledone bit (FMTR) 89sft_rst bit (BFR) 62Shadow of CWS High Register (AT IF) 145Shadow of CWS Low Register (AT IF) 145SHDWCWS[11:8] bits (AT IF) 145SHDWCWS[7:0] (AT IF) 145shock bit (DSS) 226Shock Fault Stop Formatter bit (DSS) 231shock pol bit (DSS) 219sin signxA bit (DSS) 248sin signxB bit (DSS) 248sin signxC bit (DSS) 248sin signxD bit (DSS) 248sin signxE bit (DSS) 248sin signxF bit (DSS) 248Sin Value of Burst’ Register (DSS Read Only) 247Sin Value register (DSS) 243Sine Value For Burst A register (DSS) 239Sine Value For Burst C register 241Single Error bit (DSS) 232SINVAL bits (DSS) 243SINVALXHI bit (DSS) 248

SIPWM Div Register (MTR) 258SIPWM Threshold Register (MTR) 256sipwm_div bits (MTR) 258Skip Carry bits (DSS) 213Skip Carry Register (DSS) 213Skip Enable bit (DSS) 219Skip Entry Register (HNS) 188Skip First SAM bit (DSS) 217Skip PLL Register (FMTR) 81skip valid bit (HNS) 188Slavebsyn bit (ATIF) 172Sleep Mode bit (AT IF) 174Sleep Set Register (HNS) 201sleepclr bits (HNS) 201sleepena bit (HNS) 201SMCTL[4:0] bits (AT IF) 156SMSTOP[4:0] bits (AT IF) 157SMV[7:0] bits (AT IF) 156soft error control bits (DSS) 219Soft POR bit (CLK/APLL) 284soft reset 503Soft Reset bit (ECC) 118Sonic PORN, Hard and Soft Reset Interrupt Register 174Sonic Test 1 Register 180Sonic Test 2 Register 181Spare Logic bits (BFR) 52Spare Logic Input (clk) bit (ATIF) 180Spare Logic Input (gclk) bit (ATIF) 180Spare Logic Out bits (MTR) 258Spare Logic Register (BFR) 51Spare Logic Register (ECC) 135speed bit (DSS) 226Speed high boundary bits (DSS) 220Speed High Boundary register 220Speed low boundary bits (DSS) 220Speed Low Boundary register (DSS) 220Spindle Motor PWM 453Spoke Control 1 register (DSS) 217Spoke Control 2 register (DSS) 218Spoke Control 3 register (DSS) 218Spoke Control 4 Register 219Spoke Counter Register (DSS) 214spoke counting 413Spoke gate bit (DSS) 232Spoke Mask register 215Spoke Mode Details 405Spoke Num Dat bit (DSS) 227spoke number miscompare bit (DSS) 227Spoke Number register 215Spoke Skew Register (FMTR) 85SPOKE SOFT RESET bit (DSS) 218Spoke Status register (DSS) 231SPOKEIF 412srvdat[5:0] 404srvstrobe 404STACK00 Register (ECC) 124start ack bit (BFR) 55Start of Sector Time bits 12-8 (DSS) 209start req bit (BFR) 55Start Sector time 410Start Sector Time Register 209startfq bit (FMTR) 89State Advance Threshold Bits [5:0] (MTR) 255State Advance Threshold Register (MTR) 255State Machine Control Register (AT IF) 156State Machine Entry Address Register (HNS) 186State Machine Stop Register (AT IF) 156


Status & Control Register (Test/Debug Read Only Offset 7) 276Status Read by Host bit (AT IF) 149Status Read by Host Mask bit (AT IF) 151Status Register (FMTR) 95Stop Enable bit (AT IF) 156Stop on First Uncorrectable Error bit (ECC) 115stopamtimout bit (FMTR) 91stopatlimit bit (FMTR) 91stopchecksum bit (FMTR) 91stopdiberrflt bit (FMTR) 91stopeccerrflt bit (FMTR) 91stopfq bit

FMTR) 89stopindexto bit (FMTR) 91stoppreaflt bit (FMTR) 91stopseriousflt bit (FMTR) 91stopsvofltrd bit (FMTR) 91stopsvotimout bit (FMTR) 91stopwgwedge bit (FMTR) 91Stratus System Block Diagram 22, 23svoclk1

SERVO block 325svoflterr bits (FMTR) 92svowaitr[5:0] (UPI) 292svowaitw[5:0] (UPI) 292Symbol Counter Register (FMTR, Read Only) 97Sync Global Error or trknum 15 bit (DSS) 228Sync Global Error or zero bit (DSS) 228Sync mark detection 489Sync. SAM found bit (DSS) 232Sync. Servo fault bit (DSS) 232Sync. Servo fault stop fmt bit (DSS) 232synclose 506synclose bit (ECC) 120syncls 503Syndrome Generator register 504syndrome open bit (ECC) 117

TTA bit (DSS) 226TA Bits

addlup[10:0] 107addlup[7:0] 107addlup_ptr 107addlupfail 106addlupfail_ptr 106addlupptr[5:0] 108current_pointer [5:0] 109endptr[5:0] 107flsa[15:0] 106flsa[7:0] 106initial_lupcnt[13:8] 109initial_lupcnt[7:0] 109lupcntinvalid 106lupcount[10:0] 106lupcount[7:0] 106nextptr[5:0] 107pause_at_ptr[5:0] 108raw mode/sync mode 104rawtadelay[3:0] 104tarecena 104tastr befoream 104tastr beforesplit 104tastrena 104tastrlength[13:0] 106tastrlength[7:0] 106

tastrlsa[15:0] 105tastrlsa[7:0] 105tastrsymbol[13:0] 105tastrsymbol[7:0] 105uncorr_ stoptarec 104uncorr_ptr0 109uncorr_ptr1 109

TA Current Pointer Low Register (BFR) 65TA Current Pointer PG Register (BFR) 65TA in BCV bit (DSS) 234TA in Burst bit (DSS) 232TA Record Configuration Register 104TA Record Maximum Register (TA) 105TA Sector Size[2:0] (BFR) 64TA Strobe Length Register (TA) 106TA Strobe LSA Register (TA) 105TA Strobe Symbol Register (TA) 105TA_CURR_PTR[15:0] bits (BFR) 65TA2bfr_data [16:0] 368TA2bfr_xfr 368taafteram bit (FMTR) 94tabefoream bit (FMTR) 94taclk 368tacthird bit (FMTR) 90taexceedlimit bit (FMTR) 94tarecena bit (TA) 104tarecmax bit (TA) 105tastrbefoream bit (TA) 104tastrbeforesplit bit (TA) 104tastrena bit (TA) 104Test Address register 231Test Brstcal bit (DSS) 235Test Clock bit (DSS) 234TEST Control Register (DSS) 234Test Data To FIFO register (ECC) 134Test deccrs bit (AT IF) 180Test deccws bit (AT IF) 180Test FIFO Words bit (AT IF) 181Test Interrupt bit (AT IF Write Only) 181Test IO 1 Control Register (Offset 1) 270Test IO 1 Select Register (Offset 0) 266Test IO 2 Control Register (Offset 3) 275Test IO 2 Select Register (Offset 2) 271Test IO Mux Control Register (MTR) 259Test Load bit (DSS) 234Test Mode bit (DSS) 234Test Mode for Watchdog bit (MTR) 263Test Mux Control[2:0] (MTR) 252Test Mux Select 1 register (HNS) 202Test Mux Select 2 register (HNS) 202Test Out Mux [15:8] (Motor) 259Test Out Mux [7:0] (Motor) 259Test Register (FMTR) 96Test Skip bits (DSS) 234TEST Skip Register (DSS) 234Test/Debug Bits

1394 Operating Mode (R/O) 276CLKOUT Driver Enable 276DASP_Port13 277enable AVclock output 276enable AVclock pullup 276HD0_Port10 277HD1_Port11 277HD10_Port37 277HD11_Port22 277HD12_Port24 277HD2_Port12 277


HD5_Port15 277HD6_PORT1 277HD6_PORT16 277HD7_Port39 277HD8_Port17 277HD9_Port36 277Mode Bits[4:0] 276Others 277PDIAG_Port14 277Pull-up & Pull-down Control 276TESTIO1 BLKSEL[3:0] 270, 275TESTIO1 enable 270TESTIO1SEL[7:0] 266TESTIO2 enable 275TESTIO2SEL[7:0] 271

TESTADDR bits (DSS) 231testdataxfr bit (AT IF) 181testena bit (FMTR) 96testforceam bit (FMTR) 96TESTIO1 BLKSEL[3:0] (TEST) 271TESTIO1 Enable bit (TEST) 270TESTIO1SEL bits (TEST) 266TESTIO2 BLKSEL[3:0] (TEST) 276TESTIO2 Enable bit (TEST) 275TESTIO2SEL bits(TEST) 271testload bit (FMTR) 96testmuxsel1 [4:0] (HNS) 202testmuxsel2[4:0] (HNS) 203testrg bit (FMTR) 96testwg bit (FMTR) 96Thermal Asperity Acknowledge bit (BFR) 60Thermal Asperity Address bits (BFR) 63Thermal Asperity Base Address Register Low (BFR) 63Thermal Asperity Base Address Register Page (BFR) 63Thermal Asperity Base Address Registers (BFR) 63Thermal Asperity Control Register 64Thermal Asperity Enable bit (BFR) 65Thermal Asperity FIFO Empty bit (BFR) 64Thermal Asperity FIFO Error Clear bit (BFR) 65Thermal Asperity FIFO Full bit (BFR) 64Thermal Asperity FIFO Reset bit (BFR) 65Thermal Asperity Module (16-Bit 80C0h - 80DFh) (8-Bit FBC0h -

FBDFh) 104Thermal Asperity Overrun bit (BFR) 64Thermal Asperity Request bit (BFR) 64Thermal Asperity Request Count bits (BFR) 64Thermal Asperity Request Level 0 Register (BFR) 63Thermal Asperity Request Level 1 Register (BFR) 64Thermal Asperity Status Register (BFR) 64Thermal Asperity Underrun bit (BFR) 64Times Up Reload Value Register 208Top Level State Control bit (MTR) 253Total Error Sector Register (ECC) 135Total Number Of Symbol Errors bits (ECC) 124Track 0 bit (AT IF) 171TRACK COMP EN bits (DSS) 219track data error bit (DSS) 227Track Miscompare bit (DSS) 227Track Number 32 Register (DSS Read Only) 228Track Number A Compare High register 229Track Number A Compare Low register 229Track Number A Compare register (DSS) 229Track Number B Compare High register 229Track Number B Compare register 229Track Number Registers (DSS) 228track soft error bit (DSS) 227

TRACKID16 bit (DSS) 218Transfer Active bit (AT IF Read Only) 142Transfer Active bit (AT IF) 143Transfer Active bit (ATIF Read Only) 163Transfer active bit (HNS) 201Trapper block 502tras bits (BFR) 56trc[3:0] bits (BFR) 56trcd bit (BFR) 56Tristate DASP bit (ATIF) 173TRKACMPLO[7:0] (DSS) 229TRKCMPBHIGH bits (DSS) 230TRKCMPEN bit (Servo) 219TRKCMPHI bits (DSS) 229TRKNUMHI bits (DSS) 228trp bit (BFR) 56TRPTIME[4:0] bits (ATIF) 158Two port RAM 412

UUDL 357UDL Version bits (UPI) 293Ultra Force DMARQ bit (AT IF) 180Ultra Force IORDY bit (AT IF) 180Unavailable bit (HNS) 198uncorr_ptr0 bit (TA) 109uncorr_ptr1 bit (TA) 109uncorr_stoptarec bit (TA) 104uncorrdone 506uncorrdoneint bit (FMTR) 94Uncorrectable Error bit (ECC) 122, 124Uncorrected Pointer Register (TA) 109uncorrfault bit (ECC) 120uP Core Clock Status (CLK/APLL Read Only) 279UP IF Status Register (BFR) 62uP Pause Transfer bit (AT IF) 157uP Stop Transfer at Zero CRS or CWS bit (AT IF) 158uP Stop Transfer Now bit (AT IF) 157upaddr 361upclkout 362UPCLKOUT pin signal 340UPI/Proc Bits

AV RESET 293AVINT 293burst_wait_clk_inv 289CLK Invert 289CLK Invert Completed 289cnt100r[3:0] 291cnt100w[3:0] 291cnt40r[5:0] 290cnt40w[5:0] 290cnt66r[3:0] 291cnt66w[3:0] 291DEBUG INT 293Embed Read Channel 292FMTRINT 293Foundry 293HINT 293HRESET 293RAM 292Read Channel Version 293Release Version 292SDRAM1[1:0] 289Soft Reset 289SVOINT 293svowaitr[5:0] 292svowaitw[5:0] 292


SvoWS[5:0] 290UDL Version 292waitavr[5:0] 292waitavw[5:0] 291

upi_upclkoutBFR block 333UPI block 338

upi2bfr_dram_data[15:0] 362upi2bfr_lbytr_wr 362upi2bfr_ubyte_wr 362upi2bir_addr[20:0] 362upi2bir_dramsel 362upi2bir_rdwrn 362upwrdat 361

Vvalid error address 502valid error value 502Valid LBA Shadow Register (HNS) 196VCM Auto Update Enable register 257VCM Serial Channel bit (MTR) 260VCM Serial Port Register 262VCM Serial Transfer Busy bit (MTR) 259Version Register High Byte UPI Offset B) 293Video data bit (HNS) 198Video Read Enable bit (HNS) 189VIPWM Invert bit (MTR) 253VIPWMH Threshold Value [5:1] 256VIPWMH_SVDAT & VIPWML & SIPWM Output Enable bit

(MTR) 265VIPWML Duty Cycle Control [1:0] (MTR) 256VIPWML Threshold Register (MTR) 256VIPWML Threshold Value [4:0] (MTR) 256Voice Coil (VC) PWM Logic 434, 454Voice Coil PWM Timing 318, 526Voice Coil PWM Timing register 257Voice Coil PWM Value register 257vVIPWML Threshold Value [4:0] 256

WW/R bit (ECC) 121, 124Wait Count 100 Register (UPI Offset 5) 291Wait Count 66 Register (UPI Offset 4) 291waitavr[5:0] (UPI) 292waitavw[5:0] (UPI) 291Watch Dog Polarity bit (MTR) 263Watch Dog Timer Enable bit (MTR) 263Watchdog Counter register 263Watchdog Password (MTR Write Only) 263Watchdog Timer Load Value register 262Watchdog Timer Operation 463WCS 411WCS address bits (DSS) 230WCS Address register (DSS) 230WCS Configuration register (DSS) 230WCS Data register 230WCS enable bit (DSS) 231WDCNTR[15:0] (MTR) 262wdgtmr[13:8] (MTR) 264wdgtmrctl[15:14] (MTR) 264WDXFRCNTR[7:0] bits (AT IF) 153WDXFRCNTR[8] bit (AT IF) 154WG Extend At End Of Sector Register (FMTR) 87wgpreaerr bit (FMTR) 92wgunderwg bit (FMTR) 92Word Sector Size Register (FMTR) 86

Word Transfer Counter High Register (AT IF) 154Word Transfer Counter Low Register (AT IF) 153Write Buffer Enable bit (AT IF) 147Write DMA Enable bit (AT IF) 147Write Fault bit (ATIF) 168Write IRQ14 Delay bits (AT IF) 159Write IRQ14 Delay Register (AT IF) 159Write Long Enable bit (AT IF) 147Write Multiple Enable bit (AT IF) 147Write Pending bit (HNS) 198Write Sectors Enable bit (AT IF) 147Write Verify Enable bit (AT IF) 147Write Wait Count 40 Register (UPI Offset 2) 290WRRDN bit (AT IF) 148WrScanDn bit (HNS) 188wrtstb 361wrxpndena bit (HNS) 190

Xxcerror bit (ECC) 120xctime 506xfr_lnth bits (BFR) 58xfr_lnth[2] bit (BFR) 58xfr_typ bits (BFR) 58xtal1f

TMUX block 337UPI block 337

xtermode bit (FMTR) 90

ZZero Extend Register (FMTR) 86Zero Phase Start bit (DSS) 232

Digital ASIC - Technology Writersamples.technology-writer.com/ASIC.pdf · Digital ASIC DOCUMENT SOURCE REFERENCE HARDWARE Pentium PC SOFTWARE FrameMaker 5.5 The electronic database

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