Digital Algorithms for Linearity Improvement of Current ... would like to thank my review committee members, Professors, Dr. Kuniyuki MOTOJIMA, Dr. Sadao ADACHI, Dr. Yasunori KOBORI

Digital Algorithms for Linearity Improvement of

Current-Steering Digital-to-Analog Converter

DISSERTATION

Submitted by

SHAIFUL NIZAM BIN MOHYAR

In partial fulfillment of the requirements for the award of the Degree of

DOCTOR OF PHILOSOPHY

IN

ELECTRONICS & INFORMATICS ENGINEERING

Under the guidance of

PROFESSOR HARUO KOBAYASHI, Ph. D. Eng.

DIVISION OF ELECTRONICS & INFORMATICS

GRADUATE SCHOOL OF SCIENCE & TECHNOLOGY

GUNMA UNIVERSITY

JAPAN

March 2015

Acknowledgement

i

Acknowledgement

Special thanks to my supervisor Professor Dr. Haruo KOBAYASHI

for his great guidance and support. Without his support this study could

not have been done properly.

I am gratefully acknowledges the research support from members

of Semiconductor Technology Academic Research Center (STARC)

group for their priceless advice and support during my study. My great

appreciation also goes to Dr. Takahiro MIKI from Renesas Elelctronics,

members of our ADC/DAC group (especially Mr. Yutaro KOBAYASHI)

and my colleague, Mr. Shu WU for their valuable discussion time towards

of this work. I would like to thank to Associate Professor Dr. Nobukazu

TAKAI and Mr. Nobuyoshi ISHIKAWA to their valuable support during

my present in Kobayashi laboratory.

I would like to thank my review committee members, Professors, Dr.

Kuniyuki MOTOJIMA, Dr. Sadao ADACHI, Dr. Yasunori KOBORI and

Dr. Yasushi YUMINAKA.

I would like to forward my gratitude to Universiti Malaysia Perlis

(UniMAP) and the Malaysian Government for permission to pursue Ph.D.

Acknowledgement

ii

degree and provide the financial support.

Finally, I also would like to thank to my parent Haji Mohyar Haji

Salleh and Hajah Muslimah Haji Sapuan, my mother in law Hajah Che

Chom Haji Ahmad, my beloved wife Siti Hajar Haji Che Haris and my

sons, Muhammad Azrul Aqil, Muhammad Azrul Arif, Muhammad Azrul

Adha and Muhammad Azrul Anas, for their patience, ‘dhua’, cooperation

and endless moral support.

Declaration

iii

Declaration

I hereby declare that this submission is my own work and that, to

the best of my knowledge and belief, it contains no material previously

published or written by another person, nor material which has been

accepted for the award of any other degree of the university or other

institute of higher learning, except where due acknowledgement has

been made in the text.

Signature:

Name: Shaiful Nizam Bin Mohyar

Student No.: 12820473

Date:

Table of contents

iv

Table of contents

Acknowledgement i

Declaration iii

Table of contents iv

List of figures vii

List of table x

Abstract xi

Chapter 1

DATA CONVERTERS - 1 -

1.1 Introduction - 1 -

1.2 Motivation - 1 -

1.3 Objectives - 3 -

1.4 Approach - 3 -

1.5 Outline of the thesis - 4 -

References - 4 -

Chapter 2

DIGITAL-TO-ANALOG CONVERTERS - 5 -


2.2 DAC specification - 11 -

2.2.1 General specification - 11 -

2.2.2 Static specification - 12 -

2.2.3 Dynamic specification - 15 -

2.3 High speed DAC architectures - 17 -

2.3.1 Binary-weighted current-steering DAC - 18 -

2.3.2 Unary-weighted current-steering DAC - 19 -

2.3.3 Segmented current-steering DAC - 20 -

2.4 Summary - 22 -

References - 23 -

Table of contents

v

Chapter 3

LITERATURE REVIEWS:SOURCES OF THE CURRENT SOURCE

MISMATCH AND THEIR CORRECTION TECHNIQUES - 24 -


3.2 Types of errors - 25 -

3.3 Mismatch Sources - 26 -

3.3.1 Effects of transistor mismatch - 26 -

3.3.2 Effects of switching behavior - 27 -

3.3.3 Effects of parasitics - 30 -

3.4 Statistical model design - 30 -

3.5 Correction techniques - 33 -

3.5.1 Dynamic element matching (DEM) based switching

schemes - 33 -

3.5.2 Layout based switching schemes - 41 -

3.5.3 Calibration techniques - 46 -

3.5.4 Return-to-Zero (RZ) switching technique - 55 -

3.5.5 Differential Quad Switching (DQS) technique - 57 -

3.6 Summary - 57 -

References - 60 -

Chapter 4

PROPOSED ALGORITHMS AND CALIBRATION TECHNIQUES - 63 -


4.2 Proposed calibration technique I: SFDR improvement algorithm for

current-steering DACs - 63 -

4.2.1 Switching-Sequence Post-Adjustment (SSPA) - 67 -

4.2.2 One-Element-Shifting (OES) algorithm - 68 -

4.2.3 Combination of SSPA and OES (Investigated algorithm) - 71 -

4.2.4 Calibration technique - 72 -

4.2.5 Simulation results and discussion - 74 -

4.2.6 Conclusion - 78 -

References - 80 -

Table of contents

vi

4.3 Proposed calibration technique II: Algorithm to improve current-steering

DAC linearity by digital calibration of selected pairs of current source

cells - 81 -

4.3.1 Half-unary architecture - 82 -

4.3.2 3-stage current source sorting (3S-CS) algorithm - 84 -

4.3.3 Circuits - 88 -

4.3.3.1 Current source design - 88 -

4.3.3.2 Cascoded current source cell - 89 -

4.3.3.3 Folded cascode current source cell - 94 -

4.3.3.4 Digital current measurement circuit based on

ring oscillator - 97 -

4.3.3.5 Calibration technique - 101 -

4.3.3.6 Consideration of re-calibration - 102 -

4.3.3.7 Look-up table in memory based decoder - 103 -

4.3.4 Clock-tree based layout - 104 -

4.3.5 Simulation results and discussions - 105 -

4.3.6 Conclusion - 110 -

References - 111 -

Chapter 5

CONCLUSIONS - 113 -

List of publications - 116 -

List of figures

vii

List of figures

Figure 1-1 A DAC used in transmitter path. - 3 -

Figure 2-1 DAC as a black box. - 5 -

Figure 2-2 Basic DAC with external reference. - 6 -

Figure 2-3 Bandwidth employed by the different types of DAC. - 7 -

Figure 2-4 Anti-aliasing transition region of differences type of DAC. - 8 -

Figure 2-5 DAC applications in respect of different resolutions

and sampling speeds. - 11 -

Figure 2-6 Illustration of relation between accuracy and precision. - 12 -

Figure 2-7 Definition of INL. - 13 -

Figure 2-8 Monotonic DAC. - 14 -

Figure 2-9 Non-monotonic DAC. - 14 -

Figure 2-10 Illustration of spurious free dynamic range. - 15 -

Figure 2-11 Phenomenon of glitch. - 15 -

Figure 2-12 Glitch mechanism caused by non-ideal switches. - 16 -

Figure 2-13 DAC with open-loop system. - 16 -

Figure 2-14 DAC with closed-loop system. - 17 -

Figure 2-15 “Set and forget” system. - 17 -

Figure 2-16 A 3-bit binary-weighted current-steering DAC. - 19 -

Figure 2-17 A 3-bit unary-weighted current-steering DAC. - 20 -

Figure 2-18 A (M+N)-bit segmented current-steering DAC. - 20 -

Figure 2-19 Normalized required area versus percentage of

segmentation [3]. - 21 -

Figure 3-1 A 3-bit unary weighted DAC with ideal current source cells

and linear tranfer function (dashed blackline). - 28 -

Figure 3-2 Illustration of temperature measurement using a classic

thermometer. - 28 -

Figure 3-3 Non-linear tranfer function (solid red line) caused by

mismatched current source cells. - 29 -

Figure 3-4 Parasitic capacitances at node, Vn. - 30 -

List of figures

viii

Figure 3-5 Mismatched current sources cell with a compensated non-

linear tranfer function (solid green line) by re-sequencing

the current source selections. - 34 -

Figure 3-6 Generalized DEM technique. - 34 -

Figure 3-7 Partial Random DEM (PRDEM) technique [16]. - 35 -

Figure 3-8 Random Multiple Data-Weighted-Averaging (RMDWA)

technique [17]. - 36 -

Figure 3-10 Randomized thermometer coding (RTC) technique [19]. - 38 -

Figure 3-11 Random swapping thermometer coding (RSTC) technique

[9]. - 39 -

Figure 3-12 Comparison of possible glitches occurring in each input

between Thermometer coding, DWA and OES [20]. - 40 -

Figure 3-13 Symmetrical switching schemes [21]. - 41 -

Figure 3-14 Hierarchical symmetrical switching schemes [22]. - 42 -

Figure 3-15 Q2 random walk switching schemes [23]. - 43 -

Figure 3-16 INL bounded switching scheme [6]. - 45 -

Figure 3-17 Self-calibrated DAC technique [24]. - 47 -

Figure 3-18 DAC with SSPA calibration technique [25]. - 49 -

Figure 3-19 DAC with complete-folding calibration technique [26]. - 50 -

Figure 3-20 DAC with DMM calibration technique [27]. - 52 -

Figure 3-21 DAC block diagram with 3D-SC calibration technique [28]. - 55 -

Figure 3-22 Comparison between Non-Return-to-Zero (NRZ) and

Return-to-Zero (RZ) [29]. - 56 -

Figure 4-1 Transfer function. (a) Ideal. (b) Mismatch. - 64 -

Figure 4-2 Output spectrum. (a) Ideal. (b) Mismatch. - 64 -

Figure 4-3 Current source cell selection with the conventional

thermometer- coded algorithm. - 65 -

Figure 4-4 Relation between glitch energy and number of switches. - 66 -

Figure 4-5 6 steps of SSPA calibration. - 68 -

Figure 4-6 Current source cell selection for OES. - 69 -

Figure 4-7 Graph of plotted data in Table 4-1. - 70 -

Figure 4-8 Investigated algorithm. - 71 -

Figure 4-9 Proposed calibration technique. - 72 -

Figure 4-10 Illustration of the process steps in the temporary memory,

LUT decoder and OES block. - 74 -

Figure 4-11 Error characteristics. - 76 -

List of figures

ix

Figure 4-12 Output spectrum of different algorithms. - 77 -

Figure 4-13 SFDR performances versus mismatch percentages obtained

by different algorithms and number of bits. - 79 -

Figure 4-14 Estimation of glitch performances versus input frequencies

obtained by different algorithms and number of bits. - 79 -

Figure 4-15 Proposed half-unary architecture. - 82 -

Figure 4-16 Mirrored current source structure. - 84 -

Figure 4-17 Proposed 3-stage current sorting method. - 87 -

Figure 4-18 Current source structures. - 88 -

Figure 4-19 Transistor structure. - 91 -

Figure 4-20 Multiple current sources with same transistor size. - 91 -

Figure 4-21 Multiple current sources with different transistor size. - 92 -

Figure 4-22 Current source layout. - 92 -

Figure 4-23 Current source layout with compensated width. - 93 -

Figure 4-24 Half-unary current source. - 93 -

Figure 4-25 Current mirror structure. - 95 -

Figure 4-26 Folded cascode current mirror structure. - 97 -

Figure 4-27 Examples of previously published calibration techniques. - 99 -

Figure 4-28 Digital measurement circuit and different measured

current cases. - 100 -

Figure 4-29 Flows of calibration technique. - 102 -

Figure 4-30 Clock-tree-like based layout. - 105 -

Figure 4-31 INL Yield. - 106 -

Figure 4-32 DNL Yield. - 107 -

Figure 4-33 Average SFDR performance vs. standard deviation - 107 -

Figure 4-34 2nd order harmonic distortion. - 108 -

Figure 4-35 3rd order harmonic distortion. - 108 -

Figure 4-36 Output spectrum before calibration (= 0.05A). - 109 -

Figure 4-37 Output spectrum after calibration (= 0.05A). - 109 -

List of tables

x

List of table

Table 1-1 D AC application. - 2 -

Table 2-1 Comparison between Nyquist-rate and oversampling DACs. - 22 -

Table 2-2 Comparison of different DAC systems. - 22 -

Table 2-3 Comparison of current-steering DAC architectures. - 23 -

Table 3-1 Summary of error types. - 57 -

Table 3-2 Different of mismatch sources. - 58 -

Table 3-3 Comparison of different statistical models. - 58 -

Table 3-4 Comparison of different statistical models. - 59 -

Table 4-1 Comparison of switching activities for different algorithms. - 70 -

Table 4-2 Simulation conditions. - 75 -

Table 4-3 Summary of SFDR comparison for several current cell

selection algorithms. - 78 -

Table 4.4 Types of memory. - 104 -

Table 4.5 Performance comparison between NOR and NAND based

flash memory [13]. - 104 -

Table 4-6 Simulation condition. - 106 -

Table 4-7 Performance comparison. - 111 -

Abstract

xi

Abstract

The demand for high-speed high-accuracy digital-to-analog converters

(DACs) is significantly increased due to the fast-growing market of the

telecommunication devices. As society needs faster, cheaper and reliable

communication, DAC block design becomes complicated, although the

digital electronics as benefited from advances in CMOS technology. Due

to the small silicon chip area, fast sampling speed and high-resolution,

the current-steering architecture is extensively used for these applications.

With different architectures − binary-weighted, unary-weighted, and

segmented, current-steering DACs are constructed by groups of matched

current sources. However, their performance is limited by many non-

linear mechanisms such as random mismatch errors, gradient effects,

code and voltage dependence of finite output impedance, non-linear

settling time, charge injection, and switch timing errors. In this

dissertation, non-linearity compensation techniques are presented to

improve both static and dynamic performances of the current-steering

DACs due to the random static mismatch of the current sources generated

by the difference value of threshold voltage among the current sources in

the current mirrored structure.

Two algorithms which are “Switching-Sequence Post-Adjustment

(SSPA) with One-Element-Shifting (OES)” and “3-Stages Current

Source Sorting (3S-CS)” are adopted in digital calibration technique. By

requiring only an analog comparator, the current values of the current

sources are measured and stored by temporary registers. Through the

calibration, the optimized switching sequence is obtained. Finally, using

the other algorithm, the start point of elements is shifted by one element

for each clock cycle. A 10-bit unary-weighted current steering

architecture is employed to validate the effectiveness of our proposed

technique based on combination of SSPA and OES. By simulating the

proposed technique with sampling frequency, fs of 409.6 MHz, input

frequency, fin of 143.3 MHz, and standard deviation of random errors of

0.06 A that are generated by normal distribution, SFDR level of 82 dBc

is obtained. Compared with the conventional unary weighted current-

Abstract

xii

steering DAC, it is improved by 24 dB by using our proposed technique.

As extension to our study in developing digital algorithm for current

source mismatch reduction techniques, 3S-CS is developed and adopted

in a new current-steering DAC architecture based on half-unary weighted

current source cells. By introducing a digital current measurement circuit

to replace the usage of an analog comparator in previous work, the current

values are measured and stored in temporary registers. Differently from

the previous work, the accurate current values are strongly dependent on

the analog comparator accuracy. On the other hand, in this work, the

current values are converted to the number of a counter. It is simple and

easy compared to an analog comparator. Moreover, with the additional of

a layout called “clock-tree” which is able to provide such as balanced

routing layout, the effect of propagation delay differences between

current source cells and switches, current sources and load resistors are

also reduced. Assuming that the errors are sourced due to the threshold

voltage mismatches in the mirrored current source structure, the validity

of the proposed technique in reducing the effect of the random static

mismatch is simulated in MATLAB. A 12-bit half-unary current-steering

DAC with sampling frequency, fs of 819.2 MHz, input frequency, fin of

12.8 MHz, and the normal distribution of random errors from 0.001A up

to 0.25A of standard deviation is analyzed. From the simulation results,

SFDR of more than 95 dBc is obtained. It is more than 17 dB better than

the conventional unary weighted current-steering DAC with

thermometer-coded switching scheme. In comparison with the same half-

unary weighted, SFDR obtains a value 10 dB better than that obtained

before the calibration.

As conclusion, these two techniques effectively compensate the random

mismatch errors by selectively regrouping current sources based on

current comparisons and rearranging the switching selection. The

implementation of these two calibration techniques requires only an

analog comparator in the proposed technique I and uses a digital

calibration circuit in the proposed technique II, that makes them suitable

for DAC design in the low-voltage process. The simulation results show

that these calibration techniques have the superior performance in

compensating random mismatch errors as compared to state-of-the-art.

Chapter 1: Data Converters

- 1 -

Chapter 1

DATA CONVERTERS

1.1 Introduction

Converter is a device that converts from one form to another form. In the

electronic devices, it is a key component block that is functioned as a bridge

to connect between analog to digital worlds or in vice versa. Depending on

the application, the converter names are differed such as video converter,

power converter, etc. Here, the data converters that are widely used in

telecommunication devices are concerned.

Data converter may refer to the analog-to-digital converters (ADCs or A/Ds),

the digital-to-analog converters (DACs or D/As) or any other device used in

data conversion. In telecommunication application, either wired or wireless,

most of the signal processing is done in the digital domain. It is necessary to

change the form of signal especially from analog domain to digital domain

using ADC. The advantages of processing the data in digital domain are:

to improve signal analysis potential.

to provide more robust data storage.

to increase accuracy of the transmission.

However, the information is still to be transferred with analog signals using

DAC. Therefore, it still becomes a crucial building block for many

telecommunication devices. In this dissertation, DAC design becomes the

main topic to be focused.

Recently, DACs have been extensively used in many applications. Since the

decades, most engineers have developed and used DACs based on Nyquist-

Shannon sampling theorem and nowadays monolithic DACs have become

widely available. The monolithic DACs are subject to growing interest due to

the rapid expanding market for digital signal processing. The details of each

application based on digital input are summarized in Table 1-1.

1.2 Motivation

Recently, fast-growing markets for telecommunication devices such as

mobile phones, wireless modems, and avionics devices have increased

demand for high-speed, high-accuracy DACs. In the field of wireless

communication, DAC accuracy is especially important for ensuring there no

leakage noise from the transmitter to the receiver during transmission. As

society needs faster, cheaper, and more reliable communication, this block

design becomes more complicate. Although, the DAC design is generally


- 2 -

benefited from CMOS technology scaling, the shrinkage of transistor allows

higher sampling rates and hence larger signal bandwidths.

Table 1-1 DAC application.

Application Examples Devices Function

Digital audio

CD/MP3 players,

HD radio,

Digital

telephones

Audio amplifier

Produces DC voltage

gain with

microcontroller

commands.

Digital video DVD players,

DTV Video decoder

Produces analog video

signals of various

formats, along with

optimizing of output

levels.

Display

electronics

LCD computer

screen,

LCD TV screen

Produces analog

outputs such as Red,

Green, Blue (RGB)

signals to drive a

display.

Data

acquisition

system

Converts measured data

into analog signals.

Calibration

Tuning in

embedded

systems

BIST circuit

Provides dynamic

calibration for gain and

voltage offset for

accuracy in test and

measurement systems.

Waveform

generation Test equipment

Waveform

function

generators

Produce pure waveform

for testing.

Industrial

control system

Motor,

Valves,

Transducer

excitation

Controls require

voltage control signals

driven by a processor or

controller.

Data

distribution

system

Provides the dynamic

change of voltages

during operation of a

system

Digital

potentiometer

Utilizes the string DAC

with some modification

for realizing a fully

digital potentiometer

implementation.

Software radio

Converts a signal into

analog for transmission

in the mixer circuit

Note: CD – compact disc, MP3 – moving picture 3-layer , HD – high division, DVD –

digital video decoder, DTV – digital television, LCD – liquid crystal display, BIST – built-

in self-test

The switching of current is faster, hence the DAC linearity at higher speeds

is also improved. However, there are still fundamental physical constraints—

such as noise, component matching, and fabrication process parasitics—that

need to be alleviated [1]-[3]. DAC linearity must be sufficient to


- 3 -

accommodate requirements, despite these constraints. Therefore, many DAC

designers face common basic challenges in the process of designing different

technology nodes such as transistor model characterization, basic DAC cell

optimization, and transistor matching. For resolution less than 10 bits, such

constraints are not so significant, but when the resolution increases, these

constraints are a major problem [1]-[3].

Figure 1-1 A DAC used in transmitter path.

Figure 1-1 illustrates the DAC used in the transmitter path. In order to

reconstruct a digital signal generating from digital signal processing (DSP)

unit into high purity of analog signal, an accurate DAC with sufficient

spurious free dynamic range (SFDR) level is highly required. However, most

of DACs suffer from their linearity degradation due to their component non-

idealities. Hence, the improvement of DAC linearity as well as its dynamic

performance becomes more important.

1.3 Objectives

The main objective of this study is to design a high SFDR DAC for

communication application. Therefore, the effect of the component non-

idealities must be reduced. The aims of this study are to investigate the

feasible technique for reducing the effect and then, develop new techniques

based on the investigation results. The investigation is done by focusing on

three aspects; DAC architectures, error correction techniques and circuit

implementations.

1.4 Approach

To attain the main objective, the segmented current-steering DAC

architecture is considered in order to obtain a balanced performance. The

error correction techniques are recognized as an indispensable resource to

achieve accuracy and robustness in high-performance DACs. In this study,

two digital algorithms based on switching scheme are developed to eliminate

the static errors. In addition, to reduce the risks of DAC performance


- 4 -

degradation during conversion process due to the error measurement circuit,

the foreground mode calibration is chosen. Two new digital algorithms are

developed and their performances are investigated:

(1) Combination of switching-sequence post-adjustment and one element

shifting (SSPAOES) based digital calibration algorithm in 10-bit unary-

weighted current-steering DAC.

(2) 3-stage current sorting based digital calibration algorithm in 12-bit half-

unary weighted current-steering DAC. In addition, the clock-tree based

layout is introduced to provide a balanced routing performance for

reducing the effects of parasitics which further degrade DAC dynamic

performance.

Based on these two algorithms, the effect of static errors due to the current

source mismatches is simulated and analysed. INL, DNL, SFDR and glitch

are parameters that are concerned in this study.

1.5 Outline of the thesis

The outline of this dissertation is as follows:

Chapter 1

This chapter introduces an overview to the data converters, the motivation

and the objectives of this study and the proposed approaches.

Chapter 2

This chapter discusses the basic DAC specifications and its architectures.

Chapter 3

This chapter reviews the existing research works related to techniques used

for random static mismatch reduction in current-steering DACs.

Chapter 4 This chapter presents proposed calibration techniques. Their simulation

results are presented and discussed.

Chapter 5 This chapter summarizes conclusions obtained through this study.

References

[1] R. J. van de Plassche, Integrated Analog-to-Digital and Digital-to-

Analog Converters, Kluwer Academic Publishers, 1994.

[2] F. Maloberti, Data Converter, Springer, 2007.

[3] G Radulov, Smart and Flexible Digital-to Analog Converter, Analog

Circuit and Signal Processing (ACSP), Springer, 2011.

Chapter 2: Digital-to-Analog Converters

- 5 -

Chapter 2

DIGITAL-TO-ANALOG CONVERTERS

In this chapter, section 2.1 introduces a basic principle on how DAC operates

and learns how to distinguish DAC by its types. Then, the related DAC

specification terms which are mostly used in this work are discussed in

section 2.2. Finally, different DAC architectures are reviewed in section 2.3

to understand their strength and weakness for better implementation.

2.1 Introduction

The earliest recorded binary DAC in the history is reported in 18th century

[1]. However it was used for hydraulic in sophisticated system built to meter

water. In the modern world, converters are used in converting data which are

developed around 1825-1875.

In contrast with ADCs, DACs work by converting digital form into its analog

form in electronic fields. The conversion process happens when an external

sampling clock is used to sample data and regenerate a continuous analog

output thru connection of all sampled points. Theoretically, for regeneration

of a continuous analog signal, a sampling clock, Ts must be at least half

compared to the signal, Tin that wants to be sampled (Equation 2.1).

𝑇𝑠 ≥1

2𝑇𝑖𝑛 (𝟐. 𝟏)

Otherwise, signal distortions are introduced in reconstructed signal caused by

time uncertainty of the sampling clock. Furthermore, the undesired repetition

of spectra from the input signal into the baseband due to aliasing effect also

occurs. In works of [2], [3] and [4], the detailed discussion on these basic

DAC concepts is recommended.

Figure 2-1 DAC as a black box.

Figure 2-1 shows that a DAC reconstructs the digital signal form into the

analog signal form (dotted line). Apparently, by contracting by small steps

(high-resolution), a better analog signal waveform can be generated

(waveform generation) or regenerated (analog signal reconstruction).


- 6 -

Figure 2-2 Basic DAC with external reference.

Recently, there are many types of DAC depending on their architectures and

components such as pulse width modulators (PWM), delta-sigma DACs,

binary weighted DACs and others. The details of selected architecture types

will be discussed later in section 2.3.

Figure 2-2 shows that an example of an n-bit binary weighted DAC is applying

to a parallel digital input of binary codes, B0 to Bn-1 and converting it into an

analog output, Vout. Tclock is the timing period of each cycle to read each

sampled data, while Rref is a reference value either in voltage, current or charge.

In practice, the reference value, Rref is used either as a voltage source or a

current source.

The relationship between the input and the output of a DAC can be described

by the following equation:

𝑉𝑜𝑢𝑡 = ∑ 𝐵𝑚2𝑚𝑅𝑟𝑒𝑓

𝑛−1

𝑚=0

(𝟐. 𝟐)

Since B0 is the least significant bit (LSB) and Bn-1 is the most significant bit

(MSB) of the DAC input, only in case of Bm = 1, the value of bit m is added to

the output signal while in case of Bm = 0, the value of bit m is NOT added to

the output. Therefore, Equation 2.2 can be changed into:

𝑉𝑜𝑢𝑡 = ∑ 𝐵𝑚2−𝑚𝑅𝑟𝑒𝑓

𝑛−1

𝑚=0

(𝟐. 𝟑)

Due to the quantization process, the output signal can only be changed with

the minimum step size equal to 𝑅𝑟𝑒𝑓.Thus, the quantization step, qs is equal to

𝑅𝑟𝑒𝑓 and qs = 1 , then, qs can be expressed as in Equation 2.4:


- 7 -

𝑞𝑠 = 2−𝑛+1𝑅𝑟𝑒𝑓 (𝟐. 𝟒)

Differentiating a DAC with others besides its structure is its type. Normally,

DAC type can be classified into two categories: Nyquist-rate and oversampling.

The difference between the following design strategies is due to the bandwidth

usage. The Nyquist-rate DAC input utilizes a large fraction of the available

bandwidth (Figure 2-3(a)). Whereas the oversampling uses an input-band that

only occupies a small part of the Nyquist range (Figure 2-3(b)).

(a) Nyquist-rate. (b) Oversampling.

Figure 2-3 Bandwidth employed by the different types of DAC.

In case of the total quantization noise power, the Nyquist-rate DAC contains

larger noise due to its larger fraction of bandwidth. On the other hand, the

oversampling DAC contains only small fraction of the total noise in the signal

band. The ratio between the Nyquist limit and the signal band, 𝑓𝑠

(2𝑓𝐵), where fs is

the sampling frequency and fB is input-band frequency.

This ratio is called oversampling ratio (OSR). Nyquist-rate DACs have a small

OSR, typically less than 8 while oversampling DACs have obviously much

larger than Nyquist-rate DACs; in some cases, OSR can be several hundreds.

Due to a small transition region in Nyquist-rate DACs leads to difficult

specifications for anti-aliasing filter design (Figure 2-4(a)). On the one hand, a

larger transition region in oversampling DACs leads to relax of the anti-aliasing

(Figure 2-4(b)). However, on the other hand the relaxing of the anti-aliasing

filter in Nyquist DACs can be achieved by reducing the effects of 2nd and 3rd

order harmonic distortions in signal band using our proposed techniques

mentioned in Chapter 4.


- 8 -

(a) Nyquist-rate. (b) Oversampling.

Figure 2-4 Anti-aliasing transition region of differences type of DAC.

In case of using DAC, its input signal is a digital signal (refer Figure 2-1).

Its signal is obtained through switches between two voltage levels and

representing by two states of a Boolean value (0 and 1). When an analog

signal from the sampled data of digital signal is reconstructed, the

quantization errors are introduced by digital sampling and they are

irreversible. Due to these errors, the accuracy of the DAC is limited by

manifesting as low-level noise to the reconstructed analog signal. To estimate

these errors, the mean-squares error due to the quantization can be calculated.

These errors can be estimated by assuming that:

constant probability distribution of over all ranges is zero.

they are independent of the analog signal.

Then, the mean-squares value of can be expressed as in Equation 2.5.

𝐸(𝜀2) =1

𝑞𝑠∫ 𝜀2

𝑞𝑠2

−𝑞𝑠2

𝑑𝜀 (𝟐. 𝟓)

The quantization error also can be expressed as quantization error voltage,

𝜀𝑞𝑛𝑠2 which is similar to the rms quantization error voltage, 𝜀𝑞𝑛𝑠

2 = 𝐸(𝜀2).

Therefore, the rms quantization error voltage, 𝜀𝑞𝑛𝑠2 is:

𝜀𝑞𝑛𝑠2 =

1

12𝑞𝑠

2 (𝟐. 𝟔)

In case of n binary weighted is used, the number of quantization levels is

equal to 2𝑛 − 1. Then, the maximum peak-to-peak amplitude equals to 2𝑛𝑞𝑠

before the next quantization level is reached. However, this maximum peak-

to-peak level cannot always be obtained. So, the maximum peak-to-peak

level when sine wave signal is used can be ranged between:

Anti-aliasing

transition

band

Anti-aliasing

transition

band


- 9 -

(2𝑛 − 1)𝑞𝑠 ≤ 𝐴𝑝𝑝 ≤ 2𝑛𝑞𝑠 (𝟐. 𝟕)

As 𝐴𝑝𝑝 is the peak-to-peak amplitude of the input or output signal used in the

system, 𝐴𝑝𝑝 can be approximated as in Equation 2.8 in case where the

converter uses a large number of bits

𝐴𝑝𝑝 = 2𝑛𝑞𝑠 (𝟐. 𝟖)

By substituting 𝐴𝑝 =𝐴𝑝𝑝

2 in Equation 2.9, the rms signal value 𝐴𝑟𝑚𝑠 of sine

wave signal is calculated as:

𝐴𝑟𝑚𝑠 =𝐴𝑝

√2=

2𝑛𝑞𝑠

2√2 (𝟐. 𝟗)

The signal-to-noise ratio of a DAC can be calculated by dividing Equation 2.9

with the square root of Equation 2.6. As a result:

𝑆/𝑁 =

2𝑛𝑞𝑠

2√2

√ 112 𝑞𝑠

2

= 2𝑛√1.5 (𝟐. 𝟏𝟎)

By simplifying into decibels form, the 𝑆/𝑁 can be represented as:

𝑆/𝑁 = 𝑛20log (2) +1

220 (log(3) − log (2))

= 6.02𝑛 + 1.76 dB (𝟐. 𝟏𝟏)

Equation 2.11 shows that 𝑆/𝑁 increases by 6 dB for an extra additional bit.

Since the quantization error in a non-correlated sampled system can be

modeled as a random process like a noise, a noise density per unit bandwidth

𝜀𝑞𝑛𝑠2 (𝑓) can be derived based on in Equation 2.6. Note that 𝑓𝑞𝑛𝑠 is the

quantization noise bandwidth and 𝑓𝑠 is the sampling frequency, and the

relation between 𝑓𝑞𝑛𝑠 and 𝑓𝑠 is 𝑓𝑞𝑛𝑠 =1

2𝑓𝑠. So, 𝜀𝑞𝑛𝑠

2 (𝑓) is expressed as:

𝜀𝑞𝑛𝑠2 (𝑓) =

𝑞𝑠2

12𝑓𝑞𝑛𝑠=

𝑞𝑠2

6𝑓𝑠 (𝟐. 𝟏𝟐)

To express the 𝑆/𝑁 as density as in Equation 2.10:


- 10 -

𝑆/𝑁(𝑓) =

2𝑛𝑞𝑠

2√2

√𝑞𝑠

2

6𝑓𝑠

= 2𝑛−1√3𝑓𝑠 (𝟐. 𝟏𝟑)

In case of the system that does not use Nyquist sampling, the 𝑆/𝑁 with a

bandwidth equal to 𝑓𝑠𝑖𝑔 also can be expressed by dividing Equation 2.13

with √𝑓𝑠𝑖𝑔 as:

𝑆/𝑁𝑠𝑦𝑠𝑡𝑒𝑚 = 2𝑛−1√3𝑓𝑠

𝑓𝑠𝑖𝑔 (𝟐. 𝟏𝟒)

Equation 2.14 also validates the DAC that uses much higher sampling

frequency than the maximum signal frequency such as oversampling DAC.

In this type of DAC, the quantization error is randomized over a large

frequency band. As a result, the quantization noise density is reduced, and the

effective resolution increases. By simplifying in decibels form, 𝑆/𝑁 of the

oversampled DAC can be expressed as:

𝑆/𝑁𝑠𝑦𝑠𝑡𝑒𝑚 = 𝑛 × 6.02𝑛 − 1.25 + 10𝑙𝑜𝑔𝑓𝑠

𝑓𝑠𝑖𝑔 dB (𝟐. 𝟏𝟓)

For example of 𝑓𝑠

𝑓𝑠𝑖𝑔= 8, then the 𝑆/𝑁 becomes:

𝑆/𝑁 = 6.02(𝑛 + 1) + 1.76 dB (𝟐. 𝟏𝟔)

Compared to Equation 2.11, the 𝑆/𝑁 increases by 6 dB or 1 bit for an

additional bit.


- 11 -

2.2 DAC specification

In this section, the DAC specification is discussed into three categories;

general specification, static specification and dynamic specification.

2.2.1 General specification

Resolution is the number of digital inputs received by a DAC to generate an

analog output signal from a digital input signal. It is normally indicated as

number of bits, N. It is also known as quantization step. By increasing the

number of bits, a smaller step size of the analog output can be produced, hence,

a better analog signal can be obtained. Modern Nyquist-rate and oversampling

DACs with resolution equal to or higher than 12-bits and 16-bits respectively

are specified as a high-resolution DAC.

Speed is determined by its sampling rate. Essentially, a high-speed DAC is

defined since the converter system runs with the sampling frequency equal to

or greater than 1 MS/s. But nowadays, high speed DACs between range from

30 MS/s to multi-GS/s with the resolutions between 8 and 16 bits are

extensively manufactured and widely used in vast areas such as wired and

wireless communications, instrumentation, radar, electronic warfare and other

applications. Figure 2-5 shows the DAC applications based on types of DAC.

Figure 2-5 DAC applications in respect of different resolutions and

sampling speeds.

Accuracy is the quality of the output of the DAC compared to the ideal based

on the code regards to the resolution used. There are two specifications related

to the accuracy. The first is absolute accuracy and the other is relative

accuracy (both will be further explained in next sub-chapter). In DAC design,

accuracy refers to the component matching which can be determined by its

relative accuracy.


- 12 -

Precision is the ability of a DAC in producing the values which are closed to

each other. In the other words, precision is related to reproducibility and

repeatability. 18-bit – 20-bit is required for 1-ppm-accurate DAC.

Figure 2-6 explains the relation between accuracy and precision. In case of

a high-precision low-accuracy DAC, this DAC has ability to produce a value

within a closer range without prior to the actually desired value (Figure 2-

6(a)). In case of a high-accuracy low-precision DAC it shows the ability to

produce the values that are nearer to the actual desired value but it cannot

obtain the repeatable value under the same condition (Figure 2-6(b)). While,

a high-precision high-accuracy means all the obtained values with a smaller

deviation among them and the mean of all values are nearer to the actually

desired value (Figure 2-6(c)). This kind of DACs are required especially for

instrumentation- testing and measuring applications.

(a) High precision-low accuracy. (b) High accuracy-low precision. (c) High

accuracy-high precision.

Figure 2-6 Illustration of relation between accuracy and precision.

2.2.2 Static specification

In certain reference books, static specifications are also known as DC

specifications. In this section and onwards, the word static specification is

referred.

Absolute accuracy is the actual full scale input or output (digital-to-analog

converter) signal depending on the reference either voltage, current or charge.

It is standardized by the National Bureau of Standards. In the modern system,

especially for integrated circuits, the reference source is commonly based on

the band-gap voltage of silicon. In general, absolute error is defined as the

difference between the actual and measured values. In case where the actual

value is unknown, the maximum possible error can be used.

Relative accuracy is the deviation of the output signal or output code of a

converter from a straight line drawn through zero to and full scale. However,

due to the non-ideal components, the output signal may be different from the

ideal signal caused by zero offset. Thus, the requirement for zero-offset error

correction method is also important. In most cases, the relative accuracy is

called as integral non-linearity (INL) or linearity. Basically, absolute


- 13 -

accuracy and relative accuracy are related to each other.

To understand the relationship between these two terms; absolute accuracy and

relative accuracy, an example of the current mismatch in a current source is

explained. Let consider, the actual current value of a current source cell is 1

mA with the accuracy of 0.1 mA. It means that the largest acceptable deviation

current value from the actual current value is between ±0.05 mA. So, the

possible value of this current source is between 1±0.05 mA which can be

anywhere between 0.95 mA to 1.05 mA. Here, 0.05 mA is the absolute error

value. To calculate the relative accuracy, the absolute error of 0.05 mA is

divided by the actual value of 1 mA. The relative accuracy is 0.05 or in

percentage of 5%.

For ideal transfer function for DAC, the maximum deviation of INL value is

not larger than ±1

2 LSB of a straight line through zero and full scale is shown

in Figure 2-7.

Figure 2-7 Definition of INL.

Generally, the DAC with the non-linearity less than or equal to ±1

2 LSB is

also known as monotonic DAC. Monotonic DAC is validated since the output

of the DAC never decreases with an increasing digital input. Figure 2-8 and

Figure 2-9 illustrate examples of monotonic and non-monotonic DACs. It is

possible to design DACs with guaranteed monotonic characteristic but mostly

without the half LSB linearity specification. These kinds of DACs are often

designed based on non-binary weighted DAC architecture. In other words, the

DAC with ±1

2 LSB integral non-linearity error is monotonic DAC but the

monotonic DAC does not necessarily have an integral non-linearity error

between±1

2 LSB.


- 14 -

Figure 2-8 Monotonic DAC.

Figure 2-9 Non-monotonic DAC.

Differential non-linearity (DNL) is the difference between two adjacent

analog signal values compared to the step size in LSB.

𝐷𝑁𝐿𝑘 = 𝐴𝑜𝑢𝑡(𝐷𝑘+1) − 𝐴𝑜𝑢𝑡(𝐷𝑘) − 1𝐿𝑆𝐵 (𝟐. 𝟏𝟕)

From Equation 2.17, the DNL error of a DAC is considered to be zero if each

𝐴𝑜𝑢𝑡(𝐷𝑘+1) − 𝐴𝑜𝑢𝑡(𝐷𝑘) is equal to 1 LSB. If the DNL is good, it means the

INL is also good but this is not always true when the opposite. Good DNL of

less than 1 LSB is guaranteed in monotonicity.


- 15 -

2.2.3 Dynamic specification

Spurious free dynamic range (SFDR) is defined as the ratio between the

power of fundamental signal and the power of the largest distortion or spur

(Figure 2-10). The unit of this specification is dependent on the reference

used; either decibels per full-scale, dBFS or decibels per carrier, dBc.

Figure 2-10 Illustration of spurious free dynamic range.

Glitch is a phenomenon that produces a spike or valley at each major carry

code transition especially in the MSB level. This generated spike or valley

may result in the distortion at the output that decreases the S/N ratio. For

certain application, this glitch may cause a big problem and become an

important key of performance especially for video applications. Figure 2-11

depicts the effect of glitch in DAC transfer function.

Figure 2-11 Phenomenon of glitch.

Figure 2-12 shows how the glitch happens. By using an example of 4-bit

binary-weighted DAC, the glitch mechanism due to the non-ideal switched is

explained. As the glitch mostly appears at mid-code transition, hence,

transition code between 0111 and 1000 is targeted. In the ideal case, once the

code changes from 0111 to 1000, it leads to SW1, SW2 and SW3 turned OFF

while SW4 turned ON. Nonetheless, due to the non-ideal switch, if the SW4

10001001

10101011

01100101

0111

0100

Digital input code

An

alo

g O

utp

ut

Volt

age


- 16 -

turns ON too fast before SW1, SW2 and SW3 turn OFF, a desired output of

code 1111 is obtained. In another case, if the SW4 turns OFF too slow, even

the SW1, SW2 and SW3 already turned OFF, the output of code 0000 is

obtained.

Figure 2-12 Glitch mechanism caused by non-ideal switches.

For DAC implementation, different configurations require for different DAC

specifications. DAC with the open-loop system as shown in Figure 2-13

requires high accuracy with precise DC specification due to its simple

implementation. Both INL and DNL are the key of its specification. As an

example of this open-loop system, a DAC output is used to drive the voltage

reference to effectively margin a linear regulator output in small increments.

Other examples of open-loop system are included such as test equipment and

data acquisition cards.

Figure 2-13 DAC with open-loop system.

On the other hand, a high-resolution DAC almost occupies in closed loop

system as shown in Figure 2-14 which is used for application such as motor

control. DNL is the key of specification. This system includes a feedback path,

which is used either ADC or sensor to detect an error signal and uses DAC for

correction.


- 17 -

Figure 2-14 DAC with closed-loop system.

The combination of these two systems, called as “set and forget” system, is

also possible. In such system, an adjustment or calibration is made once,

either at the time of manufacture of during installation. The system behaves

as a closed-loop system, and then it goes to the open-loop system. The

advantage of this system is to relax the initial accuracy requirement which

later can be compensated during adjustment.

Figure 2-15 “Set and forget” system.

However, the stability of this system becomes a key of its performance once

the feedback path is removed. An example of this system is implementing 12-

bit DAC for offset adjustment of 16-bit DAC. Figure 2-15 depicts the “set

and forget” system.

2.3 High speed DAC architectures

In this thesis, the design of a high-speed Nyquist-rate DAC for

telecommunication application is discussed. Commonly, three classes of

current-steering DACs are distinguished by their basic components used


- 18 -

namely resistor, capacitor and transistor. Within these three components,

transistor based current-steering DAC is more popular due to its small silicon

chip area and high speed conversion. Early current-steering DACs used

single-ended output, but differential output is preferable. This is due to its low

output impedance. Nowadays, most of DACs use differential output because

of its advantages; lower output impedance and better common mode noise

attenuation. There are three common architectures related to this class of

DAC; binary-weighted, unary-weighted and segmented DAC architectures.

The details will be discussed in next subsection.

2.3.1 Binary-weighted current-steering DAC

The binary-weighted DAC is the simplest architecture in current-steering

DAC design. It is composed of matched current source cells with different

weights. Figure 2-16 is an example of a 3-bit binary-weighted current-

steering DAC. As shown in Figure 2-16, RL is represented for load resistor,

SW1, SW2 and SW3 are the switches controlled by digital input code and the

output voltage, Vout, is the difference between Vdd and the potential generated

by current I flowing through the load resistor RL, as in Equation 2.18.

𝑉𝑜𝑢𝑡 = 𝑉𝑑𝑑 − 𝐼𝑜 𝑅𝐿 (𝟐. 𝟏𝟖)

The binary-weighted current-steering DAC has advantage of high-speed

sampling. Since only a small digital signal is used without any decoding logic

requirement, it is implemented with its low power and small chip area.

However, its disadvantages are that glitch energy is large due to the mismatch

in switching between the MSB bit and all smaller bits especially in mid-code

transition as previously explained in Section 2.2.3. Furthermore, input-output

monotonicity is not guaranteed. In order to maintain a good performance

against large DNL and dynamic errors, the DNL error can be approximately

predicted using Equation 2.19. By assuming a normal distribution for unit

current sources with a standard deviation, the DNL error can be

predicted as:

𝜎2(∆𝐼) = (2𝑁 − 1)𝜎2(𝐼)

𝜎(∆𝐼) = √(2𝑁 − 1)𝜎(∆𝐼)

𝐼𝐿𝑆𝐵 (𝟐. 𝟏𝟗)

This sigma, 𝜎(∆𝐼), is a good approximation for the DNL error.


- 19 -

Figure 2-16 A 3-bit binary-weighted current-steering DAC.

2.3.2 Unary-weighted current-steering DAC

The unary-weighted current-steering DAC in Figure 2-17 was introduced to

overcome the disadvantages of the binary-weighted DAC. The unary-

weighted architecture has lower glitch energy because 2N-1 unit current

sources with identical weight (Equation 2.20) are used for N-bit resolution.

𝐼1 = 𝐼2 = 𝐼3 = 𝐼4 = 𝐼5 = 𝐼6 = 𝐼7 = 𝐼 (𝟐. 𝟐𝟎)

This means that smaller current source weights are used, then glitch

magnitude is smaller. In addition, these 2N-1 unit current sources with

identical weights can include redundant cells which enable output

optimization (optimized switching schemes) as well as flexible current source

selection (different switching selections for the same digital input). When the

digital input is 4, then SW1, SW2, SW3, SW4 turn on and SW5, SW6, SW7

turn off, and the output voltage Vout is given by the difference between Vdd

and potential drop of I through that load resistor, RL as in Equation 2.18.

This architecture has advantage that glitch energy is small. This is because

unary weighted DAC produces a small step compared to binary weighted one.

Also input-output monotonicity characteristics are guaranteed, while the

drawbacks are larger chip area, higher power consumption and slower

sampling speed as a result of large decoder. Compared to binary weighted

architecture, the approximate DNL error for this type of DAC architecture

can be given by:

𝜎(∆𝐼) = 𝜎(∆𝐼)

𝐼𝐿𝑆𝐵 (𝟐. 𝟐𝟏)

Compared to binary weighted DAC architecture, unary weighted one has

small DNL error.


- 20 -

Figure 2-17 A 3-bit unary-weighted current-steering DAC.

2.3.3 Segmented current-steering DAC

In many cases, a segmented (combination) architecture is used; a unary-

weighted architecture is used for higher-order bits and a binary-weighted

architecture for lower-order bits (Figure 2-18).

For a partial segmentation between unary-weighted and binary-weighted

circuits, the accuracy of the most significant bit (MSB) for the binary-weighted

can be less stringent. Normally, the segmentation is considered to depend on

the requirements, the resolution on the DAC and the matching accuracy of the

technology used.

Figure 2-18 A (M+N)-bit segmented current-steering DAC.

I4=I I3=I I2=I

SW4 SW3 SW2

Vdd

RL

+

Vout

⧿

I5=I

SW5

I1=I

SW1

I6=I

SW6

I7=I

SW7

SW2 SW1SWM-1

IM=I

SWM

IM-1=I I2=I I1=I

…SW2

Vdd

RL

SW1SWN-1

IN=2N-1I

SWN

IN-1=2N-2I I2=2I I1=I

…

Unary weighted Binary weighted

MSB LSB

+

Vout

⧿


- 21 -

Figure 2-19 Normalized required area versus percentage of segmentation

[3].

Figure 2-19 shows the chart that depicts die size versus segmentation. The die

size is reduced if 100% of unary-weighted circuit is used compared to no

segmentation is used (100% of binary-weighted circuit). This segmented

topology can achieve a good balance of chip area, power, speed and glitch

energy. Since the segmented architecture is a combination of binary weighted

and unary weighted circuits, its DNL error can be approximated by:

𝜎(∆𝐼) = √(2𝐵+1 − 1)𝜎(∆𝐼)

𝐼𝐿𝑆𝐵 (𝟐. 𝟐𝟐)

This equation is valid for the combination of binary (B = N-1) and the unary

implementation (B=0).


- 22 -

2.4 Summary

The difference between Nyquist-rate and oversampling DACs has been

discussed in Chapter 2.1. Table 2-1 summarizes the advantages and

disadvantages between these DACs.

Table 2-1 Comparison between Nyquist-rate and oversampling DACs.

Nyquist-rate Oversampling

Occupied

bandwidth Large Small

Transition region

of anti-aliasing

filter

Small Large

Quantization noise Large Small

Oversampling ratio Small Large

Different DAC applications require different specifications discussed in

Chapter 2.2. Summary of the DAC implementation is tabulated in Table 2-2.

Table 2-2 Comparison of different DAC systems.

Open-

loop

Closed-

loop

Combination of

open - closed loops

Specification Accuracy Resolution Depending on

application

Physical

system

w/o

feedback

w/

feedback

Start : w/ feedback

End : w/o feedback

Requirement INL &

DNL

DNL

Monotonic

Depending on

application

Relaxation - INL INL

The current-steering DAC architectures for high-speed DAC have been

described in Chapter 2.3. Each architecture has its own strength and

weakness points. Table 2-3 summarizes the differences between these three

architectures.


- 23 -

Table 2-3 Comparison of current-steering DAC architectures.

Binary Unary Segmented

Chip area

Sampling

speed

Power

Complexity

Glitch energy

Redundancy

Monotonicity

DNL

INL = = =

References

[1] W. Kester, The Data Conversion Handbook, Elsevier (2005).

[2] R. van de Plassche, Integrated Analog-to-Digital and Digital-to- Analog

Converters, Kluwer Academics Publishers (1994).

[3] A. van den Bosch, M. Steyaert, and W. Sansen, Static and Dynamic

Performance Limitations for High Speed D/A Converters, Springer,

(2004).

[4] F. Malorberti, Data Converter, Springer (2007).

Chapter 3: Literature Reviews

- 24 -

Chapter 3

LITERATURE REVIEWS: SOURCES OF THE

CURRENT SOURCE MISMATCH AND

THEIR CORRECTION TECHNIQUES

In this chapter, the challenges of designing a high-speed and/or high-accuracy

current-steering DAC which are the main topic on this research are discussed.

To achieve good linearity and dynamic performance, the reduction of effect

from the possible error sources is also covered. Then, the related techniques

for each error source are reviewed. Finally, from comparison of these reviews,

the new techniques are proposed based on the review results.

3.1 Introduction

The current-steering DAC is the most favored architecture for high-speed

high-accuracy implementation due to its abilities; small chip area and high

sampling speed as previously discussed in Chapter 2. Based on three main

blocks; the digital data control block, the analog resources block and the

analog resource support block, this current-steering DAC operates by

converting the digital data provided by the digital data control block into an

analog signal. Then, these data control the switching transistors and current

sources in the analog resource block. While between two blocks, including

biasing circuit and interconnection network exist as the analog resource

support block. Generally, the size of the analog resource block is determined

by three primary factors depending on the technology node. These three

factors are the full-scale (FS) current, the transistor matching and the output

resistance.

However, due to the transistor mismatches, from both analog resources

mentioned above, both static and dynamic of the DAC performances are

deteriorated. The effects of these transistor mismatches become more

significant and important due to the reduction of devices dimensions and

available signal swing. Transistor mismatch behavior due to systematic,

random or gradient errors has been investigated and presented in by a few


- 25 -

scholars in their works [1]-[4].

Before further detailed discussion in the topics transistor matching, the

common error types are briefly explained for better understanding in the next

section.

3.2 Types of errors

Generally, the well-recognized error sources are divided into three categories;

systematic, random and gradient errors. These errors occur by different

condition and affect different parameters.

Systematic error is defined as the error introduced in circuit or layout by

designer. This type of error can be avoided by using proper design and layout

techniques; for examples, usage of the multiples of small transistor or unit

sized devices, cascoded current sources to increase the output impedance in

case of smaller current variations with changes in VDS, avoiding of

asymmetric loading, etc.

Random error is the errors that are generated due to the variation in process

parameters (device length, channel doping, oxide thickness, etc). This type of

error is inevitable in the circuit and cannot be controlled by designer. Thus,

the reduction effect of these errors is very important and must be taken into

account during the design process. Practically, these errors can be reduced by

increasing the device area, ratio of area per perimeter,

Gradient error is the one defined as a systematic error besides edge-effect,

metal coverage and temperature gradient. This type of errors occurs due to a

large silicon area used. It is generally modelled by superposition of both

linear and quadratic components. These errors can be avoided by producing

with under the same environment such as the size of devices, orientation,

location in die and supplies controlled temperature. Layout technique also

can be applied such common-centroid and interdigitation to minimize these

errors.


- 26 -

3.3 Mismatch sources

Mismatch is defined as the difference between the parameters of one group

devices and other group devices produced by the same designs. Even though

all the process is the same, different coordinate pairs on the wafer result in

the different values. In this thesis, the effects of the transistor mismatch in the

current sources [1]-[5], switching behavior [6]-[10] and parasitics [11] are

discussed.

3.3.1 Effects of transistor mismatch

Shyu [1] has investigated the effect of random errors in MOS current sources.

Using the NMOS technology, both local (granular) and global (large-scale)

effects are observed. As a result, the effect of random errors in MOS current

sources due to four difference conditions; edge effects, surface–state-charge

and ion implanted-charge effects, oxide effects and channel mobility effects

are formulated. This work reveals that the accuracy of the DAC performance

is ultimately limited by the random errors with the absence of systematic

errors.

Further investigation in this problem has been done by Lakshikumar [2]. By

considering two variations in integration circuit; global variation is referred

to the total variation in the value of a component over a wafer or a batch and

local variations referred to the variation in a component value reference to an

adjacent component on the same chip. Six factors that cause the mismatch

are observed; threshold voltage, conductance constant, correlation between

mismatches, drain current mismatches, range of applicability, and effect of

temperature. The model for estimating the INL yield was also developed in

this work which later is used as a model in designing DAC based on statistical

design technique. Finally, it found that mismatch especially in MOS

transistors was more complex, and it is not only affected by the devices

dimension but also by the operating point.

In 1989, Pelgrom [3] reported the discussion on matching due to the threshold

voltage and the substrate factor, and the current factor of the MOS transistor

as a function of area, distance and orientation. This investigation work has

been performed by modelling the random mismatches occurred in two


- 27 -

identical areas at certain coordinate. As a result the variance of the threshold

voltage, the current factor, and the substrate factor are obtained, which is

inversely proportional to the transistor area.

In another work reported by Gregor [4], the relation between transistor

matching and its topography is also explored. The findings from this work

show that MOS transistor matching is degraded by topography created prior

to the gate level. This can be explained that the topography interfered with

the flow of resist spun on the wafer, leading to thickness variations in the

resist and subsequent channel length variations in the transistor. The

importance is that matching does not improve by the use of common centroid

symmetric or pseudo-gate layouts, but greatly improves by the use of tri-level

resist process at the gate level. However, due to its complexity and cost, the

modification to single-layer resist condition is suggested.

Besides the above mentioned factors, the influence of die residual stresses

(mechanical stress) on MOS transistor matching also has been studied by

Bastos [5]. As results, the measurement on different cases; dies bonded, hard

solder, and polymide adhesive, are compared with measurements in wafer.

The experimental results found that the mechanical stress generated by

eutectic die bonding to ceramic package is far more significant for transistor

matching than wafer gradients in a modern process technology. The

systematic error on the MOS current factor matching caused by this effects

raised up to ten times compared to the systematic offset which is normally

produced by wafer gradient. While the threshold voltage matching degrades

five times with the distance on eutectic bonded dies.

From the above work, it is clearly shown that transistor mismatch can present

by many resources. Therefore, the proper design with many considerations

must be taken into account.

3.3.2 Effects of switching behavior

As explained in previous chapter, one of the important DAC specifications is

linearity. This can be verified through its transfer function. Means, as linear

as a transfer function can be achieved, a purer an analog signal is produced

(in case of waveform generation for testing) or reconstructed (in case of


- 28 -

Figure 3-1 A 3-bit unary weighted DAC with ideal current source cells and

linear tranfer function (dashed black line).

conversion in transceivers). Figure 3-1 shows that linear transfer function

can be obtained based on “thermometer-coded” switching scheme in case of

the ideal current sources are used.

The word of “thermometer coded” is used since the selection of current

source during switching transition is similar case when a classic thermometer

measures temperature using liquid (Figure 3-2). This switching scheme is

extensively used due to its simplicity and direct implementation corresponds

to the digital input. However, in the context of switching scheme use for DAC,

this thermometer coded switching scheme tends to select the same current

source cells for every clock cycles. As a result, the DAC outputs are strongly

dependent on the digital input values, also called as data-dependent output

[6]-[8].

Figure 3-2 Illustration of temperature measurement using a classic

thermometer.

In the static condition, the effect of current source mismatch (amplitude error)

is not severed. Nonetheless, in dynamic condition (switching transition), the

accumulation of correlated errors of static current source mismatch produces

a non-linear transfer function of DAC output in time-domain due to different

output signal compared to its ideal output (Figure 3-3).

Ideal case

Current cell Code

Outp

ut

Conventional

switching

sequence


- 29 -

At the same time, the non-linearity of DAC outputs is translated into the

undesired output signals in the output spectrum in frequency domain. These

undesired signals often appear as spurs which degrade the SFDR level, as

DAC performance.

Figure 3-3 Non-linear tranfer function (solid red line) caused by

mismatched current source cells.

There is another problem related to the switching behavior. Different with the

data dependent output signal, glitches occur due to the time skew between

the switches and some contribution from the amplitude errors of mismatched

current source cell. This problem is severely affected in conventional binary

DAC due to the large current source switching during mid-code transition [9],

[10], and very sensitive to certain DAC application such as video and

electronic display.


- 30 -

3.3.3 Effects of parasitics

Figure 3-2 Parasitic capacitances at node, Vn.

In Brigati [11], the effect of parasitic capacitances from revelry biased

junctions associated with switches has been reported. Since, a high speed

DAC requires fast and accurate settling but due to limitation on analog CMOS

switches, the maximum speed is unachievable. To obtain a fast settling time,

the switch width need to be designed with large size in case that the minimum

channel length is used, in order to reduce the on-resistance. However,

increasing the gate width also increases the parasitic capacitances, with a

consequent increases the capacitive load to be driven. Another source of

parasitics is exists between the MOS switch and current source cell node

(Figure 3-4) which later becomes one of the sources of the glitch problem.

Lastly, the parasitic capacitances are also generated between interconnection

wiring which contributes to other problem called propagation delay.

3.4 Statistical model design

As previously explained, mismatch occurs due to the difference between the

parameters of one group devices and other group devices produced by the

same designs. Even though all the process is the same, different coordinate

pairs on the wafer result in the different values. Therefore, to attain the good

matching, transistor dimension must be accurately matched within a tolerance

range for certain resolution.


- 31 -

A very accurate DAC is designed by estimating the INL error less than

±1

2𝐿𝑆𝐵. First estimation for INL yield is done in [2] using Equation 3.1

𝐼𝑁𝐿𝑦𝑖𝑒𝑙𝑑 = ∏ 𝑒𝑟𝑓

2𝑁−1

𝑖=2

(𝑄𝑖

√2) (𝟑. 𝟏)

1

𝑄𝑖= 2𝑁+1√

𝑧�̅�(1−𝑧�̅�)

2𝑁−1

𝜎(𝐼)

𝐼

N : the number of bits,

𝑧�̅� : the mean normalized output at code i,

𝜎(𝐼)

𝐼 : the unit current relative standard deviation.

with assumption that there exists no correlation between the outputs of a

current-steering DAC. However, this assumption is considered as incorrect

since the outputs correspond with the digital input. For example, in case of

digital input 01100 and 01101, both outputs are using the same current

sources. As a result, using this assumption, the estimation of the INL yield is

imposed to severe constraint, thus leads to oversize the transistors.

In [12], the INL yield estimation [2] is adjusted to be as in Equation 3.2 and

used for MSB part which is considered as the most critical in a binary

weighted DAC implementation.

𝐼𝑁𝐿𝑦𝑖𝑒𝑙𝑑 = ∏ 𝑒𝑟𝑓

2𝑁−1

𝑖=2𝑁−1−1

(𝑄𝑖

√2) (𝟑. 𝟐)

1

𝑄𝑖= 2𝑁+1√

𝑧�̅�(1−𝑧�̅�)

2𝑁−1

𝜎(𝐼)

𝐼


𝑧�̅� : the mean normalized output at code i,

𝜎(𝐼)


with assumption that the DAC output before and after the MSB transition are

not correlated.


- 32 -

In 1989, Conro [13] has introduced the method to obtain an accurate

estimation called “Monte Carlo” simulation. This simulation works by

calculating and comparing the output of each digital code with the ideal value.

If the difference is larger than half of an LSB, even for only one digital code,

it is considered as not functional and is rejected. This procedure is repeated

with a large number of times (>100) to obtain reliable results. However, a

major drawback of this procedure is consuming simulation time for a high

resolution DAC.

Due to the estimation done in [2] and [12] are situated, thus method in [13]

is more preferred in order to estimate the maximum INL error through INL

yield.

Recently, in work [14], the simple estimation for INL yield is developed. By

using the required accuracy it is given by:

𝜎(𝐼)

𝐼≤

1

2𝐶√2𝑁 (𝟑. 𝟑)

𝐶 = 𝑖𝑛𝑣_𝑛𝑜𝑟𝑚 (0.5 +𝑦𝑖𝑒𝑙𝑑

2)

𝜎(𝐼)



Inv_norm : inverse cumulative normal distribution,

Yield : relative number of DAC with and INL <1

2𝐿𝑆𝐵.

Compared with previous report, it takes only a matter of seconds to determine

the mismatch that can be allowed between the unit current sources of the

DAC for certain yield.

The works reported in [2], [12]-[14] have modelled the random mismatches

by comparing two identical areas for short devices. As a result, the

relationship between the mismatch in threshold voltage, the current factor,

and the substrate factor of the MOS transistor and area, distance and

orientation in circuit implementation is presented.


- 33 -

In further work, the statistical model for a large chip area with the different

number of devices has been presented in [15]. This methodology is based on

mean value and autocorrelation functions for the relevant process parameters

described as spatial stochastic processes. By using this matching model, the

inconsistencies observed for long devices used formula derived in case of

short devices is solved. In addition, this mismatch model also can be applied

for different layout structure by partitioning and placement.

3.5 Correction techniques

In previous section, the current-steering DAC performance has been limited

by three effects; MOS transistor mismatch, non-linear switching and

parasitics. Therefore, in order to reduce these mentioned effects, several

works have been reported. In this section, the selected techniques for MOS

transistor mismatch especially for current source design are reviewed.

3.5.1 Dynamic element matching (DEM) based switching

schemes

There are many correction techniques which can be found in the open

literature. In cases of avoiding the error measurement, the techniques that rely

on good understanding about the error mechanism are reviewed. The most

interactive is random switching schemes and layout techniques. In this

section, these two techniques are discussed.

In previous section, the effect of switching behavior is discussed. By using

conventional switching scheme in case of using mismatched current source

cells, the linearity of transfer function is degraded. However, by re-

sequencing the current source cell selections during switching transition, the

nonlinearity DAC transfer function is possible to be compensated as

illustrated in Figure 3-5.

Based on the reshuffling the selection of current source cells for the same

digital input, the most referred techniques is dynamic element matching

(DEM).


- 34 -

Figure 3-5 Mismatched current sources cell with a compensated non-linear

tranfer function (solid green line) by re-sequencing the current source

selections.

This technique is performed by averaging the mismatch errors over time, hence,

the data-dependent DAC output is removed. In order to enable to represent the

same digital input by different current source cell selection, most of the works

are employed using unary weighted architecture to realize DEM technique.

Many different DEM techniques are reported [9], [16]-[20].

Figure 3-6 Generalized DEM technique.

Figure 3-6 shows that dynamic element matching circuit is generally

composed of a digital decoder. In most of DEM applications, unary weighted

current source cells are employed to provide more selections. Hence, the

thermometer-coded decoder is used to convert the binary code into the

thermometer code. Then, the thermometer code will randomly rearrange by

build-in scrambler logic. The scrambled thermometer code is fed to 1-bit DAC.

Finally, the outputs of the DAC are summed to obtain the final output.


- 35 -

(a) Randomization index, I = 3.

(b) Switching block of the k-th layer.

(c) Data bank.

Figure 3-7 Partial Random DEM (PRDEM) technique [16].


- 36 -

The work reported in [16] has partially employed DEM technique. Compared

to the general DEM circuit, the number of layers is used to replace the

scrambler path which is called randomization index, I. As represented in

Figure 3-7, each switching block is labelled Sk,r where k denotes as the k-th

layer number and r as the r-th position of the switching block in the layer

while DBi is the i-th DAC-banks (Figure 3-7(a)).

Generally, for a b-bit version, of the DAC with randomization index, I, the

number of binary switches required is:

𝑁𝑏 = (𝑏 − 𝐼 + 2)2𝐼 − 𝑏 − 2 (𝟑. 𝟒)

An 8-bit DAC with three random control bits requires 46 binary switches.

Each switching block, has a (k+1)-bit input, two k-bit outputs, k-switches per

layer and block (Figure 3-7(b)). This means, a set of eight switches in layer

8, two sets of seven switches in layer 7 and four sets of 6 switches in layer 6,

total 46 switches. While, each DAC bank, DB has a 6-bit input xi[n] and

analog output yi[n] (Figure 3-7(c)). From this work, the estimated minimum

SFDR increases by approximately 10 dB per increment of randomizations

index, and it is definitely independence of the particular DAC bit-resolution.

However, the trade-off of this technique is between number of randomization

and hardware complexity while the effectiveness increases as the

randomization index is increased.

Figure 3-8 Random Multiple Data-Weighted-Averaging (RMDWA)

technique [17].


- 37 -

Data-weighted-averaging (DWA) is widely used in delta-sigma converter. It

is able to provide such a first-order noise shaping by sequentially selecting

the elements based upon the data. Random multiple data-weighted-averaging

(RMDWA) is proposed in [17] for Nyquist DAC by using multiple pointers.

The element selection is controlled so that it is either randomly jumped to a

different DWA cycle or continuing in the same cycle as illustrated in Figure

3-8. PTR1 and PTR2, two pointers which function to store the number of

starting element for the next conversion. R is random bit generated from

pseudo random number generator that determines which pointer will be used

for the next depending on the direction and input referred to digital input

value. When digital input is 5, R=0, PTR1 is initially pointed to first element

as starting point and {U0, U1 U2, U3, U4} are selected and new value PTR1

becomes 5. For the second input of 7, R= 0, according to PTR1, {U5, U6 U7,

U0, U1, U2, U3} are selected. Then, when input of 4, R=1, PTR2 is still initially

pointed at first element, so, {U0, U1 U2, U3} are selected. And PTR2 becomes

4. It is continuing until the last input signal. This technique provides a great

suppression of harmonic distortion effects.

Figure 3-9 Deterministic dynamic element matching (DDEM) technique

[18].

Just like the illustration in Figure 3-9, the deterministic dynamic element

matching (DDEM) is performed based on cyclic operations. The current

sources are arranged conceptually and sequentially around a circle. The


- 38 -

DDEM technique deterministically chooses the k current sources to be

switched ON. For n-bit DDEM, N = 2n current sources are used. As shown in

Figure 3-9, an example of input data is [5, 5, 5, 5]. Then, the current

selections are, {I1, I2 I3, I4, I5}, {I5, I6 I7, I8, I9}, {I9, I10 I11, I12, I13} and {I13, I14

I15, I16, I1}. The advantage of this techniques is able to produce DAC output

nearly uniformly spaced samples. For ADC INL testing, the ADC need to be

tested from the static viewpoint, where the DAC output is used as the input

to the ADC. Therefore, by using the DDEM technique, the difference

deterministically chosen current source for the same input digital code can be

generated. Additionally, DACs that are substantially less accurate than the

ADCs under test can be used to generate testing stimulus for the ADCs. As a

result, more accurate of INL calculation is attained.

Figure 3-10 Randomized thermometer coding (RTC) technique [19].

2

2

2

2

4

4


- 39 -

Next example of switching algorithm is called randomized thermometer

coding (RTC) [19]. This technique aim is to produce a randomization

property using the conventional thermometer coding, meantime, maintaining

low-element switching activity. The operation of this technique is explained

as in Figure 3-10. To maintain low switching activity, the starting element of

the thermometer code remains unchanged for a specified number of input

samples. RP represents randomized period. As examples, RP which equals 2

and 4 are given. With an eight-element DAC, the RTC technique is

demonstrated. With DAC input codes of 5, 7, 4, 2, 6, 1, 3, and 5, SP is starting

point and is initially set as 0. For RP = 2, with the input of 5, the elements

{U0, U1, U2, U3, U4} are selected. Following by input of 7, the elements {U0,

U1 U2, U3, U4, U5, U6, U7} are selected. For third input code of 4, the SP is

randomly generated in a range between 0 and 7. For input code of 4, SP of 4

is randomly chosen, which means that the elements {U4, U5, U6, U7} are

selected. Next, for input code of 2, the elements {U4, U5} are selected. Means,

every RP period, SP is randomly generated. Thus, the elements are selected

from the starting element of SP as the same manner in case of RP = 4

implementation. This technique is be able to realize in a very low cost, high-

SFDR with a small active area.

Figure 3-11 Random swapping thermometer coding (RSTC) technique [9].


- 40 -

Random swapping thermometer coding in [9] has been presented by random

selection for starting element as depicted in Figure 3-11. Two independent

registers, RegA and RegB are used to store the starting and ending points of

selected elements for each input digital code. While R is 1-bit random value,

it uses to determine the direction of element selection. Using a 3-bit unary

weighted implementation, the RSTC operation is described by referring

Figure 3-11. For initial input code of 5, {U0, U1, U2, U3, U4} are selected with

R=0 indicates the clock-wise direction. RegA and RegB are initially to be 0.

After the selected elements are turned ON, RegB is updated to according to

the sum of RegA value and input code. For second input of 7, all elements are

selected. Since R=1 that indicates the opposite direction, the selection of

elements begins from {U4, U3, U2, U1, U0, U7, U6, U5}. In this case, the RegB

remains unchanged. For third input code of 4 with R = 1, the elements {U5,

U4, U3, U2} are selected in the same direction as in the second input code. It

is continued for all input codes. By using this technique, the glitches

introduced by the generic DEM techniques can be reduced. In addition, the

effect of harmonic distortion is also suppressed.

Figure 3-12 Comparison of possible glitches occurring in each input

between Thermometer coding, DWA and OES [20].

Aiming to attain the balanced performance between conventional DWA and

DEM, one element shifting (OES) is presented in [20]. This technique has

historically been used a long time ago in clock-averaging (CLA) technique,

but suffered from glitch problem. However, due to its simplicity and


- 41 -

effectiveness, it is still attractive and useful in nowadays design. The OES

operation is demonstrated as in Figure 3-12. The operational of OES is

performed by shifting the starting element for each input digital code. By

doing so, the number of element turn ON for every input digital code can be

reduced compared conventional DWA technique except for the RSTC and

thermometer coding. Therefore, the smaller glitch energy can be obtained.

This is because, the glitch energy is proportional to number of switches that

are turned ON once in every clocks. As a result, OES substantially suppresses

both effects of mismatch and glitch.

3.5.2 Layout based switching schemes

Figure 3-13 Symmetrical switching schemes [21].

As mentioned in the section that describes about errors in this chapter,

different error sources require different techniques. In [21], a fast settling

time is necessary to achieve 10-20mA output current. However, due to the

large current, the linearity of the current is also degraded, hence, it causes a

non-linear error. In this work, the voltage drop along the ground line,

produces a tapered error distribution in the output value of each current

source and its effect becomes significant if a conventional sequential

switching scheme is used. Therefore, the new switching scheme is developed

in order to overcome these nonlinear errors. The symmetrical switching

scheme as depicted in Figure 3-13 is described how this symmetrical

switching scheme chooses the current source. By assuming that a matrix

current source is used, all current sources are rearranged in a one-dimensional

way for simplicity. Compared to conventional sequential switching scheme,


- 42 -

symmetrical switching scheme starts from center of the current sources array.

This is because in conventional sequential switching scheme, the deviation

from the average is accumulated as input increases, hence, a significant

integral nonlinear error is produced. While, by using the symmetrical

switching scheme, the deviation from the average of the output current is

immediately cancelled in the next step. As a result, the integral nonlinearity

error is reduced using the new switching scheme. However, this switching

scheme only reduces the integral nonlinearity error caused by graded error.

In this work, two-dimensional decoder known as “row-column” decoding

technique is also introduced.

Figure 3-14 Hierarchical symmetrical switching schemes [22].


- 43 -

A symmetrical switching scheme only compensates graded error of current

sources along a column or row in the matrix, but not for other types of errors,

therefore, new switching scheme called hierarchical symmetrical switching

scheme is introduced in [22]. By approaching two ways of switching

selection, as shown in Figure 3-14, both graded and symmetrical errors are

simultaneously cancelled.

Figure 3-15 Q2 random walk switching schemes [23].

In case of 8- [21] and 10-bit [22] DACs, intrinsic accuracy occupies large

area. One bit increases, the element area increases by factor of four. So the

distance between elements is large, hence the gradient error is introduced.

Then, the compact, matrix configuration is preferred. But still there is large

distance between elements. In the high-speed current-steering DAC designs,

a large chip area is required to achieve better matching requirements in the

current source. However, a large chip area can produce systematic errors such

as gradient errors and temperature gradients. The first intrinsic 14-bit current-

steering DAC with a new switching scheme called as “Q2 random walk” is

developed and presented [23]. This switching scheme achieves reduction

both graded and systematic errors compared to previous approaches [21],

[22].

In this approach, the effect of random errors is also been taken into account.

Q2 is referred to quad quadrant which four (quad) units in every quadrant

altogether compose one current source. Using 256 current sources with

residual error of both higher and lower than average value, are divided into

16x16 current source matrix. Then, this 16x16 current source matrix is again


- 44 -

divided into 16 4x4 regions referred to A-P arrangement as shown in Figure

3-15. In order to implement the approached switching scheme, current

sources with switching number from 0 to 15 are placed according to

arrangement of A in 4x4 region and A-P in 16x16 matrix. Then, current

sources with switching number from 16 to 31 are placed according to

arrangement of 0-15 in 4x4 of L region and A-P in 16x16 matrix. For set

current sources of 32 to 47, are also arranged in the same manner with the

first and second sets of current sources. In case of 8-bit unary weighted in 14-

bit segmented DAC, only 255 current sources are required, thus the last

current source in region P is not used. In order not to waste this current source,

it is configured as a MOS diode and used as a biasing reference for the current

source array. As drawback, even all current sources are equally distributed

around the matrix, but since 16 current sources in every 4x4 region do not

have exactly the same residue, there still errors are remained. Moreover, the

switching scheme is described for a fixed (16x16) size, but not for other

different size and types of error profiles.

For depth analysis for gradient errors is approached in the reported work [6].

Gradient error distribution across a unary matrix can be approximated by a

Taylor series expansion around the center of the unary array. The gradient

error of the element located at (x, y) can be written as:

𝜀𝑙(𝑥, 𝑦) = 𝑎0 + 𝑎11𝑥 + 𝑎11𝑦 + 𝑎21𝑥2 + 𝑎21𝑦2 + 𝑎23𝑥𝑦 … (𝟑. 𝟓)

While, three gradient error distributions are formulated depend on their types

(Figure 3-16(a), Figure 3-16(b), Figure 3-16(c)).

(a) Linear error distribution. (b) Linear error distribution.


- 45 -

(c) Linear error distribution.

(d) Comparison of different switching sequences.

Figure 3-16 INL bounded switching scheme [6].

1) Linear error distribution is expressed as:

𝜀𝑙(𝑥, 𝑦) = 𝑔𝑙 ∗ cos𝜃 ∗ 𝑥 + 𝑔𝑙 ∗ sin𝜃 ∗ 𝑦 (𝟑. 𝟔)

2) Quadratic error distribution is expressed as:

𝜀𝑞(𝑥, 𝑦) = 𝑔𝑞 ∗ (𝑥2 + 𝑦2) − 𝑎0 (𝟑. 𝟕)

3) Normalized joint error distribution is expressed as:

𝜀𝑗(𝑥, 𝑦) = 𝜀𝑙(𝑥, 𝑦) + 𝜀𝑞(𝑥, 𝑦) (𝟑. 𝟖)

Since in the row-column switching schemes [21], [22] are performed either

for row selection or column selection, which means the switching sequences

are optimized in one-dimensional. By considering the switching optimization

of one dimensional and symmetrical, the approached switching scheme is

rearranged the selection of current source as in table comparison in order to

achieve smaller linearity error (Figure 3-16(d)). It is almost half the

maximum deviation of all the current sources in the gradient error array.


- 46 -

3.5.3 Calibration techniques

Compared to two techniques discussed previously, generally, both techniques

are used based on the assumption of error profiles without exact values.

Therefore, most of these kind of correction techniques can be performed as a

background correction mode. In some cases, such as DEM DAC, the

requirement for having exact number is not necessary However, it creates a

risk due to its behavior which is averaging the errors over time. For example,

DEM DACs which have a mismatch dependent gain, which may be a problem

for some low-voltage power-supply application or for application where gain

is important. Moreover, due to its property that allows to perform only in a

background mode, which creates risks for the DAC intrinsic performance,

since there are always correction activities during the normal operation of the

DAC. In addition, the back ground correction methods also consume more

power because their correction circuits cannot be static. However, using these

methods, the slowly changing errors such as temperature changes can be

taken care with their active correction activities.

Several works related to calibration techniques are presented, both back

ground and foreground methods. In [24], a self-calibrated DAC architecture

is developed and reported. By aiming to employ for very-low-voltage

processes, it becomes a challenge for designers using the state-of-art during

that time. There are two techniques that might be used such reducing the

effective gate source voltages and using cascoded current source. However,

these techniques cause the deterioration of the matching and noise immunity

of current source in first case and are not impractical for low-voltage in latter

case even cascoded current source can provide output impedance

enhancement and DAC dynamic linearity improvement. Therefore, a

foreground calibration is approached. This calibration scheme is used to

calibrate the current source mismatches and achieve high linearity, high-

speed with small die and low power.


- 47 -

(a) A 14-bit segmented current-steering DAC.

(b) Simplified version in (a).

Figure 3-17 Self-calibrated DAC technique [24].

This technique is demonstrated in a 14-bit segmented current-steering DAC,

composed of a 6-bit thermometer decoded MSB array, a 4-bit thermometer-

decoded upper LSB (ULSB) and 4-bit binary-weighted lower LSB (LLSB)

(Figure 3-17(a)). Only the MSB array will be calibrated while the remaining

9-bit accuracy is maintained without any calibration. By employing a slow

speed 16-bit calibration analog-to digital converter (CALADC), a small 8-bit

binary-weighted calibration digital-to-analog converter (CALDAC), a 63-

word 8-bit-per-word SRAM, a bias generator and some calibration control

logic, each current source is measured and calibrated. The ADC is used to

measure the differential output and change into digital, thus the calibration in


- 48 -

digital domain can be done. The SRAM is used to store the measured errors.

During the normal conversion, which means after calibration, only SRAM

and CALDAC are used to read out the stored errors and drive them to the

main DAC output. The outputs of CALDAC and the main DAC are summed

to provide overall DAC output current. This means, CALADC and logic

circuit are no longer used, they can be put into a sleep mode during normal

operation. Therefore, the power dissipation of CALDAC during calibration

and transient noise of calibration circuitry can be minimized.

During calibration process, the gain error is also calibrated. Even though, the

gain error does not affect the linearity performance, but it increases the tuning

range requirements for the CALDAC. As a result, this calibration technique

can be used to achieve high linearity, small die area, and low power

dissipation. However, the use of additional calibration ADC and DAC

increases the cost because a higher resolution ADC is required to obtain better

current measurement.

Another work is reported in [25] based on sort-and-group algorithm which

adopted in calibration technique. This technique is used to improve the

matching of the current source after fabrication process. Thus, the technique

called “Switching-Sequence Post Adjustment” calibration or SSPA. As

depicted in Figure 3-20, the calibration performed using the algorithm in

order to optimize the switching sequence. Only additional analog calibration

circuit is a current comparator. This is much simpler compared to the previous

published work.

SSPA method is approached to achieve minimum INL by measuring all

current sources. Then, the best switching sequence is calculated based on

these measured current values. Finally, the RAM-based thermometer coder is

reprogrammed to apply this calculated switching sequence.

The current sources are rearranged and re-sequencing by sorting and

comparing procedures according to the measured current values as in Figure

3-20(a). In this work, 7-7segmented DAC is designed by increasing the

number of binary bits in order to reduce the unary bits which will complicate

the design of thermometer coder. The improvement of the static properties

due to re-sequencing can be observed from the measurement results. In order


- 49 -

(a) Sort and group procedure. (b) SSPA calibration technique.

(c) Simplified version in (b).

Figure 3-18 DAC with SSPA calibration technique [25].

to reduce the DNL error is reduced the 20 extra current sources are added. In

term of INL error, the reduction is observed after re-sequencing. The

advantages of used extra current sources are to replace the defects on some

current sources which may ruin the static performance and to take out the

current sources with big variations. However, the extra current sources

increase silicon chip area in order to maintain mismatch requirements for the

same resolution DAC.

In [26], the complete-folding procedure is adopted in calibration technique to

attain high matching property. A calibration technique called as complete-

folding which achieves the high matching accuracy by selectively regrouping

current source into a fully binary-weighted array based on the current

comparison. This technique also aims to reduce the effects of current source


- 50 -

mismatch after fabrication. Similar in work done in [24], this calibration

technique also uses an analog comparator with addition of digital circuitry to

perform. A 14-bit segmented DAC is simulated in MATLAB. Compared to

the method in [24], the analog comparator is used to rank all the current

sources. Then, the best switching sequence is determined based on these ranks.

(a) Complete-folding procedure.

(b) Calibration technique flow.

Figure 3-19 DAC with complete-folding calibration technique [26].

Complete-folding technique (Figure 3-19(a)) is very similar to calibration

technique in [24]. However, compared to the work in [24], it actually converts

a unary-coded array into a binary-weighted array by recombining the current

sources rather than changing the switching sequence of the current source.

As illustrated in Figure 3-19(a), the current sources are sorted and rearranged

so that the smallest current is grouped with the biggest current and the current

in the middle is left behind. Next, the only grouped current sources are

summed and sorted for the second time and then, rearranged. The smallest


- 51 -

group is grouped with the biggest group to form 4 grouped of unary current

source as MSB bit of 3-bit binary code. Next a group of two current sources

as 2nd bit and a remaining unary as LSB bit. Therefore, the complete-folding

calibration is feasible in the very-low-voltage-process, since it only requires

an accurate current comparator. The complexity of the digital circuitry is

much relaxed because complete-folding calibration used binary-weighted as

the decoding scheme rather than unary-coded (Figure 3-19(b)). As a

drawback, the complete-folding requires more step when a higher bits is used.

The examples in [24], [25], [26] are mostly approached for one-dimensional

calibration technique with amplitude error targeted. Dynamic-mismatch

mapping (DMM) is presented in [27] by aiming to reduce the distortion

caused by both amplitude and timing mismatch errors in once. Compared to

DEM techniques, DMM does not increase the noise floor since the distortion

is reduced, not randomized. In previous work, static-mismatch errors can be

easily measured in the time domain using an ADC [24] or a current

comparator [25], [26] while dynamic-mismatch errors can be measured more

efficiently in the frequency domain. In this calibration technique, by digitally

switching a current source cell as square-wave output at modulation

frequency, fm, its dynamic mismatch error appears as vectors at all harmonic

frequencies. Due to property of a square wave, mismatch errors at

fundamental and second harmonic frequencies are the two most dominant

errors that contain all amplitude and timing error information (Figure 3-

20(a)). Here, timing duty-cycle error is considered as a timing error. To

measure the errors in frequency domain, DMM procedure can be offered as

a candidate. DMM reduces the dynamic-INL by changing the switching

sequence of the thermometer current source cell. Therefore, the dynamic-

mismatch error of each cell can be maximally cancelled by the following

current source cell. In order to simplify the sorting logic, only a simple sorting

logic with an easy hardware implementation is used. The dynamic-mismatch

errors (Efm, E2fm) of two cells have to cancel each other, since Efm and E2fm

are vector signals, so they should be cancelled in I-Q plane. The switching

sequence is determined by comparing the minimized total power of summed


- 52 -

(a) Dynamic-mismatch error in the time, frequency and I-Q domains.

(b) DMM procedures.

(c) DMM DAC architecture.

Figure 3-20 DAC with DMM calibration technique [27].


- 53 -

Efm and E2fm of two current source cells as expressed in Equation 3.8:

|𝐸𝑓𝑚,𝑖 + 𝐸𝑓𝑚,𝑖+1|2

+ |𝐸𝑓𝑚,𝑖 + 𝐸𝑓𝑚,𝑖+1|2

= (𝐼𝑓𝑚,𝑖 + 𝐼𝑓𝑚,𝑖+1)2

+ (𝑄𝑓𝑚,𝑖 + 𝑄𝑓𝑚,𝑖+1)2

+ (𝐼2𝑓𝑚,𝑖 + 𝐼2𝑓𝑚,𝑖+1)2

+ (𝑄2𝑓𝑚,𝑖 + 𝑄2𝑓𝑚,𝑖+1)2

(𝟑. 𝟖)

For simplicity as illustrated in Figure 3-20(b), only Efm is explained. As an

example of five current cells used, the measured dynamic-mismatch errors

are Efm,1, Efm,2, Efm,3, Efm,4 and Efm,5. Then, these errors are sorted in

descending order. Finally, starting with the largest error and the second largest

error, the total power is calculated between these two cells using the

Equation 3.8. Then the second largest error with the third largest error until

all current cells are calculated. During the conversion, the total power of the

summed Efm and E2fm is simultaneously calculated. In order to determine the

switching sequence, the relative dynamic-mismatch errors of the current cells

in the I-Q plane are used.

As shown in Figure 3-20(c), the dynamic-mismatch errors of current source

cells are measured by dynamic-mismatch sensor. The digitized dynamic-

mismatch errors are then sorted. The information of optimized switching

sequence is mapped in the mapping engine based on registers which later is

used during normal conversion. A 14-bit 200MS/s current-steering DAC is

used to validate the effectiveness of DMM calibration technique. The

advantages of this technique are improvement of the DAC linearity in a wide

frequency range and low noise floor of the DAC output; in addition, the

relaxation of circuit requirements for measuring dynamic-mismatch errors,

such as offset and reference accuracy.

In order to simplify the calibration circuit, while improving their achievement,

the latest calibration technique employed for a high-speed high-resolution is

reported in [28]. A 16-bit current-steering DAC with 3.2 GS/s is

demonstrated using a 3-dimensional sort-and-combine (3D-SC) calibration

technique.


- 54 -

Compared to work in [27], 3D-SC calibration technique targeted for three

component errors; amplitude, duty-cycle and delay errors to be compensated

together. As shown in Figure 3-21(a), the mismatched current source cells

are measured using mismatch sensor as in work [27]. In case that 3-bit

thermometer-coded and one-dimensional optimization are considered, one-

dimensional matching errors in current-source amplitude are represented as

differences in height of the units, while three-dimensional matching errors

are shown as three dimensional error vectors. By measuring all current source

cells, I1 to I7, the average current source amplitude, I AVG is determined. The

first step is to select the closest current source cell with the IAVG, as a b0. Then,

all remaining current source amplitudes are sorted and combined such that

their combined level becomes as close as possible to 2xIAVG and assigned as

T1 to T3. As a result the thermometer-coded data segmentation level

decreases with 1-bit. This combining of units can be extended in second

round, based on their remaining errors such that one arrives at sets of 4 units.

Then, the thermometer data segmentation level decreases with an extra 1-bit

and the programmable decoder translates into B0, T1 and T2. By

implementing 63-bit thermometer coded MSBs which are then programmed

into 1 combinations of four, a combination of two and a single unit translates

the 16-bit binary input data into 15-bit thermometer-coded MSBs and 12-bit

binary coded LSBs, results 2-bit decrement in thermometer data

segmentation level.

(a) A 3-dimensional sort-and-combine procedure.


- 55 -

(b) DAC block diagram.

Figure 3-21 DAC block diagram with 3D-SC calibration technique [28].

Figure 3-21(b) shows the block diagram and MSB unit cell circuit. It is

composed of a programmable decoder, current mode logic (CML) block, 63

MSB and 10 LSB array, an on-chip error measurement, a staked of a cascoded

current source, a switch pair, and two sets of switch cascodeds. The two sets

of cascodes allow the DAC to switch between normal operation mode and

error measurement mode.

The advantages of this calibration technique are to provide a 3-dimensional

errors compensation with 10 dB lower third order intermodulation (IM3)

compared to state-of-art CMOS DAC with similar sampling rate and low

power.

3.5.4 Return-to-Zero (RZ) switching technique

As alternative, to void the correlated current source mismatch be accumulated,

and at the same time to reduce the effect of data dependent which also

contributes as one of the undesired spurs in the output spectrum return-zero

based switching scheme has been developed. In [29], a 12-bit high speed

DAC with RZ has been demonstrated.


- 56 -

Figure 3-22 Comparison between Non-Return-to-Zero (NRZ) and Return-to-

Zero (RZ) [29].

Return-to-zero technique operates by setting the switch transistor of DAC

output to be zero during the switching transition or mode ‘zero’. Once the

data is settled, the DAC output is switched back to normal or mode ‘track’.

The illustration of comparison between the output using non-return-to-zero

(NRZ) and return-to-zero (RZ) techniques as shown in Figure 3-24. This RZ

technique is basically functioned to protect the DAC output signal from the

data dependent effect. By setting the switch to zero at the first part of output

duty cycle. Thus, it not only changes the data dependent into clock-dependent,

but also avoids the glitch problem. Generally, this technique is effective

against both random and systematic, data-switching errors. On the other hand,

since this technique requires twice higher than the DAC sampling rate, it is

difficult to ensure the DAC output to be properly settled at high speed.

Moreover, the reset circuit itself represents extrinsic DAC redundancy which

is a risk of deteriorating the intrinsic DAC performance. RZ technique is

essentially an analog correction. Thus, as other analog circuits, the same

problems such as clock jitter effects, non-linearity, accuracy, and layout

parasitic effects need to be considered. As conclusion, the RZ techniques are

suitable for implementation of DAC that are sensitive to data-dependent

NR

Z

RZ

RZ

NR

Z


- 57 -

switching error such as binary DACs. Nonetheless, this technique is not

suitable for extremely fast DAC due to the RZ output cannot properly settle.

3.5.5 Differential Quad Switching (DQS) technique

As similar to RZ technique, the differential-quad switching (DQS) technique

also operates by replacing the data-dependent which causes the disturbance

into clock-dependent [30]. By implementing four switch transistors instead

two for conventional differential current switching.

As explained previously, differential quad switching, provides the same good

points of both RZ switching and ordinary differential switching which is

suitable for high sampling rate and changes the data-dependent into clock-

dependent. However, implementation of differential quad switching increases

its design complexity, dynamic power consumption due to the used the fact

that one pair of the four switches each cycle.

3.6 Summary

The static and dynamic performances of the DAC are determined by the

accuracy of its analog components such as current sources and switches.

Due to the transistor mismatch, both static and dynamic performances

are deteriorated. Therefore, the development of correction error

techniques either before or after fabrication process are becoming

important in order to attain better DAC output signal, hence this

development techniques become more attractive.

In order to develop a good correction error technique, the important thing

is to identify the type of errors and their behaviors.

Table 3-1 Summary of error types.

Error Sources Counterplans

Systematic Circuits, layouts

by designers

Proper circuit and layout designs

such as cascoded current sources,

symmetrical loading inter-

connection

Random Variation in

process parameters

Increase device area, correction

techniques


- 58 -

Gradient Large silicon area Layout technique, such as common-

centroid and inter-digitation.

Component mismatch becomes one of the most problems in designing

DAC. Their effects can deteriorate both the static and dynamic DAC

performances.

Table 3-2 Different of mismatch sources.

Source Mismatch types Effects

Transistors Inaccuracy Amplitude error

Switches Asynchronous switches Timing error

Parasitics Asymmetric interconnection Timing error

Statistical model based DAC design is used to estimate the INL

performance. By using the estimation, the desired DAC out

characteristics can be expected, e.g. linearity, monotonicity, etc.

Table 3-3 Comparison of different statistical models.

Cited

work Model

Performance

Advantage Drawback

[2] 𝐼𝑁𝐿𝑦𝑖𝑒𝑙𝑑 = ∏ 𝑒𝑟𝑓

2𝑁−1

𝑖=2

(𝑄𝑖

√2)

Nearly fault-

free

Situated

condition

Oversizing

transistor due

to high

constraint

[12]

𝐼𝑁𝐿𝑦𝑖𝑒𝑙𝑑

= ∏ 𝑒𝑟𝑓

2𝑁−1

𝑖=2𝑁−1−1

(𝑄𝑖

√2)

Situated

condition

[13] Monte Carlo Accurate

estimation

Consume

simulation

time

[14] 𝜎(𝐼)

𝐼≤

1

2𝐶√2𝑁

Less

simulation

time

Note : Situated condition referred to the assumption that DAC output before

and after the MSB transition are not correlated.


- 59 -

Error correction techniques become attractive, but not all techniques can

be realized in circuit implementation. Thus, depending on the error types,

the selection of error correction technique is important in order to attain

a maximal effectiveness.

Table 3-4 Comparison of different statistical models.

Error correction

technique Advantages Drawbacks

DEM

[9], [16]-[20]

W/o error measurement

Robust to temperature

changes due to

Complex circuit

Increases noise floor

Increased power

consumption

Increased noise

Slow conversion speed

Layout

[6], [21]-[23] W/o error measurement

Sensitive to temperature

changes

Calibration

[24]-[28]

W/ error measurement

Possible to work in

both foreground and

background mode

Less power

consumption

Risk of performance

deterioration due to

measurement circuit

Rely on the accuracy of

the measurement circuit


changes due to frequently

calibrate

RZ

[29] W/o error measurement

Not reduce the error but

hide the glitch effect

Reset circuit risks the

performance degradation

DQS

[30] W/o error measurement

Not applicable for high-

speed

Sensitive to transistor

mismatches

Calibration

[24]-[28]

W/ error measurement

Possible to work in

both foreground and

background mode

Less power

consumption

Risk of performance

deterioration due to

measurement circuit

Rely on the accuracy of

the measurement circuit


changes due to frequent

calibration

Since the effectiveness of the correction techniques for current source

mismatch effect reduction is notified, more idea related to these techniques

should be developed. However, not all these ideas can be simply realized due


- 60 -

to the limitation in practical implementation.

In our research works, we propose to use calibration technique. With

requirement of error measurement, the exact error can be obtained and

therefore, accurate correction can be done. In addition, by implementing

foreground calibration mode, the risks of deterioration DAC performance

during normal conversion process are reduced.

References

[1] B. Shyu, G. C. Temes, and F. Krummenacher, “Random errors effects in

matched MOS capacitors and current sources,” IEEE J. Solid-State

Circuits, vol. SC-19, pp. 948-955, 1984.

[2] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland,

“Characterization and modeling of mismatch in MOS transistors for

precision analog design:’ IEEE J. Solid-State Circuits, vol. SC-21, pp.

1057–1066, 1986.

[3] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P.G. Welbers, “ Matching

properties of MOS transistor”, IEEE J. Solid-State Circuits, vol. 24, no.

5, pp. 1433-1439, October 1989.

[4] R. W. Gregor, “On the relationship between topology and transistor

matching in an analog CMOS technology”, IEEE Trans. on Electron

Devices, vol. 39, no. 2, pp.275-282, February 1992.

[5] J. Bastos, M. J. Steyaert, and W. Sansen, “ Influence of die attachment

on MOS transistor matching”, IEEE Trans. on Semiconductor

Manufacturing, vol. 10, no. 2, pp. 209-217, May 1997.

[6] Y. Cong and R. L. Geiger, “Switching sequence optimization for gradient

error compensation in thermometer-decoded DAC arrays,” IEEE Trans.

Circuits Syst. I, Reg. Papers, vol. 47, no. 7, pp. 585–595, Jul. 2000.

[7] Z. Yu, D. Chen, and R. Geiger, "1-D and 2-D switching strategies

achieving near optimal INL for thermometer-coded current steering

DACs," in Proc. of IEEE Int. Symposium on Circuts and Syst.

(ISCAS2003), pp. 909-912. May 2003

[8] M. Clara, A. Wiesbauer, and W. Klatzer, “Nonlinear distortion in current-

steering D/A-converters due to asymmetrical switching errors,” in Proc.

of IEEE Int. Symposium on Circuits and Syst.( ISCAS’04), vol. 1, 2004.

pp. I-285-288

[9] M-H. Shun, J-H. Tsai, and P-C, Huang,” “Random swapping dynamic

element matching technique for glitch energy minimization in current-


- 61 -

steering DAC”, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no.5,

pp. 369–373, May. 2010

[10] W.-T. Lin and T.-H. Kuo, “A compact dynamic-performance-improved

current-steering DAC with random rotation-based binary-weighted

selection,” IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 444–453, Feb.

2012.

[11] S. Brigati, G. Caiulo, F. Maloberti, and G. Torelli, “Active compensation

of parasitic capacitances for very high frequency CMOS DACs” in Proc.

of IEEE Int. Symposium on Circuits and Syst.,( ISCAS’93), vol. 2, 2004.

pp. 1208-1211

[12] K. Lakshmikumar, R. A. Hadaway, and M. A. Copeland., "Reply to: A

Comment on Characterization and Modeling of Mismatch in MOS

Transistors for Precision Analog Design", IEEE Journal of Solid-State

Circuits, vol. 23, pp. 296, February 1988

[13] C. S. G. Conroy, W. A. Lane, M. A. Moran, "Comments, with reply, on

`Characterization and modeling of mismatch in MOS transistors for

precision analog design'," IEEE J. Solid-State Circuits, vol. 23, pp. 294-

296, 1988.

[14] A. v. d. Bosch, M. Steyaert, and W. Sansen, Static and Dynamic

performance limitations for high speed D/A converters (Springer, 2004)

[15] M. Conti, P. Crippa, S. Orcioni, and C. Turchetti,”Layout-based

modelling for the prediction of the matching properties of MOS

transistors”, IEEE Trans. on Circuits and Syst.-I: Fundamental Theory

and Application, vol.49, no. 5, May 2002.

[16] H. T. Jensen, I. Galton, “An analysis of partial randomization dynamic

element matching technique”, IEEE Trans. on Circuits and Syst.–II:

Analog and digital processing. vol. 45, no. 12, pp.1538-1549, December

1998.

[17] D.-H. Lee, Y.-H., and T. –H. Kuo, ”Nyquist-Rate Current-Steering Digital-

to-Analog Converters with Random Multiple Data-Weighted Averaging

Technique and QN Rotated Walk Switching Scheme”, IEEE Trans. on

Circuits and Syst.—II: Express Briefs, vol. 53, no. 11, pp. 1264-1268,

November 2006

[18] H. Jiang, B. Olleta, D. Chen, R. L. Geiger, ”Testing high-resolution

ADCs with low-resolution/accuracy deterministic dynamic element

matched DACs”, IEEE Trans. on Instrumentation and Measurement, vol.

56, no. 5, pp. 1753-1761, October 2007.


- 62 -

[19] D. –H. Lee, T. –H. Kuo, “Low cost 14-bit current-steering DAC with a

randomized thermometer-coding method”, IEEE Trans. on Circuits and

Syst.–II: Express Brief, vol. 56, no. 2, pp.137-141 February 2009.

[20] H. P. Ninh, M. Miyahara, and A. Matsuzawa, “A83-dB SFDR 10-MHz

bandwidth continuo-time delta-sigma modulator employing a one-

element-shifting dynamic element matching”, IEEE Int. Symposium on

Radio-Frequency Integ. Tech. (RFIT), Beijing, pp.109-112, Nov. 2011

[21] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba,

"An 80-MHz 8-bit CMOS D/A Converter," IEEE J. Solid-State Circuits,

Vol. sc-21, No. 6, Dec. 1986.

[22] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, "A 10-b

70-MS/s CMOS D/A Converter," IEEE J. Solid-State Circuits, Vol. 26,

No. 4, Apr. 1991.

[23] G. Van der Plas, J. Vandenbussche, M. Steyaert, W. Sansen, and

G.Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS

DAC,”IEEE J. Solid-State Circuits, vol. 34, pp. 1708–1718, Dec. 1999.

[24] Y. Cong and R. L. Geiger, "A 1.5-V 14 bit 100-MS/s self-calibrated

DAC," IEEE J. Solid-State Circuits, , vol. 38, pp. 2051-2060, 2003.

[25] T. Chen and G. Gielen, “A 14-bit 200-MHz current-steering DAC with

switching-sequence post-adjustment calibration,” IEEE J.Solid-state

Circuits, vol. 42, No. 11, pp. 2386-2394, Nov. 2007

[26] T. Zeng, D. Chen, “New Calibration Technique for Current-Steering

DACs”, Proc. IEEE ISCAS, pp. 573-576, May 2010.

[27] Y. Tang, J. Briaire, K. Doris, et al., “A 14 bit 200 MS/s DAC with SFDR

>78dBc, IM3 <-83dBc and NSD <-163dBm/Hz Across the Whole

Nyquist Band Enabled by Dynamic Mismatch Mapping”, IEEE J. Solid-

State Circuits, vol. 46,no. 6, pp. 1371-1381, June 2011.

[28] H. Van de Vel, J. Briaire, C. Bastiaansen, P. van Beek, G. Geelen, H.

Gunnink, Y. Jin, M. Kaba, K. Luo, E. Paulus, B. Pham, W. Relyveld, and

P. Zijlstra, “A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc

IM3 up to 600MHz”, in IEEE ISSCC Dig. Tech. Papers,, pp. 205-206,

Feb. 2014.

[29] Wei-Hsin Tseng, Jieh-Tsorng Wu, and Yung-Cheng Chu, “A CMOS 8-

Bit 1.6 GS/s DAC with Digital Random Return-to-Zero,” IEEE Tran.

Circuits Syst. II, Exp. Briefs, vol. 58, no. 1, Jan. 2011.

[30] S. Park, G. Kim, S. –C. Park, and W. Kim, “A digital-to-analog

converter based on differential-quad switching,” IEEE J. Solid-State


- 63 -

Circuits, vol. 37, no. 10, pp. 1335-1338, Oct. 2002 .

Chapter 4

PROPOSED ALGORITHMS AND

CALIBRATION TECHNIQUES

4.1 Introduction

In this chapter, two algorithms; a combination of switching-sequence post-

adjustment (SSPA) and one-element-shifting (OES) called SSPAOES, and a

3-stage current sorting (3S-CS) are proposed. These two algorithms are

described and adopted into two calibration techniques. Their details are further

explained in the next sections. Then, their simulation results are presented and

discussed. Finally, the conclusions are provided in the last section.

4.2 Proposed calibration technique I: SFDR improvement

algorithm for current-steering DACs

Wireless communication systems require high-speed, high-resolution

digital-to-analog converters (DACs) with high spurious free dynamic range

(SFDR) [1],[2], and current-steering DACs, with a segmented architecture

for higher-order bits and a binary-weighted architecture for lower-order

bits, are frequently employed. Segmented architecture is chosen due to its

abilities to provide a good balance between chip area [3], [4], power, speed,

and glitch energy [5]. To obtain high SFDR, we have to take into account

the static mismatches among current sources in the segmented architecture

for higher-order bits, and also the glitch energy due to switching timing

mismatch.

In this research work, we investigate digital-domain algorithms for current

source selection in higher order bits of segmented part to achieve high

SFDR; the algorithms reduce the effects of current source mismatches and

reduce the number of current switches toggled to reduce glitch energy.

From the previous literature reviews, several research works related to error

correction techniques have been studied. Two techniques; switching-

sequence post-adjustment (SSPA) [6] and one-element-shifting (OES) [7]

Chapter 4: Proposed Algorithms and

Calibration Techniques

- 64 -

have been chosen to be implemented in this work.

The static errors from mismatched current sources become a problem in

DAC output. Figure 4-1 shows a transfer function of DAC obtained by the

ideal (dashed blue line) and the mismatched current sources (solid red line).

This non-linear transfer function is also caused by the use of switching

scheme especially thermometer-coded algorithm based switching scheme.

Figure 4-1 Transfer function. (a) Ideal. (b) Mismatch.

Figure 4-2 shows DAC output spectrum of current-steering DAC with and

without mismatch in frequency-domain.

Figure 4-2 Output spectrum. (a) Ideal. (b) Mismatch.

Due to the static errors caused by current source mismatches, large

frequency-domain spurious components can be observed. In addition, the

behavior of thermometer-coded based switching scheme in producing a



- 65 -

pattern of DAC output is also recognized as contributor to this problem. This

output pattern is mostly known as data-dependent output. The effect of data-

dependent output appears when the same current sources are always selected

to be switched according to the same digital input code. This means that the

same amount of accumulated errors are presented for every corresponding

analog output. Moreover, the effect of data-dependent becomes serious in

high speed application due to the same digital input codes are generated

which is represented as undesired spurious components in frequency-

domain. Therefore, the combination of these two spurious components

which are sourced from the current source mismatches and the data-

dependent output signal have caused not only the DAC transfer function non-

linearity, but also the dynamic performance degradation. Hence, the

correction of these two effects; current source mismatches and data-

dependent are becoming important.

Conventionally, a thermometer-coded algorithm based switching scheme is

used to switch ON or OFF the current sources according to the digital input

code. This thermometer-coded (TC) algorithm is commonly used for element

selection in the segmented current-steering DAC and more attractive due to

its simple implementation. For the digital input, Din, the elements U1, U2,

…, UDin are selected (SW1, SW2, …, SWDin are on, and the others are off).

Figure4-3 shows an example of 3-bit conventional thermometer coded DAC

with setting digital inputs {5, 7, 4, 6, 2, … }. U1 to U7 represent available

initial point and end point current sources.

Figure 4-3 Current source cell selection with the conventional thermometer-

coded algorithm.

Thermometer-coded procedures:

(i) When the digital input is 5, current source switches of U1 to U5 turn ON

and U6, U7 are off.

U1 U2 U3 U4 U5 U6 U7

5

7

4

6

2

0

3

1

Dig

ita

l in

pu

t

End pointStart point



- 66 -

(ii) When the digital input changes from 5 to 7, U1 … U5 remain ON, and

U6 and U7 turn ON.

(iii) Now suppose that the digital input decreases from 7 to 4. Then U1 to U4

remain ON while U5 to U7 are turned OFF.

This process is continued for all digital input codes and analog values are

obtained.

By doing switching selection in such a way, thermometer-coded algorithm

based switching scheme can provide the lowest number of switching

activities (switches are turned ON or OFF) during transition, means that a

lower glitch energy is produced. Then, the relationship between number of

switching activities and glitch is explained. Glitch is expected to be a

problem when there are too many switches which are turned ON or OFF

between two different codes transition. Due to non-idealities among the

switches, it can produce a switching delay. As a result, the undesired analog

output signal is obtained. This glitch energy is proportional to the number of

switches that are turned ON or OFF at each transition. Figure 4-4 shows the

relationship between glitch energy and number of switches, n.

Figure 4-4 Relation between glitch energy and number of switches.

However, due to data-dependent effect, the SFDR level produced by

thermometer-coded switching scheme is degraded.

Back to our main target for reducing the effect of the static errors caused by

mismatched current sourced, switching-sequence post-adjustment (SSPA) is

considered due to its ability to reduce the effect of these errors. The reasons

of this consideration are explained as the following.



- 67 -

In case of a low-resolution DAC design, the random static errors of

current sources can be minimized by the proper transistor matching

design. For better transistor matching, the transistors need to be made big

and laid out close to each other. However, as the number of bits increases

the number of current sources also increases. The big size transistor

consumes more silicon area. Moreover, a large area produces systematic

errors.

DEM techniques hide the errors effect rather than reduce them during conversion

process. As a result, the noise floor is increased.

Layout based switching sequence can be used effectively if the errors

exist as they were expected.

4.2.1 Switching-sequence post-adjustment (SSPA)

As described in earlier chapter, switching-sequence post-adjustment (SSPA)

calibration method allows the switching sequence of current sources changes

after the fabrication process. It uses a simple calibration method which

requires only a current comparator to find out the best arrangement of current

sources. By implementing this calibration method, a DAC with optimal INL

can be configured. This is also contributed to improve SFDR. In [6], spare

(redundant) current sources are provided to allow fabrication defects to be

compensated for. But in this work, we consider a technique where no any

spare current source is required. Based on the current sorting and rearranging

its sequence, the procedure of SSPA is demonstrated as in Figure 4-5.

SSPA procedures:

(i) The current sources are compared and sorted from the lowest to highest

order.

(ii) Then, the sorted current sources are rearranged by alternating the

smallest and largest, second smallest and second largest, and so on as

shown in Figure 4-5.

(iii) Next, neighboring pairs of currents are summed.

(iv) Then summed currents are again compared, sorted and rearranged as

shown in Figure 4-5.

(v) Lastly, the final sequence is obtained.



- 68 -

Figure 4-5 6 steps of SSPA calibration.

Original work in [6], thermometer-coded algorithm is used during

conversion process. Thus, even the effect of static mismatches caused by

current sources is reduced, but then the effect of data-dependent still remains

because of the repetition same current source selection for every same digital

input code due to thermometer-coded switching scheme. In order to reduce

the effect of data-dependent output signal, the set of current source selection

for the same digital input code need to be changed.

But, without a proper technique, changes can be produced another problem

because too many current sources are switched ON and OFF for every

interchanging code which causes glitch problem.

.

So, to maintain as low as possible number of switches that are turned ON

and OFF in each clock cycle, the effect of glitch can be minimized. In next

section, the suitable candidate is to select to cope with our target; high

SFDR with low glitch energy.

4.2.2 One-Element-Shifting (OES) algorithm

As point out in previous section, the glitch energy can be reduced by

optimizing the switching activity. In [7], One-Element-Shifting (OES) is

proposed, to spread the effect of current mismatch errors in the frequency

domain and reduce glitch energy by reducing switching activity. Therefore,

this technique is suitable for our work. Therefore, the steps of this algorithm



- 69 -

are studied. Figure 4-6 explains the operation of this algorithm.

OES procedures:

(i) When the digital input is 5, U1 to U5 switches are turned ON while U6

and U7 are OFF.

(ii) When the digital input changes to 7, U2 to U7 and U1 are selected due

to change of starting point from U1 to U2, shifted by 1 for every clock.

(iii) When digital input is 4, U3 to U6 are selected which is as the same as

in (ii) where the starting points changes from U2 to U3.

(iv) When the digital input is 6, U4 to U7 and U1 to U2 are selected.

And it is continued until all digital input codes are inserted.

Figure 4-6 Current source cell selection for OES.

In term of switching activity, OES algorithm has slightly more than that for

the thermometer-coded (TC) algorithm, but it is minimal; the increase in

switching activities becomes less significant as DAC resolution in bits

increases. The reason for that we are compared with TC algorithm that it

produces the lowest number of switching activities. Hence the glitch is also

small.

U1 U2 U3 U4 U5 U6 U7

5

7

4

6

2

0

3

1

Dig

ital in

pu

t

End pointStart point



- 70 -

Table 4-1 Comparison of switching activities for different algorithms.

Number

of bit

Thermometer

coded

One-

element-

shifting

(OES)

%

Data-

weighted-

averaging

(DWA)

%

3 16,439 18,249 11% 20,061 22%

6 146,420 149,610 2% 183,296 25%

8 592,422 596,056 1% 742,254 25%

10 2,376,311 2,380,181 0.2% 2,977,941 25%

Comparison data are obtained with condition: fin = 1433MHz, fs=4.096MHz, Data points = 4096,

current sources=1023, std =0.04, Mean,=-0.01, Mismatch, 0.20;

Figure 4-7 Graph of plotted data in Table 4-1.

As referred to Table 4-1 and Figure 4-6, which shows the DWA algorithm, the

number of switching activities is increased by 25% as a number of bits is

increased compared to TC algorithm. On the other hand, the number of switching

activities is slightly increased but the percentage of the different is decreased by

the increment number of bits by used OES algorithm in case that it is compared

with TC algorithm. Therefore, OES theoretically produces the small glitch, and

also changes the output characteristic from a data-dependent output to a clock-

dependent output signal. This is due to the changes of the starting point of

selected current source cell for each data input code is shifted by one element. It

means that the effect of output pattern with TC algorithm is reduced.



- 71 -

4.2.3 Combination of SSPA and OES (Investigated algorithm)

By considering two methods; SSPA and OES advantages, we decided to

make further investigation to these two methods. Thus, we investigated the

combination of SSPA and OES algorithms which are called as SSPAOES

algorithm, in order to further suppress the effect of static errors due to current

mismatches and improve SFDR performance (Figure 4-8). Basically, the

operation of this method is to implement SSPA method from step (i) – (v), as

described in Section 4.2.1, with the difference that we change the method to

use the OES switching method as shown in Figure 4-5 instead of the

thermometer-coded switching method.

Figure 4-8 Investigated algorithm.

Therefore, changing from the TC switching scheme to the OES switching

scheme reduces the effect of distortions due to the data-dependent output

signal. By implementing the OES switching scheme, the output signal is

indirectly changed from data-dependent to clock-dependent. Meaning that,

for a given digital input value, the output is obtained using different

combinations of current sources. This does not happen in the TC switching

scheme, where a given digital input value corresponds to a given current

source cell configuration.

In addition, the OES switching scheme requires fewer the switches to turn on

or off in each clock period than other switching schemes. This is because

other random switching scheme especially dynamic element matching

(DEM) such as data weighted averaging (DWA) changes its starting point of

I6

I5 I7

I3

I4

I2 I1

⑤ Rearrange

I6

I5 I7

I3

I4

I2 I1

④ Sort

I6 I5 I7I3 I4I2 I1

⑥ Final sequence

+ proposed algorithm

I7I6 I5 I4I3 I2 I1

① Sort

I7 I6 I5I4I3 I2 I1

② Rearrange

I6

I5I7

I3

I4

I2 I1

③ Combine



- 72 -

the current source cell selection for every clock period at the one after the

last selected current source cell in the previous digital input. Means, if the

number of the current sources is large, there is a possibility that, during the

next clock period, all the selected current source cells need to be turned OFF

while new selection current source cells will turn ON. This leads to glitch

problems.

Thus, reducing the number of switches that turn on and off in each clock

period can contribute to glitch effect reduction. Moreover, the changing

starting point of the selected current source cells in each clock period

indirectly averages the accumulated current source mismatches over time.

Therefore, the distortions caused by these mismatches will convert into white

noise and be suppressed into the noise floor.

4.2.4 Calibration technique

Figure 4-9 Proposed calibration technique.

To realize our proposed algorithm, we proposed to adopt this algorithm into

a calibration technique as shown in Figure 4-9. Figure 4-10 is illustration in

memory for an example of 3-b MSB array. The steps of our proposed

calibration technique are explained as follows:

① First, all current source cells are measured in order to obtain their exact

values. In order to measure each current source cell, a test code is loaded

to control the switch, SWi, to disconnect i-th current source cell in MSB



- 73 -

array from their normal output line to the input of measurement circuit.

This measurement is done by using an analog comparator due to its

simplicity.

② All measured current values are temporarily stored in random access

memory (RAM) using registers. The optimized memory size is also

taken into account to maintain the overall chip area (Figure 4.9(a)).

③ Using the calibration controller, the stored registers that contain position

of each current source cell and its value, then these registers will be

calibrated using the proposed digital algorithm (SSPA) to attain the

switching sequence optimization (Figure 4.9(b)).

④ After that, this new switching sequence will be stored in the look-up

table (LUT) based decoder that is used during normal conversion

(Figure 4.9(c)).

During the normal conversion, the input MSB code is decoded into

thermometer code, generates an address of the switch configuration

according to the digital input value (Figure 4.9(d)). Then, this switch

configuration trough the OES block to shift the position of starting element

from the original switch configuration in LUT decoder (Figure 4.9(e)).

(a) Temporary memory.

(b) LUT decoder.



- 74 -

(c) OES block.

Figure 4-10 Illustration of the process steps in the temporary memory, LUT

decoder and OES block.

We propose the use of measurement circuit based on a time-domain analog

method rather than a voltage domain analog circuit. Therefore, robust and

higher precision measurement can be achieved. The conversion speed

depends on the hardware specifications such as that of random access

memory (RAM) to store the measured current source values and optimize

switching selection, and calibration controller to perform the SSPA procedure.

However, there is still remained a trade-off between precision of the

measurement circuit and overall DAC performance.

4.2.5 Simulation results and discussion

In this work, the coherent sampling method is used. It is normally applied for

evaluating the dynamic performance of high-speed ADCs. This is because,

by employing this method, it can increases the spectral resolution of an FFT

and eliminates the need for window sampling when certain conditions are

met. Otherwise, the window sampling can be used as an alternative.

Coherent sampling of a periodic waveform occurs when an integer number

of cycles exist in the sample window. In other words, coherent sampling

occurs when the relationship of Equation 4.1 is met.

𝑓𝑖𝑛

𝑓𝑠=

𝑀

𝑁 (4.1)



- 75 -

Where:

𝑓𝑖𝑛 – input frequency.

𝑓𝑠 – sampling frequency.

M – the integer number of cycles in the data.

N – the integer with factor of 2, total number of samples in the data.

The coherent relationship works for any arbitrary M and N. Normally, N is

integer with a power of 2. This is because the inherent periodicity of Fourier

Fast Transform (FFT) requires the number of samples to be power of 2.

Compared to the Discrete Fourier Transform (DFT), FFT provides less

computation time. In order to eliminate common factor of N, M should be

selected as an odd or a prime integer. This is important to avoid the different

harmonics of 𝑓𝑖𝑛 having the same bin in the FFT after aliasing.

We have implemented the developed algorithms to demonstrate a 10-bit

segmented current-steering DACs at 143.3 MHz input frequency with

409.6MHz sampling frequency using MATLAB simulation. Fig. 8 shows

one of the simulation results for the conditions summarized in Table 4-1.

Table 4-2 Simulation conditions.

Parameter Value

Input frequency, fin 143.3 MHz

Sampling frequency, fs 409.6 MHz

FFT points 4096

Standard deviation 0.06 A

Tolerance, ± 0.2 A

First, the error distribution is generated according to the desired range.

Figure 4-11(a) depicts an example of time-domain for amplitude errors

Figure 4-11(b)

is the figure of their histogram.



- 76 -

;

(a) Amplitude distribution.

(b) Histogram of error amplitude.

Figure 4-11 Error characteristics.

By adding these amplitude errors into the ideal unary-weighted current

source cells, the simulation results show that as the number of bits (DAC

resolution) increases, the SFDR average performance improves

proportionally. Figure 4-12(a), Figure 4-12(b), Figure 4-12(c) and Figure

4-12(d) show a comparison of SFDR performance of a 10-bit current-

steering DAC with four different algorithms, where only current source

mismatches are considered and glitch effects are NOT. For comparison, we

calculate the number of switches that turn ON and OFF for every clock

period where a glitch might occur.

Our MATLAB simulations show that the investigated algorithms achieve

better SFDR than the conventional thermometer method (when static current

source mismatches are considered). The observation shows that the proposed

algorithm obtains 82.4 dBc at condition of frequency input 143.3MHz with

6% standard deviation error and 40% mismatch (0.8 to 1.2A); 24 dB better

SFDR performance compared with the thermometer coded algorithm, 22dB

compared with the OES algorithm and 2 dB compared with the SSPA

algorithm. 0.2%, 0.02% and 0.2% higher glitch energy (calculated through

the total occurrences of the switching activities) due to mismatched switching



- 77 -

timing, compared to the conventional thermometer-coded, switching-

sequence post-adjustment (SSPA)[6] and one-element-shifting (OES) [7]

methods respectively in some conditions.

Figure 4-12 Output spectrum of different algorithms.

Table 4-3 shows the summarized SFDR performance of four different

simulated algorithms and their number of the switching activities. From the

results, we see that the investigated algorithm is comparable to the

thermometer-coded and SSPA and equal with OES due to the based algorithm

(a)

(b)

(c)

(d)

Normalized frequency, fin/fs



- 78 -

used. Hence glitch sizes are expected to be smaller than for the SSPA

algorithm due to implementation of OES as well as conventional SSPA.

Table 4-3 Summary of SFDR comparison for several current cell selection

algorithms.

Algorithm SFDR

[dBc] Diff [dB]

Switching

Occurrences Diff [%]

CTC 58.3 - 2376311 -

OES [7] 60.3 +2.0 2380181 + 0.2

SSPA-CTC [6] 80.7 +22.4 2376311 0.0

Investigated 82.4 +24.0 2380692 + 0.2

4.2.6 Conclusion

The algorithms for current-steering DACs SFDR improvement by

minimizing current source mismatches and glitches have been

investigated.

Combination of Switching-Sequence Post-Adjustment (SSPA) and One-

Element-Shifting method has been proposed due to their abilities in

reducing random static error caused by current source mismatches and

changing the output signal from the data-dependent output to clock-

dependent output signal.

A 10-bit unary weighted current-steering DAC was employed to

demonstrate the proposed algorithm effectiveness which was adopted as

a foreground calibration technique.

MATLAB simulator has been used to simulate and validate the proposed

method.

The simulation results show that the proposed algorithm obtained better

SFDR level compared to the conventional thermometer-coded, OES and

SSPA algorithms. In addition, the total switching activities are slightly

increased than thermometer-coded algorithm.

The proposed algorithms are relatively easy to be extended into more

complicated method due to its fully digital implementation.

Finally, by remarking that conventional SSPA in [6] uses a current

comparator with sophisticated analog circuit design, however the time-



- 79 -

domain analog method of digital circuit implementation for current

comparison in [7] would make the investigated method more suitable for fine

CMOS processes. Otherwise, the precision of the measurement circuit used

is still becoming a trade-off to the overall of this technique.

Figure 4-13 SFDR performances versus mismatch percentages obtained by

different algorithms and number of bits.

Figure 4-14 Estimation of glitch performances versus input frequencies

obtained by different algorithms and number of bits.



- 80 -

References

[1] R. J. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-

to-Analog Converters, Springer (2010).

[2] R. J. van de Plassche, Integrated Analog-to-Digital and Digital-to-

Analog Converters, Kluwer Academic Publishers (1994).

[3] C. H. Lin and K. Bult, “A10-b, 500-MSample/s CMOS DAC in 0.6

mm2”, IEEE J. of Solid-State Circuits, vol.33, no.12, pp.1948-

1958,(Dec.1998).

[4] G. Raja, and B. Bhaumik, “16-bit Segmented Type Current-Steering

DAC for Video Application”, 19th Int. Conference on VLSI Design

(VLSID), pp.1-6, Hyderabad, India (Jan. 2006).

[5] A. Van denBosch, M. Borremans, J. Vandenbussche, G. Van der Plas,

A. Marques, J. Bastos, M. Steyaert, G. Gielen, W. Sansen, “A 12-bit

200 MHz Low Glitch CMOS D/A Converter”, IEEE Custom Integrated

Circuits Conference (CICC), pp.249-252,Santa Clara, CA, (May 1998).

[6] T. Chen, and G.Gielen, “A 14-bit 200-MHz Current-Steering DAC with

Switching-Sequence Post-Adjustment Calibration”, IEEE J. Solid-State

Circuits, vol. 42, no. 11, pp. 2386-2394, (Nov. 2007).

[7] H. P. Ninh, M.Miyahara, and A.Matsuzawa,”A 83-dB SFDR 10-MHz

Bandwidth Continuous-Time Delta-Sigma Modulator Employing a

One-Element-Shifting Dynamic Element Matching”, IEEE Int.

Symposium on Radio-Frequency Integration Technology (RFIT),

Beijing, China, pp. 109-112(2011).



- 81 -

4.3 Proposed calibration technique II: Algorithm to improve

current-steering DAC linearity by digital calibration of

selected pairs of current source cells

Fast-growing markets for telecommunication devices such as mobile phones,

wireless modems, and avionics devices have increased demands for high-

speed, high-accuracy digital-to-analog converters (DACs) [1]-[5]. In the

transmitter path, DACs convert digital signals into analog signals. In order to

avoid noise leakage from transmitter to receiver, accurate DACs with

sufficient Spurious-Free Dynamic Range (SFDR) are required. Commonly

DAC performance is degraded due to non-ideal dynamic performance and

nonlinearity. Improving these is very important.

As society needs faster, cheaper, and more reliable communication, DAC

block design becomes more complicated, although digital electronics have

benefited from advances in CMOS technology. However, there are still

fundamental physical constraints—such as noise, component matching, and

fabrication process parasitics—that need to be mitigated. DAC linearity must

be sufficient to accommodate requirements, despite these constraints. For

resolution less than 10 bits, such constraints may not be a big problem, but

for current-steering DACs with higher resolution, current mismatch effects

that cause nonlinearity and limit the SFDR are a major problem[1]-[3], [6]-

[8].

This research work describes a half-unary current-steering DAC that uses

selected pairs of current source cells to reduce mismatch. In this work, a

technique called 3-stage current source sorting is developed to further reduce

mismatches, especially random static mismatches.

This technique is divided into two main stages: the first stage selects the

optimum combination of half-unary weighted current source cells to pair up,

such that the error of one cell in the pair cancels that of the other, each pair

forming a unary-weighted current source. In the second and third stages, the

switching of pairs is optimized: current-source pairs are organized into

groups of pairs such that the combined current is closest to n times the unit

current. Thus, during calibration, both minimize current source mismatch and

optimize switching group selection sequence can be automatically achieved.

In addition, by doing that, even smaller standard deviations between selected

groups of current sources also can be obtained.

Our method uses only a digital technique (a ring oscillator and a counter) to

measure the order of the current sources and does not need analog circuits

such as comparators or a precise AD converter. The half-unary weighted is

realized in the MSB part of a segmented architecture with 3C-CS algorithm

is adopted in calibration technique which is then performed in the digital



- 82 -

domain. Also we describe clock-tree-like layout and routing topology of

current source and switch arrays to minimize clock and signal skews and

improve the dynamic performance.

4.3.1 Half-unary architecture

In this section, the new proposed architecture based on a half-unary weighted

structure is introduced (Figure 4-15). This architecture is employed with a

proposed digital algorithm as one calibration technique in a segmented

current-steering DAC. With a half-unary weighted architecture for higher-

order bits and a binary-weighted architecture for lower-order bits, this

research work objectives aim to reduce the effect of current source

mismatches and improving the DAC linearity by optimizing the switching

sequence. Therefore, the linearity of DAC can be obtained, hence, better

SFDR can be achieved. Moreover, the effect of the 2nd and the 3rd order

harmonic distortions are also effectively suppressed resulting not only for

better dynamic performance but also for the relaxation of the analog filter

requirement.

Figure 4-15 Proposed half-unary architecture.

Compared to a conventional unary architecture, a half-unary architecture

uses double the number of current sources, 2(2N-1) each with half the unary

current value. As referred to Figure

𝐼1 = 𝐼2 = ⋯ = 𝐼13 = 𝐼14 = 0.5𝐼 (𝟒. 𝟐)

Increasing the number of current sources increases the selection choices

which can later be used for differential nonlinearity reduction. On the other



- 83 -

hand, it will increase silicon chip area and routing complexity, so a trade-off

is required. However, a clock tree based layout is introduced and discussed

later, can reduce the routing complexity.

In this work, the segmented architecture is employed—but for SFDR

improvement, the higher-order bits which the unary-weighted structure is

normally used is more important, and hence this discussion is focused on the

half-unary architecture as the unary-weighted structure replacement.

As demands of portable devices increase, the smaller device size and the

lower supply voltage are required. For example, a 90 nm technology process

with a supply voltage of 1.0V ±10%, the design of analog circuits with high

performance becomes challenging. It caused the increment number of

interconnection layers. Normally, 6 to 8 layers is still accepted as a standard.

In addition, the reduction of transistor size leads to the increment of the layer

thickness which is the thickness layers larger than the transistor width. This

means that the interconnect capacitance between two adjacent layers

increases. As a result, the delay over these wire wires also increases.

Therefore, there are considerations that need to be taken into account in a

design stages.

In practical MOS technologies, current source mismatch is influenced by

threshold mismatch, Vth, or by slope mismatch,

. This work considers

current source mismatches caused by different values of threshold voltage.

As shown in Figure 4-16(a), mirrored current sources with ideal threshold

voltages produce the same current value. However, mismatch among current

source cells results in different current values (Figure 4-16(b)).

In practice, these mismatch effects can be reduced during semiconductor

processing by reducing gate oxide thickness. This allows the supply voltage

to be decreased. However, reduced supply voltage adversely affects signal-

to-noise ratio. In order to maintain the signal-to-noise ratio, more bias current

is required, resulting in increased power draw. Another trade-off is between

threshold voltage and device size. Increasing the gate size reduces the offset

but increases the device area. Moreover, the capacitance of the devices is also

increased. Larger bias current is required, which increases the power draw.



- 84 -

(a) Ideal case.

(b) Mismatch case.

Figure 4-16 Mirrored current source structure.

Here, we consider reducing current mismatches by post-fabrication

calibration rather than pre-fabrication such as MOS matching techniques.

4.3.2 3-Stage Current Source Sorting (3S-CS) algorithm

Sort-and-group techniques are widely used post-fabrication techniques,

described in other published works [2], [4], [10], to reduce the effect of static

errors. Basically, these techniques are intended to optimize the switching

selection. In [2], switching-sequence post-adjustment method is performed

by sorting the current source cells by their current values and rearranging

their selection order. By using unary-weighted current sources, all the

measured current source values are sorted in ascending order. Then, the

smallest and the largest current values are grouped as a pair of unary

weighted current sources, and the values of these two current sources are

summed. After all unary-weighted current sources are paired and their

current values are summed, only the pairs are sorted for a second times by

Iref I1 I2

Vth Vth1 Vth2

….

IN

VthNVth3

I3

Vdd

Iref I1+I1 I2+I2

Vth Vth1

+Vth1

Vth2

+Vth2

….

IN+IN

VthN

+VthN

I3+I3

Vth3

+Vth3

Vdd



- 85 -

their summed values. Then, the smallest and the largest summed current

values are rearranged. Lastly, by disassociating the pairs of two unary-

weighted current sources to each single unary weighted current source cell,

the final sequence is obtained. This method reduces only Integral non-linear

(INL) errors, but differential non-linearity (DNL) errors still remain. In [10],

the complete-folding method is used to combine unary current cells in a

group of unary current cells with different weights. By employing such a

technique, mismatch errors can be eliminated before conversion, since two

or more current sources are grouped together. The remaining mismatches are

averaged during conversion. This method improves both INL and DNL

performance. However, the steps of this method increase with increments in

the number of bits.

Recently, several methods for approaching dynamic mismatch have become

available, either based on 3-dimensional sort-and-combine methods [4], or

mapping methods [8]. These two examples combine two or more mismatch

sources together as vector errors and resolve them once using the respective

methods mentioned.

In our work, we have merged these two techniques in [2] and [10] into one

and called it as a “3-stage current source sorting” (3S-CS) procedure. This

procedure is divided into two main stages: combine and rearrange. Figure 4-

17 shows the steps of 3S-CS procedure using a 3-bit half-unary-weighted

current-steering DAC with 14 available current source cells (twice the

number of a conventional unary-weighted architecture, 2(2N-1))). The 3S-CS

procedure steps are as following:

The 3S-CS procedure

: The current source cells in the original order.

1st stage:

: The current source cells are compared and sorted by their current values

in ascending order.

: Then, the smallest and largest current values (in this example, I3 and I7)

are combined to form a pair of half-unary weighted cells. Next pair the

second smallest current value, I14, with the second largest current value,

I10 , the third smallest current value, I11, with the third largest current

value, I4, and continue until all half-unary weighted cells are paired.



- 86 -

There should be 2N-1 half-unary pairs.

2nd Stage:

: The half-unary pairs are compared and sorted again by their summed

current values in ascending order.

: By repeating the procedure in step, the sorted half-unary pairs are

grouped, and their current values are summed. These 2N-1 half-unary

pairs are grouped into pairs, with a single half-unary pair left over.

3rd stage:

: For the third stage, only the grouped pairs of half-unary pairs are

compared and sorted by their summed current values, with a single half-

unary pair left over.

: The sorted pairs of half-unary pairs are rearranged as per the procedure

in step.

: Lastly, by disassociating the groups of four half-unary weighted cells

down to pairs of half-unary cells with the half-unary pair with smaller

value coming first in each group, a new switching sequence is obtained.

I7 I6 I5 I4 I3 I2 I1I8I9I10I11I12I13I14

① Original

I7I6 I5 I4I3 I2 I1I8 I9 I10I11 I12 I13I14

② 1st sorting

I7

I6

I5I4

I3 I2

I1

I8

I9I10

I11 I12

I13

I14

③ 1st arranging

& associating

1st STAGE



- 87 -

Figure 4-17 Proposed 3-stage current sorting method.

Compared with [2], the number of steps is slightly increased, but is

significantly less than [10] for the same resolution. This is because our

proposed method does not require any additional steps for difference

resolution. This method reduces both non-INL and DNL errors.

I7

I3

I1

I8 I2

I9 I4

I11

I5

I12I6

I13

I10

I14

④ 2nd sorting

2nd STAGE

I1

I8

I7

I3

I4

I11 I2

I9

I5

I12I6

I13

I10

I14

⑤ 2nd arranging

& associating

I1

I8

I7

I3

I4

I11I2

I9

I5

I12 I6

I13

I10

I14

⑥ 3rd sorting

I1

I8

I7

I3

I4

I11I2

I9

I5

I12I6

I13

I10

I14

⑦ 3rd arranging

3rd STAGE

I1

I8

I7

I3

I4

I11I2

I9I5

I12I6

I13I10

I14

⑧ New current source

switching sequence



- 88 -

4.3.3 Circuits

In order to optimize the DAC output, a few modifications to the traditional

current-steering DAC architecture have been made. In this section, three

circuit modifications are explained.

4.3.3.1 Current source design

A simple differential pair of current source cell consists of a transistor as a

current source cell and another two transistors as switches (Figure 4-18(a)).

This current source cell has low output impedance. This is because, at low

frequencies, the output impedance of the current source is equal to the

impedance of the transistor itself. However, when the frequency is increased

the impedance is reduced due to the drain capacitance of the system. This is

true when the switch is operated as a low impedance switch. At the moment

of switch Msw1, Msw2 is operated in saturated mode, the output impedance

increases with a factor gmsw1, sw2RoutMsw1, Msw2. This multiplication is

depending on the channel length of the Msw1 and Msw2. To increase the output

impedance, a cascoded current source is used (Figure 4-18(b)). By adding

McasCS, the output impedance increases with gmcasCSRoutMcasCS. This means, the

extra multiplication of output impedance is possible at high frequency. This

not only increases the output impedance but also provides node isolation

between the current source cells and switches.

(a) Basic. (b) Cascoded.

Figure 4-18 Current source structures.



- 89 -

4.3.3.2 Cascoded current source cell

For conventional current source design, the accuracy of a current source is

dependent to their transistor size matching. However, due to the fabrication

process variation, the transistor size can be varied each other. This will cause

the random error. Let consider that a transistor 𝑋 and it random error is ∆𝑋.

Equation 4.3 shows that the standard deviation of a transistor random error

is inversely proportional to the square root of the transistor size.

𝜎(∆𝑋) =𝑎

√𝐿𝑊 (𝟒. 𝟑)

Where 𝑎 is a constant which is depending on the process and material that

be used.

To realize a high-speed current-steering DAC, a well-matched transistors in

current source mirror is required. Thus, the drain current Id produces by each

transistor of each current source cell is constant. Again, as mentioned earlier,

the fabrication process can affects the value of threshold voltage 𝑉𝑡ℎ each

transistor in result of different current values are produced. Ideally, the drain

current Id can be obtained by Equation 4.4:

𝐼𝑑 =1

2𝜇𝐶𝑜𝑥

𝑊

𝐿 (𝑉𝑔𝑠 − 𝑉𝑡ℎ)

2

(1 + 𝜆𝑉𝑑𝑠) (𝟒. 𝟒)

Where 𝜇 is the electron mobility, 𝐶𝑜𝑥 is the capacitance per area, 𝑉𝑔𝑠 is

the ground-source voltage, 𝜆 is the length channel modulation and 𝑉𝑑𝑠 is

drain-source voltage. By assuming that 𝜆 = 0, and 𝛽 = 𝜇𝐶𝑜𝑥𝑊

𝐿, Equation

4.4 can be simplified as Equation 4.5:

𝐼𝑑 =𝛽

2 (𝑉𝑔𝑠 − 𝑉𝑡ℎ)

2 (𝟒. 𝟓)

Assume that gate-source voltage 𝑉𝑔𝑠 and gain 𝛽 is constant, the drain

current is proportionally changed by the changes of threshold voltage. Thus,

the different value of the transistor threshold voltage, it leads to produces



- 90 -

different drain current. As a result, the different output result is obtained

compared to desired value.

Derivation between two transistor with different threshold voltage value, the

current mismatch at small current densities is given by Equation 4.6:

Δ𝐼𝑑

𝐼𝑑=

2Δ𝑉𝑡ℎ

𝑉𝑔𝑠 − 𝑉𝑡ℎ (𝟒. 𝟔)

Since the Δ𝑉𝑡ℎ =𝐴𝑉𝑡ℎ

√𝑊𝐿 as referred to Equation 4.3, the current mismatch

can be further expressed as Equation 4.7:

Δ𝐼𝑑

𝐼𝑑=

2

𝑉𝑔𝑠 − 𝑉𝑡ℎ

𝐴𝑉𝑡ℎ

√𝑊𝐿 (𝟒. 𝟕)

Where 𝐴𝑉𝑡ℎis the threshold voltage mismatch coefficient. It is varied by

fabrication process. It is known from literature in [12] that increasing the

transistor size can reduce the mismatch. However, in practical situation, the

device size variations is limited. Therefore, increasing the biasing current ca

be considered but it is cost to more power consumption. As a result, the

optimized transistor size combined with acceptable biasing current is

possible to produce better performance.

Figure 4.19(a) shows the basic transistor from the top-view. L and W is the

length and width of the transistor respectively. While Figure 4.19(b) is the

cross-section view of same transistor.

Normally, mirrored current source is used in the current-steering DAC. For

unary-weighted current source cells, the same transistor size as in Figure 4-

19(a) can be constructed as in Figure 4.20.



- 91 -

(a) Top-view.

(b) Cross-section.

Figure 4-19 Transistor structure.

Figure 4-20 Multiple current sources with same transistor size.

For a binary-weighted current source cell, to form different weighted values

of current source cell, it can be done by charging the ratio of W/L of the

transistor. Let consider that Figure 4-19(a) as a reference basic current

source cell with W and L that produces I. In order to produce 2I, it can be

achieved by doubling the width as shown in Figure 4-21.



- 92 -

Figure 4-21 Multiple current sources with different transistor size.

However, if the different weighted current source in Figure 4-21 is realized as

in Figure-4.22(a), the mirrored current source might be suffered from poor

transistor matching effects because of the different size implementation. As

solution, the implementation as in Figure 4-22(b) is more recommended.

(a) Poor layout.

(b) Good layout.

Figure 4-22 Current source layout.



- 93 -

Figure 4-23 Current source layout with compensated width.

In this research, we proposed to implement the half-unary weighted current

source structure compared to the conventional unary-weighted current source

structure. Thus, in order to realize our proposed structure to produce better

current steering DAC performance by calibrating half-unary current source

using digital algorithm. Assume that a basic unary-weighted current source

structure as in Figure 4.19(a), a half-unary weighted current source structure

formed by halved the width of transistor as shown in Figure 4-24(a). While

Figure 4-24(b) illustrates the proposed half-unary weighted current source

network.

(a) Transistor.

(b) Network.

Figure 4-24 Half-unary current source.



- 94 -

The advantages of this structure is remained the area of current source

structure but the total device area increases by increment the wiring and logic

decoder circuit as compared to the structure in Figure 4-20. Moreover, due

to the reduction of width, the standard deviation of random error imposes in

threshold voltage is increased. Consider that the standard deviation for

random error of unary-weighted current source structure is given in

Equation 4.8:

Δ𝑉𝑡ℎ =𝐴𝑉𝑡ℎ

√𝑊𝐿 (𝟒. 𝟖)

While Equation 4.9 presents as the standard deviation of half-unary-

weighted current source structure.

Δ𝑉𝑡ℎ =𝐴𝑉𝑡ℎ

√𝑊𝐿/2=

√2𝐴𝑉𝑡ℎ

√𝑊𝐿 (𝟒. 𝟗)

Thus, the standard deviation of random error imposed half-unary-weighted

current source structure increases by factor of √2 compared to unary-

weighted current source structure. Even though the standard deviation of

random error has increased, the adopted calibration can be used to fix this

problem.

4.3.3.3 Folded cascode current source cell

For a high speed current-steering DAC, the accuracy of the current source by

matching the transistor size is important to provide the better output

performance. In previous chapter, the usage of cascoded current source

structure is explained due to its ability to provide a better output impedance

compared to its conventional structure. Figure 4-25(a) and Figure 4-25(b)

show the basic current mirror and cascoded current mirror. From Figure 4-

25(a), M1 and M2 are used as a mirrored current source. By assuming that

M1 and M2 have the same width and length, it provides the same gate-source

voltage, Vgs1=Vgs2. In addition, by neglecting the effect of channel-length

modulation, the same drain current Id1=Id2 between these two transistors is



- 95 -

also can be realized.

(a) Basic. (b) Cascoded.

Figure 4-25 Current mirror structure.

In current mirror implementation, the values of the threshold voltages are

critical. It is very important to determine the overall accuracy of the mirror.

In order to matching current mirror due to the effect of threshold voltage

mismatch. By referring to the basic current mirror in Figure 4-25(a), since

both paths M1 and M2 have the same value of Vgs and assume that the sizes

and transconductance parameters are equal, the effect of a mismatch in

threshold voltages between these two transistors can be derived as

Equation 4.10 and Equation 4.11

𝑉𝑡ℎ1 = 𝑉𝑡ℎ𝑛 −Δ𝑉𝑡ℎ𝑛

2 (𝟒. 𝟏𝟎)

𝑉𝑡ℎ2 = 𝑉𝑡ℎ𝑛 +Δ𝑉𝑡ℎ𝑛

2 (𝟒. 𝟏𝟏)

Where 𝑉𝑡ℎ𝑛 is the average value of 𝑉𝑡ℎ1 and 𝑉𝑡ℎ2 and ∆𝑉𝑡ℎ𝑛 is the

mismatch, then, 𝐼𝑜

𝐼𝑟𝑒𝑓 is derived as Equation 4.12:

𝐼𝑜

𝐼𝑟𝑒𝑓=

𝐾𝑃𝑛

2𝑊𝐿 (𝑉𝑔𝑠 − 𝑉𝑡ℎ𝑛 −

∆𝑉𝑡ℎ𝑛

2 )2

𝐾𝑃𝑛

2𝑊𝐿 (𝑉𝑔𝑠 − 𝑉𝑡ℎ𝑛 +

∆𝑉𝑡ℎ𝑛

2 )2 =

[1 −∆𝑉𝑡ℎ𝑛

2(𝑉𝑔𝑠 − 𝑉𝑡ℎ𝑛)]

2

[1 +∆𝑉𝑡ℎ𝑛

2(𝑉𝑔𝑠 − 𝑉𝑡ℎ𝑛)]

2 (𝟒. 𝟏𝟐)



- 96 -

If both expressions are squared and the higher order terms are ignored, then

the first-order expression for the ratio currents becomes

𝐼𝑜

𝐼𝑟𝑒𝑓≈ 1 −

2∆𝑉𝑡ℎ𝑛

𝑉𝑔𝑠 − 𝑉𝑡ℎ𝑛= 1 −

2∆𝑉𝑡ℎ𝑛

𝑉𝑑𝑠,𝑠𝑎𝑡 (𝟒. 𝟏𝟑)

From Equation 4.13, it shows that as Vgs decrease, the difference in the

mirrored currents increases due to the threshold voltage mismatch. This is

particularly critical for devices that are separated by relatively long distances

because the threshold voltage is susceptible to the process gradient. Therefore,

to attain high speed conversion and reduce the threshold voltage mismatch, a

large gate overdrive voltage is required. This is because of 𝑉𝑜𝑣𝑛 = 𝑉𝑑𝑠,𝑠𝑎𝑡 =

𝑉𝑔𝑠 − 𝑉𝑡ℎ𝑛 for long-channel process. Hence, it is reduced range of compliance

as a drawback.

Cascoded current source mirror as in Figure 4-25(b) is used to provide better

output impedance by increasing the output resistance of a current mirror, so

that it behaves more ideally. Cascode is a vestige from the days of vacuum

tubes when a common-cathode amplifier was cascaded (in series with) a

common-grid amplifier. As shown in Figure 4-25(b), 𝐼𝑜 is determined by the

gate-source voltages of MI and M2. Changing the sizes of M3 and M4 simply

changes the drain-source voltages of M1/M2. As a result, the matching of their

drain currents will affected. Therefore, it is important to hold the drain-source

voltages of M1/M2 more constant to increase the current mirror’s output

resistance. In addition, if the drain-source voltage is constant, then the current

does not vary.

Folded cascode current source structure is constructed by connecting a NMOS

current source to a PMOS current source and fold the cascode structure over

and diode-connect the folded NMOS devices as shown in Figure 4-26.

Therefore, the gate potentials of M1 and M2 are set by the current that sourced

from M5 and M7. If the transistors are perfectly matched, the output voltage

will equal with the gate voltage of M1 (the drain voltage of M3) because of

the circuit’s symmetry. The advantages of this structure are as follow:

High Gain

Improved Bandwidth



- 97 -

High Slew rate

High stability

High input impedance

The folded cascode structure is useful for moderately low supply voltages,

at the cost of some extra current, but has limited performance in sub 1V

application.

Figure 4-26 Folded cascode current mirror structure.

4.3.3.4 Digital current measurement circuit based on ring oscillator

Calibration methods can be categorized as calibration with error

measurement [1], [2], [4], [8], [10] or calibration without error measurement

such as dynamic element matching [3], [7], [11]. Both categories have

strengths and weaknesses. By performing error measurement, an exact error

profile can be obtained, and calibration can be performed either in the

foreground or background. However, the effectiveness of such calibration

relies on the accuracy of the measurement circuit. There are several types of

calibration circuits for error measurement, such as extra calibration

ADC/DAC circuits [1] (Figure 4-27(a)), the high-precision current

comparator [2], [4], [10] (Figure 4-27(b), Figure 4-27(c)) and the current



- 98 -

sensor based on a combination transimpedance amplifier (TIA) and ADC

circuit [8]. Such analog circuits can increase noise and implementation cost.

As the error measurement circuit may actually degrade performance, it’s a

challenge to create a simple calibration circuit with low noise. In contrast,

calibration without error measurement is performed without knowledge of

error by averaging the accumulated errors over the conversion time. However,

this method can only perform in background mode. Moreover, the

complexity of the circuit also increases. As a result, the power consumption

and noise are increased and hence, overall performance deteriorates.

In this work, we are considering implementing calibration by the error

measurement approach as it is a good match with our proposed techniques.

(a) An example of self-calibration circuit [1].

(b) SSPA calibration circuit [2].



- 99 -

(c) Complete-folding calibration circuit [10].

Figure 4-27 Examples of previously published calibration techniques.

Compared with the works in [1], [2], [10], the difference is that a digital

current measurement circuit based on a ring oscillator is introduced (Figure

4-28(a)). By adopting this circuit, analog circuits such as comparators or a

precision AD converter are no longer needed.

(a) Digital current measurement based on ring oscillator.

(b) Case of a low measured current.



- 100 -

(c) Case of a high measured current.

Figure 4-28 Digital measurement circuit and different measured current

cases.

This can be realized by counting the number of cycles generated by the ring

oscillator circuit within a cycle of a fixed clock period. The relationship

between the measured current values and the number of cycles counted

during a cycle of the fixed clock varies depending on the circuit configuration.

As illustrated in Figure 4-28(b), when the measured current is small, only a

few peaks within the rise to fall time of the fixed clock cycle period are

counted. On the other hand, as the measured current increases, more peaks

are counted (Figure 4-28(c)). This is due to more inverters inside the ring

oscillator loop turning on to generate a larger signal in the same fixed clock

cycle period. Thus, the measured current value is proportional to the number

of counts.

Due to the necessity for measuring each current source values, the foreground

calibration technique is chosen. During the calibration, the converter must be

taken off line to allow the current source cell be measured by the current

measurement circuit after be removed from the output line. The total

calibration time is determined from the beginning of the first test code is

loaded from memory to turn ON the switch that control the connection

between current source and current measurement circuit until the optimized

switching selection is stored in the decoder. Due to the large number of

current source cells use in the half-unary weighted DAC, the total calibration

time is strongly dependent to the number of current source cell. Although the

foreground calibration technique not affects the conversion time, but it still

need to be concerned with total calibration time as it affects testing cost.



- 101 -

4.3.3.5 Calibration technique

As mentioned in previous section, calibration divided into two categories;

with and without error measurement. In the category of calibration with error

measurement, it is divided into another three classes which are self-

calibration, mapping/ switching scheme and pre-distortion.

In this work, the second class is chosen. By using the 3S-CS algorithm, the

current source cells selection is mapped to the new switching sequence. That

means, the collection of chosen combinations for all input codes are defined

as in the new switching sequence. Therefore, during conversion process, this

new switching sequence will behavior like in the conventional thermometer

coding but the accumulated errors are controlled during each updated code.

Therefore, this switching sequence shares the advantages of the thermometer

coding - low glitch energy and low power consumption for incremental code

transitions. This mapping method is also known as static map. The main

limitation of this technique is the method which can be applied only to the

MSB DAC part in the DAC segmented architectures. The effectiveness of

the method and its hardware requirement grow exponentially for each extra

bit decoded in a unary way.

Generally, self-calibration of current source and mapping switching sequence

is similar in term of the targeted error mechanism. Depending on the class,

these two classes have their own advantages and disadvantages. The self-

calibration is able to correct both random and systematic mismatch errors by

adjusting the DAC current source cells and hence correct for mismatched

related to amplitude and timing errors. But it is interacted with the analog

DAC signal generation. On the other hand, the mapping method avoids

interacting with analog DAC signal by adjusting the distribution order of the

mismatch errors, creating mutual cancellation and effectively correcting

them. Although, it is not that powerful in correcting systematic mismatch

errors. Therefore, it is a matter of trade-off, since the correction methods

bring its own particular advantages and disadvantages.

The overall calibration flow is shown in Figure 4-29. Either for stand-alone

half-unary or segmented architecture, the calibration circuit composes five



- 102 -

parts: current source matrix, digital current measurement circuit, calibration

controller circuit, random access memory (RAM) unit, and look-up table

(LUT) based decoder. First, the calibration code of 000…001 to 100…000

from RAM is inserted to control the switch. The switch turns ON to connect

the current source cell to the input of the digital current measurement circuit.

At the same time, the current of all available current source cells (in case of

fully half-unary DAC architecture) or the most significant bit (MSB) part for

the upper part in a segmented DAC architecture is measured using our

proposed digital measurement circuit. Then, all the measured values are

converted into a count number and temporarily saved in RAM. Then, the

calibration controller loads the stored values RAM and calibrates them using

the proposed algorithm. The optimized current source selection obtained

from the calibration is stored in the LUT decoder, which is later used for

conversion.

Figure 4-29 Flows of calibration technique.

The advantages of our calibration technique are due to a simple measurement

mechanism and a fully digital implementation. However, there is a trade-off

between the accuracy of the measurement circuit and the overall area and

performance of the DAC. The simple bubble-sort algorithm can be used to

speed up the calibration process.

4.3.3.6 Consideration of re-calibration

In our proposed, we plan to make the calibration process once after the

fabrication process before shipping the devices. However, due to the

Current

to Counter

Calibration

Circuitry

LUT

Decoder

MSB

Array

LSB

Array RL RL

Vout

Vout

LSB

Inputs

(binary code)

MSB

Inputs

(binary code)

RAM

…



- 103 -

possibility which is in case of the current source values are changed due to

the temperature or long operational time, the consideration of re-calibration

is possible. There are two ideas which can be thought. Firstly, by setting the

total current value that can be obtained from the look-up table after the first

calibration process, the output current within the acceptable range can be

monitored. Once the total current value is out of the acceptable range, then

there is some mechanism that indicates for re-calibration. Secondly, by

setting a number of the operating time. So, the re-calibration process can be

set to run automatically when the number of operating time is equal to set

one. As expected result, the accuracy of the DAC can be maintained while

there is no malfunction components existed.

4.3.3.7 Look-up table in memory based decoder

In chapter 4, we focused on the usage of RAM for LUT based decoder to

store the measured current source values. This is because the advantages of

RAM that allow to write and read data with the large storage capacity.

However, DRAM speed referred to Table 4.4 shows that DRAM provides

the slower performance. Therefore, to take up reconsideration to replace the

RAM with other available memory type is possible. One of the possible

candidates is flash memory which can provides similar performance with

DRAM with better operating speed. As stated in Table 4.4, flash memory is

divided into two types: NOR and NAND based flash memory. The

comparison between these two types of flash memory can be pointed out as

in Table 4.5. As a result, the NAND based flash memory is more suitable to

replace the conventional RAM due to their similarities. However, NAND

based flash memory is limited by only allows for single page access, unlike

the RAM. Therefore, the combination of both RAM and flash memory in

parallel implementation compromises better performance in terms of storage

and speed.



- 104 -

Table 4.4 Types of memory.

Physical Random access memory

(volatile)

Read-only

memory

(non-

volatile)

Combination RAM &

ROM

(non-volatile)

Type

RAM ROM Flash

SRAM

DRAM

SDRAM

DDRAM

PROM,

EPROME

EPROM

NOR-

based

flash,

NAND-based

flash

Capability Read and/or write Read only Read & write

Memory

condition

Memory is erased when

the power is OFF

Not

erasable

Memory is not erased

when the power is OFF

Speed Fast

25ns

Moderate

60ns Fast

As fast as DRAM but not

as fast as SRAM or ROM

NOR < NAND

Cost Expensive Less

expensive

Less

expensive Less expensive

Refresh rate 70 ns 64 ms 70 ns 70 ns/bit

Table 4.5 Performance comparison between NOR and NAND based flash

memory [13].

NOR NAND

Application Code execution File storage

Storage density Low High

Cost - Better

Active power - Better

Standby power Better -

Write speed - Good

Read speed Good -

4.3.4 Clock-tree based layout

The half-unary architecture has doubled the number of current sources,

which not only increases the area of logic and decoder circuit, but also the

complexity of the layout in terms of routing that could suffer the risk of high

parasitic effects. Theoretically, the wiring capacitance depends upon the

length and width of the interconnecting wires. Resistance is added by



- 105 -

transitions between routing layers (contact through via). However, inductive

effects can be ignored if the resistance of the wire is substantial enough; in

case of a long aluminum (or copper) wires with small cross section, or if the

rise and fall times of the applied signals are slow. For a high-speed DAC, the

first condition might be satisfied but not the second, because fast rise and fall

times are compulsory. Thus, the effect of parasitics cannot be neglected.

Moreover, if only a single parasitic component (C, R, or L) is dominant, the

effect of parasitics is not so significant. However, if there is a combination of

(C, R, or L) components, this introduces propagation delay problems. Thus,

it is important to reduce the parasitic effects.

In this work, in order to deal with such problems, the proper layout especially

for routing is highly needed to provide an optimized length, width and cross

section of the wires. For the introduced clock-tree-like layout, the same

length between each current source and load resistor can be achieved (Figure

4-30). The symmetrical layout also provides a balance of capacitance and

resistance values. This means that the effects of both capacitance and

resistance within interconnection wires from current source cells to load

resistor can be reduced. At the same time, the propagation delay differences

between interconnections can be minimized as well.

Figure 4-30 Clock-tree-like based layout.

4.3.5 Simulation results and discussions

For verifying our developed algorithm and calibration procedure, we have

evaluated a 12-bit half-unary current-steering DAC using the MATLAB

Route

Clock tree-based

layout

Route

Load

resistor

Current cells

& switches



- 106 -

simulator. This simulation results are important which later can be used for

higher resolution such as 14-16 bit segmented current-steering DAC

architecture using a 12 bit half-unary weighted cells as MSB part and 2-4 bit

binary weighted as LSB part. Figure 4-31 to Figure 4-36 show the

simulation results for the conditions summarized in Table 4-4.

Table 4-6 Simulation condition.

Resolution, N 12-bit

Input frequency, fin 12.8 MHz (single tone)

Sampling

frequency, fs 819.2 MHz

Simulation iteration 100 times

Distribution type Normal distribution, N(0,)

(= 0.001 ~ 0.25 A)

The simulation results compare a conventional unary weighted DAC and the

proposed half-unary weighted DAC, considering only current source

mismatches, and not considering glitch effects. For comparison purposes, the

yields of INL and DNL have been simulated to determine the value of relative

standard deviation, , for 12-bit resolution. After 100 simulation iterations

for each in the range of 0.0001A to 0.25A, Figure 4-31 shows that 99.7%

yield of the INL < 0.5 LSB obtained by half-unary weighted cells with 3S-

CS switching scheme is better matching requirement compared to INL yield

of

Figure 4-31 INL Yield.

0

20

40

60

80

100

0.001 0.01 0.1

Yie

ld (

%)

Standard deviation, (A)

INL Yield < 0.5 LSB

Unary+TCThis work



- 107 -

Figure 4-32 DNL Yield.

unary weighted with conventional thermometer coded switching scheme in

the same condition. The result shows that conventional unary requires

0.002A to get a yield of 99.7%. However, using the developed method,

the matching requirement is reduced to 0.004A, a relaxation of 50%. The

same applies to the DNL in Figure 4-32.

Figure 4-33 shows average SFDR performance for various values. From

our simulation results, average SFDR values obtained for a conventional

unary architecture decrease with increased However, the average SFDR

values obtained using our proposed calibration technique remain at > 90 dBc

from = 0 up to 0.05A. This means that, at= 0.05A, the maximum

difference between the conventional and proposed methods is 20 dB.

Figure 4-33 Average SFDR performance vs. standard deviation.

It is almost impossible to filter out 2nd and 3rd order harmonic distortion by

0

20

40

60

80

100

0.001 0.01 0.1

Yie

ld (

%)


DNL Yield < 0.5 LSB

Unary+TCThis work

50

70

90

110

0.001 0.01 0.1

Level (d

B)


SFDR

Unary+TCThis work



- 108 -

an analog filter especially in Nyquist DACs. Otherwise, in DAC, the 2nd

and 3rd order spurs can be transferred to a higher frequency band by the

oversampling technique which cannot be achieved by a Nyquist DAC. In

order to relax the analog filter requirement for the Nyquist DAC, the effects

of 2nd and 3rd order harmonic distortions need to be suppressed sufficiently.

Thus, we also simulate the effect of the 2nd and 3rd order harmonic distortions

inside the desired band.

Figure 4-34 2nd order harmonic distortion.

Figure 4-34 shows the level of 2nd order harmonic distortion of our proposed

method is less than -100 dBc from = 0 up to 0.05A and is 20 dB better than

a conventional unary architecture from = 0 up to = 0.25A.

Figure 4-35 3rd order harmonic distortion.

Figure 4-35 shows the level of 3rd order harmonic distortion. Compared to the 2nd

-140

-120

-100

-80

-60

0.001 0.01 0.1

Leve

l (d

B)


2nd order Harmonic Distortion

Unary+TCThis work

-140

-120

-100

-80

-60

0.001 0.01 0.1

Le

ve

l (d

B)


3rd order Harmonic Distortion

Unary+TCThis work



- 109 -

order, the 3rd order becomes a dominant spur at a lower valueFrom our simulation

results, 3rd order spur appears larger than 2nd order with maximum difference value

of 7 dB. But, from range of 0.005A up to 0.25A, the 2nd order effects become

dominant spurs by 2 dB compared to the 3rd order. As a result, the range between

0.005A up to 0.05A, the 3rd order spur level is less than -102 dBc. The reduction

factor for both 2nd and 3rd order compared to conventional method is 0.3 and 0.25

respectively.

Figure 4-36 Output spectrum before calibration (= 0.05A).

Figure 4-37 Output spectrum after calibration (= 0.05A).

Figure 4-36 is an example of the output spectrum of a 12-bit half unary

without calibration with fin = 12.8 MHz, fs = 819.2 MHz and = 0.05A. As

shown in the same figure, the SFDR performance is 72 dB. It is clearly shown

that the 2nd order harmonic distortion spur deteriorates the SFDR

HD2HD3

HD2

HD3



- 110 -

performance. In contrast, with the proposed calibration technique, the output

spectrum shows that both 2nd and 3rd harmonic distortions are successfully

suppressed (Figure 4-37). Therefore, the obtained SFDR level is improved

to 99 dBc. The overall performance of our proposed calibration technique

compared with other existing calibration methods are summarized in Table

4-5.

4.3.6 Conclusion

The conclusions are as follow:

A 12-bit half-unary current-steering DAC with high SFDR DAC is

demonstrated. This architecture can be fully realized in digital

implementation which is very suitable for the fine CMOS process.

The 3-stage current sorting technique is developed for improving

linearity as well as dynamic performance.

A digital technique (a ring oscillator and a counter) of current

measurement circuit is employed to measure the order of the current

sources, hence it does not need a precision AD converter or analog

comparator which is suitable for fine CMOS implementation.

The improvement of INL and DNL yield relaxes the matching

requirement by 50% is achieved. In addition, the SFDR performance is

improved by 20 dB compared to a conventional unary circuit with

thermometer-coded switching scheme.

The clock-tree-like layout and routing topology of current cell and switch

arrays is utilized in order to minimize the clock and signal timing skews.



- 111 -

Table 4-7 Performance comparison.

[2]

JSSC

2007

[8]

JSSC

2011

[4]

ISSCC

2014 This work

Architecture Segmented

(7T+7B)

Segmented

(6T+8B)

Segmented

(6T+10B) Half-unary

Technique 1D, SG 2D, Mapping 3D, SG 1D, SG

Error, Amplitude Amplitude,

Timing

Amplitude,

duty cycle,

delay

Amplitude

Resolution, N 14-bit 14-bit 16-bit 12-bit

Sampling

rate, fs 200 MS/s 200MS/s 3.2 GS/s 819.2 MS/s

INLafter 1.37 LSB 1.8 LSB - 0.2 LSB

DNLafter 0.76 LSB 2 LSB - 0.3 LSB

SFDRafter 78 dBc@

fin = 2 MHz

78 dBc@

fin = 1 up to

100 MHz

58 dBc@

fin = 1 up to

600 MHz

99 dBc@

fin = 12.8 MHz

2nd Order

HDafter - - -

< -100 dBc@

fin = 12.8 MHz

3rd Order

HDafter - - -

< -102 dBc@

fin = 12.8 MHz

IM3 -

< -83dBc@

fin = 1 up to

100MHz

< -80dBc@

fin = 1 up to

600MHz

-

T – thermometer-coded, B – binary, D – dimensional, SG – sort-and-group

References

[1] Y. Cong and R. Geiger, “A 1.5-V 14-bit 100-MS/s Self-calibrated DAC,”

IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2051–2060, Dec. 2003.

[2] T. Chen and G. Gielen, “A 14-bit 200-MHz current-steering DAC with

switching-sequence post-adjustment calibration,” IEEE J. Solid-State

Circuits, vol. 42, no. 11, pp. 2386-2394, Nov. 2007.

[3] W-T. Lin and T-H. Kuo, “ A compact dynamic-performance –improved

current-steering DAC with random rotation-based binary-weighted

selection”, IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 444–453, Feb.

2012.

[4] H. Van de Vel, J. Briaire, C. Bastiaansen, P. van Beek, G. Geelen, Y. Jin,

M. Kaba, K. Luo, E. Paulus, B. Pham, W. Relyveld, P. Zijlstra,”A 240mV

16b 3,2GS/s DAC in 16nm CMOS with <-80dBc IM3 up to 600MHz”,

ISSCC Dig. Tech. Papers, pp. 206-207, Feb. 2014.

[5] G. Raja, and B. Bhaumik, “16-bit Segmented Type Current-steering

DAC for Video Application”, Proceedings of the 19thInternational

Conference on VLSI Design, Hyderabad, India, pp.1-6, January 2006.



- 112 -

[6] C. H. Lin and K. Bult, “A10-b, 500-MSample/s CMOS DAC in 0.6

mm2”, IEEE Journal of Solid-State Circuits, vol.33, no.12, pp.1948-

1958, December 1998.

[7] M-H. Shun, J-H. Tsai, and P-C, Huang,” “Random swapping dynamic

element matching technique for glitch energy minimization in current-

steering DAC”, IEEE Trans. Circuits Syst. Ii, Exp. Briefs, vol. 57, no.5,

pp. 369–373, May. 2010

[8] Y. Tang, J. Briaire, K. Doris, R. van Veldhoven, P. C. W. van Beek, H. J.

A. Hegt, and A. H. M. van Roermaund, “ A 14 bit 200 MS/s DAC with

SFDR >78 dBc across the whole Nyquist band enabled by dynamic-

mismatch mapping”, IEEE J. Solid-State Circuits, vol. 46, no.6, pp.

1371-1380, June. 2011.

[9] A. Van den Bosch, M. Borremans, J. Vandenbussche, G. Van der Plas,

A. Marques, J. Bastos, M. Steyaert, G. Gielen, W. Sansen, “A 12-bit 200

MHz Low Glitch CMOS D/A Converter”, IEEE Custom Integrated

Circuits Conference (CICC), Santa Clara, CA, pp.249-252, May 1998

[10] T. Zeng, D. Chen,” New calibration technique for current-steering

DACs”, IEEE Int. Symposium on Circuits and Syst.,(ISCAS), pp. 573-

576, 2010.

[11] Y. Arakawa, Y. Osawa, H. Kobayashi, O. Kobayashi, “ Linearity

improvement technique of multi-bit sigma-delta TDC for timing

measurement,” IEEE 3rd International Workshop on Test and Validation

of High-Speed Analog Circuits, Anaheim, CA, Sept. 12-13, 2013.

[12] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland,

“Characterization and modeling of mismatch in MOS transistors for

precision analog design:’ IEEE J. Solid-State Circuits, vol. SC-21, pp.

1057–1066, 1986.

[13] http://en.wikipedia.org/wiki/Flash_memory

http://users-tima.imag.fr/rms/stratigopoulos/TVHSAC.html

http://users-tima.imag.fr/rms/stratigopoulos/TVHSAC.html

Chapter 5: Conclusions

- 113 -

Chapter 5

CONCLUSIONS

The effect of random mismatch sourced from current source cells was

studied. The investigation in this study involves current-steering DAC

architectures, error correction techniques and circuit implementation which

reflects in objectives of this study in Chapter 1.

(1) Current-steering DAC architecture

The binary-weighted DAC is the most efficient in terms of DAC

occupied area and power consumption. However, since it is composed

of different weight current sources, this architecture suffers from high

matching requirement. Moreover, due to its switching behavior,

binary-weighted architecture produces large glitch energy. This can be

observed in switching between the MSB bit and all smaller bits where

the worst integral non-linearity is obtained. This means, binary-

weighted is not suitable for high-speed DAC application. On the other

hand, unary-weighted DAC is used in order to obtain smaller INL as

well as glitch energy. However, the die size is increased by the

increment number of bits. Therefore, the combination of these two

architecture called segmented architecture (unary-weighted in upper

bits, MSB while binary-weighted in lower bit, LSB) is used to obtain

better performance.

In this work, the effect of the random mismatch is observed only in

MSB part. Therefore, only the performance of unary-weighted

architecture is presented. As a result, better INL performance is

obtained. For certain application, the higher SFDR is required. This

means, the linearity of DAC transfer function becomes important.

Unary-weighted can provide a small INL but DNL is unchanged which

greatly limits by the matching efficiency. Thus, the half-unary is

introduced in order to provide better INL and DNL with acceptable

matching requirement.


- 114 -

(2) Error correction techniques

Two categories of error correction techniques; without and with error

measurement are reviewed in order to find out the suitable solution

method for reducing the effect of random static error.

As a result, the technique with error measurement technique is chosen in

order to obtain as a maximal error reduction. This is because, by

obtaining the exact information of targeted error, the proper error

elimination can be done compared to without knowing them. Such as

DEM techniques, it can be performed without the exact error information

and suppresses the effect of random static error by averaging over the

time. Eventually, this technique only changes the error into noise floor

and does not eliminate them. Therefore, another problem will occur such

as increment of noise floor and harmonic distortion. In addition, the

glitch problem is also increased.

Here, the effectiveness of technique with the exact error measurement is

investigated and its results are presented. Better linearity and SFDR

performance are obtained.

(3) Circuit implementation

Compared to conventional DAC circuit design technique which is laid

on the component matching properties, the accurate transistor size is

compulsory. This matching requirement becomes difficult to achieve

when the device size decreases. Otherwise, it can be a problem since the

mismatch between components generates error that affects the overall

DAC performance. This error is remained inerasable since there is error

correction feature in designed circuit. However, by using the error

correction technique which is adopted in calibration, the generated error

can be eliminated by applying error correction either every time in

background calibration mode or frequently in foreground calibration

mode. In addition, the matching requirement can be relaxed. This is

because, even the error caused by low matching components combined

with the error that generates after fabrication due to the various process

parameters, the effects of these two errors are still possible to be


- 115 -

compensated.

For high resolution application, the number of current source array is

also increased. Thus, the complexity of the routing and the occupied die

size. By adopting a calibration circuit, the number of current sources can

be reduced. As a result, the complex routing can be avoided.

(4) Future work

As well known, the DAC design covers various parameters in different

design stages in order to provide the best performance with certain

specification depending on the application.

In this study, the investigation is only done in simulation environment

with less parameters. In static specification, INL and DNL performances

are observed in order to validate the linearity of the system. While, SFDR

and 2nd and 3rd order harmonic distortions are carried out as a dynamic

specification parameters to validate the dynamic performance.

In the future, other important parameters such offset error, supply voltage

for the static specification and glitch energy, settling time for dynamic

specification are highly considered.

List of publications

- 116 -


Journal

[1] S. N. Mohyar, M. Murakami, A. Motozawa, H. Kobayashi,

O. Kobayashi, T. Matsuura,”SFDR Improvement Algorithms for

Current-Steering DACs”, Key Engineering Materials, vol. 634,

pp.101-108,2015.

(doi:10.4028/www.scientific.net/KEM. 643.10).

[2] M. Li, Y. Kobori, F. Zhao, Q. Zhu, Z. Nosker, S. Wu,

S. N. Mohyar, H. Kobayashi, N. Takai, “Single-Inductor Dual-

Output DC-DC Converter Design with Exclusive Control”, Key

Engineering Materials, vol. 643, pp.47-52, 2015.

(doi:10.4028/www.scientific.net/KEM.643.47).

International conferences

[1] S. N. Mohyar and H. Kobayashi,” Linearity Improvement

Algorithm for Current Steering DAC Based on 3-Stage Sorting of

Half-Unary Current Sources”, 1st Int. Symp. of Gunma Univ.

Medical Innovation (GUMI) & 6th Int. Conf. on Advanced Micro-

Device Eng. (AMDE2014), Kiryu City Performing Art Center,

(Dec. 5, 2014).

[2] S. N. Mohyar, H. Kobayashi, “Digital Calibration Algorithm for

Half-Unary Current-Steering DAC for Linearity

Improvement”,11th IEEE Int. SoC Design Conference

(ISOCC2014), Jeju, Korea (Nov. 2-6, 2014).

[3] S. N. Mohyar, M. Murakami, H. Kobayashi, O. Kobayashi, T.

Matsuura, N. Takai, I. Shimizu, M. Tsuji, M. Watanabe, N.

Dobashi, R. Shiota, S. Umeda, T. Yamaguchi, “New Digital

Algorithm for Current-Steering DAC SFDR Improvement for

Communication Application” , 5th Int. Conf. on Advanced Micro-

Device Eng. (AMDE2013) Kiryu, Japan (Dec. 19, 2013).

[4] S. N. Mohyar, H. Hassan, M. Murakami, A. Motozawa, H.

Kobayashi, O. Kobayashi, T. Matsuura, N. Takai, I. Shimizu, K.

Niitsu, M. Tsuji, M. Watanabe, N. Dobashi, R. Shiota, S. Umeda,

T. J. Yamaguchi, “SFDR Improvement Algorithms for Current-

Steering DACs,” The 4th IEICE Int. Conf. on Integrated Circuits

Design and Verification (ICDV2013), Ho Chi Minh City, Vietnam

(Nov. 15-16, 2013).


- 117 -

[5] M. Murakami, S. N. Mohyar, H. Kobayashi, T. Matsuura,

O. Kobayashi, M. Tsuji, S. Umeda, R. Shiota, N. Dobashi,

M. Watanabe, I. Shimizu, K. Niitsu, N. Takai and

T. J. Yamaguchi, “Study of Complex Multi-Bandpass ΔΣ

Modulator for I-Q Signal Generation,” The 4th IEICE Int. Conf. on

Integrated Circuits Design and Verification (ICDV2013), Ho Chi

Minh City, Vietnam (Nov. 15-16, 2013)

[6] M. Murakami, S. N. Mohyar, H. Kobayashi, T. Matsuura,

O. Kobayashi, M. Tsuji, S. Umeda, R. Shiota, N. Dobashi,

M. Watanabe, I. Shimizu, K. Niitsu, N. Takai and

T. J. Yamaguchi, “Study of Complex Multi-Bandpass DWA

algorithm for I-Q Signal Generation” 5th Int. Conf. on Advanced

Micro-Device Eng., (AMDE2013) Kiryu, Japan (Dec. 19, 2013)

[7] Z. Yang, Y. Kobayashi, S. N. Mohyar, M. Kazumi, H. Kobayashi,

Gunma University, Japan, “DAC Architecuture with Fibonacci

Sequence Weighted Current Sources”, 5th Int. Conf. on Advanced

Micro-Device Eng., (AMDE2013) Kiryu, Japan (Dec. 19, 2013).

[8] Y. Kobori, L. Quan, S. Wu, S. N. Mohyar, Z. Nosker, N. Tsukiji,

N. Takai and H. Kobayashi, “Electrolytic Capacitor-less

Transformer-less AC-DC LED Driver with Current Ripple

Canceller”, Int. Conf. on Power and Energy Syst. Eng., (ICPESE

2014), Paris, France (Aug 28-29, 2014)

[9] C Li, K Katoh, H Kobayashi, J. Wang, S. Wu, S. N. Mohyar,

“Time-to-Digital Converter Architecture with Residue Arithmetic

and its FPGA Implementation”, 11th IEEE Int. SoC Design

Conference (ISOCC2014), Jeju, Korea (Nov. 2-6, 2014)

[10] R. Wang, S. Tanaka, Y. Kobori, K. Kaneya, S. Wu, S. N. Mohyar,

N. Tsukiji, N. Takai and H. Kobayashi, “Single Inductor Dual

Output Buck Converter with Rippled-Based Serial Control”, 1st

Int. Symp. of Gunma Univ. Medical Innovation (GUMI) & 6th Int.

Conf. on Advanced Micro-Device Eng. (AMDE2014), Kiryu City

Performing Art Center, (Dec. 5, 2014)

[11] Y. Kobori, L. Xing, H. Gao, M. Onozawa, S. Wu, S. N. Mohyar,

Z. Nosker, H. Kobayashi, N. Takai, K. Niitsu, "Non-Isolated

Direct AC-DC Converter Design with BCM-PFC Circuit," Int.

Conf. on Power Eng.,, Bali, Indonesia (Oct. 2012).

[12] Y. Kobori, F. Zhao, Q. Li, M. Li, S. Wu, Z. Nosker,

S N. Mohyar, N. Takai, H. Kobayashi, T. Odaguchi,

I. Nakanishi, K. Ueda, J. Matsuda ,"Single Inductor Dual Output

Switching Converter using Exclusive Control Method", IEEE 4th

Int. Conf. on Power Eng., Energy and Electrical Devices

(POWERENG), Istanbul, Turkey (13-17 May 2013) , pp. 320 –

325 (ISSN:2155-5516).

http://www.el.gunma-u.ac.jp/~kobaweb/news/pdf/2013/Poster_151_KOBORI(final).pdf

http://www.el.gunma-u.ac.jp/~kobaweb/news/pdf/2013/POWEReng2013(Kobori)final.pdf

http://www.el.gunma-u.ac.jp/~kobaweb/news/pdf/2013/POWEReng2013(Kobori)final.pdf

http://www.powereng2013.org/

http://www.powereng2013.org/


- 118 -

[13] K Kato, M. Murakami, F. Abe, Y. Arai, H. Kobayashi, T.

Matsuura, S. N. Mohyar, K, Ramin, O. Kobayashi, K. Niitsu, N.

Takai,“Low-Cost High-Quality Signal Generation for ADC

Testing”, IEEE Int. Test Conference, Anaheim, CA(Nov. 2012).

[14] Y. Kobori, Qiulin Zhu, M. Li, F. Zhao, Z. Nosker, S. Wu,

S. N. Mohyar, M. Onozawa, H. Kobayashi, N. Takai, Kiichi

Niitsu, T. Odaguchi, I. Nakanishi, K. Nemoto, J. Matsuda,“Single

Inductor Dual Output DC-DC Converter Design with Exclusive

Control”,IEEE Asia Pacific Conference on Circuits and Systems,

(APCCAS), Kaohsiung Taiwan (Dec. 2012) pp. 436-439 (ISBN:

978-1-4577-1728-4).

Domestic conferences/seminar

[1] S. N. Mohyar, H. Kobayashi,” 3-Stage Current Sorting Algorithm

for Current-Steering DAC Linearity Improvement” IEEJ

Electronic Circuits Seminar (Japanese), Akita Univ. (Tegata

Campus), (Oct. 9-10, 2014).

[2] S. N. Mohyar, H. Kobayashi,“New digital algorithm for current-

steering DAC SFDR Improvement,”36th Analog RF

Seminar(Japanese), Yakushima, Kagoshima (July 16-18, 2014)

[3] S. N. Mohyar, H. Kobayashi, “Digital Calibration for Current-

Steering DAC Linearity Enhancement”, 57th LSI Joint Seminar

(Japanese), Tokyo Inst. of Tech. Univ. (Ookayama Campus)

(June, 28, 2014).

[4] S. N. Mohyar, H. Kobayashi, ”DAC Architecture Comparison for

SFDR Performance”,4th IEEJ Seminar (Japanese), Tochigi-

Gunma Branch, Gunma Univ. (Kiryu Campus), (Mar. 3-4, 2014),

ETT-14-53, ETG-14-53.

[5] S. N. Mohyar，M. Murakami, H. Kobayashi, , T. Matsuura, O.

Kobayashi, “A Study of a Complex Multi-Band Pass ΔΣ D/A

Modulator for I,Q signal generation”, 3rd IEEJ Seminar

(Japanese), Tochigi-Gunma Branch, Utsunomiya Univ., (Feb. 28-

Mar. 1, 2013) ETT-12-37, ETG-12-37.

[6] 村上正紘，S. N. Mohyar，小林春夫，松浦達治（群馬大学），

小林修（STARC）、「通信用 IC テスト用 I, Q信号発生の

ための複素マルチバンドパス ΔΣDA変調器の検討(2)」、第

3 回電気学会東京支部栃木・群馬支所合同研究発表会,宇都

宮大学(2013 年 2 月 28 日（木）, 3 月 1 日（金）), ETT-12-

38, ETG-12-38.


- 119 -

[7] 村上正紘、S. N. Mohyar、小林春夫、松浦達治、小林修、高

井伸和、”通信用 IC テスト用 I, Q 信号発生のための複素ル

チバンドパス ΔΣDA変調器の検討、”電気学会,電子・情報・

システム部門大会, 企画セッション（複素信号処理とアナ

ログ複素係数フィルタ）北見工業大学、（２０１３年９月

５日）.

[8] 須釜裕太、S. N. Mohyar, Khatami S. Ramin, 新津葵一、小林

春夫、高井伸和「増幅器の出力遅延時間を利用した微小信

号電位差・電流差検出回路」, 第６７回ＦＴＣ研究会、滋賀

県大津市, (2012年 7月 12 日).

[9] 村上正紘、新井薫子、S. N. Mohyar、安部文隆、加藤啓

介、小林春夫、松浦達治、小林修、新津葵一、高井伸

和,「任意波形発生器を用いたノイズシェーピング技術」,電

気学会電子回路研究会, ECT-12-085, 熊本, (2012 年 10 月

5日).

[10] 楊志翔*, 小林佑太朗, S. N. Mohyar, 小林春夫（群馬大学）、

「フィボナッチ数列を用いたＤＡ変換回路アーキテクチャ」、

第４回電気学会東京支部栃木・群馬支所合同研究発表

会, 群馬大学理工学部、（桐生キャンパス）2014 年 3月 3日

（月）, 3月４日（火）,ETT-14-82, ETG-14-82.

[11] 小堀康功、李慕容、呉ジュ、趙峰、権力、S. N. Mohyar、小

田口貴宏、中西功、根本謙治、松田順一、高井伸和小林春

夫、「疑似デルタシグマ変調単インダクタ 2 出力 SIDO 降

圧形スイッチング電源」、電子情報通信学会, 回路とシステ

ム研究会、大分、（２０１３年１月２９日）.

[12] 趙峰*，小堀康功，李慕容，呉ジュ，権力，朱秋霖，S.

N. Mohyar，小田口貴宏，山口哲二，上田公大（AKM テク

ノロジ），松田順一（旭化成パワーデバイス），高井伸和，

小林春夫（群馬大学），「排他的制御を用いた単一インダ

クタ２出力 DC-DC スイッチング電源の実験検証」、第 3回

電気学会東京支部栃木・群馬支所合同研究発表会,宇都宮大

学工学部、(2013年 2月 28 日（木）, 3月 1日（金）), ETT-

12-26, ETG-12-26.


- 120 -

[13] S. Wu, Y. Kobori, M. Li, Z. Feng, Q. Zhu, S. N. Mohyar, T.

Odaguchi, T. Yamaguchi, I. Nakanishi, K. Ueda, J. Matsuda, N.

Takai, H. Kobayashi, “Single Inductor Dual Output DC-DC Boost

converter with Serial Control,” 電子情報通信学会集積回路

研究会（ICD）, 東京工業大学, (2012年 12月 17日, 18日).

[14] 小堀康功 , 朱秋霖 , 田中駿祐 , 呉ジュ、築地伸和、S. N.

Mohyar、高井伸和、小林春夫「リプルレギュレータ方式に

よる単インダクタ 2 出力 DC-DC 電源」電子情報通信学会,

回路とシステム研究会、北海道大学（2014年 7月 9 日ー11

日）.

[15] 小堀康功, 李慕容, 呉ジュ（Wu Shu),趙峰, S. N. Mohyar, 小

田口貴宏, 中西功, 根本謙治、松田順一, 高井伸和, 新津

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スイッチング電源」、電気学会電子回路研究会, ECT-12-100,

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Digital Algorithms for Linearity Improvement of Current ... would like to thank my review committee members, Professors, Dr. Kuniyuki MOTOJIMA, Dr. Sadao ADACHI, Dr. Yasunori KOBORI

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