Digilab 2E digilent, inc.tylee/Courses/FPGA... · Digilab 2E FPGA Development Board The Digilab 2E (D2E) FPGA-based development board makes an excellent prototyping platform for moderate

Digilab 2E FPGA Development Board

The Digilab 2E (D2E) FPGA-based development board makes an excellent prototyping platform for moderate to complex digital circuits and systems. The D2E board features a 200K-gate Xilinx Spartan 2E XC2S200E FPGA in a PQ208 package that provides 143 user I/Os. All available I/O signals are routed either to the expansion connectors, or to the ports and other on-board devices. A single on-board pushbutton and LED allow for quick circuit and device programming checks, as well as basic I/O (e.g., for reset and status). The D2E board mates with several existing peripheral boards so that entire digital systems can be quickly and easily constructed. The D2E board works seamlessly with the free WebPack CAD tools, and it ships with a programming cable and power supply, so projects can be implemented immediately, without the need for any other components or expenses. D2E board features include: • A Xilinx XC2S200E FPGA in a PQ208

package offering 143 user I/O signals; • Dual on-board 1.5A power regulators (3.3V

and 1.8V); • A socketed 50MHz oscillator; • A socket for a Xilinx SPROM; • EPP-capable parallel port for JTAG-based

FPGA programming and user data transfers; • A separate JTAG header for use with Xilinx

parallel 3 or parallel 4 programming cables; • 5-wire RS-232 serial port; • Status LED and pushbutton for basic I/O; • 6 100-mil spaced, right angle DIP socket 40-

pin expansion connectors. For more information, please see the Digilab 2E reference documents available at the Digilent website.

Digilab 2E (D2E) Development Board

50MHzCLK

Xilinx Spartan2EXC2S200E-PQ208

Powerjack

5-9VDC

2.5VDCregulator

StatusLED

Expansion E Expansion F

Exp

ansi

on C

Exp

ansi

on D

Seri

al P

ort

Para

llel P

ort

Port/progcontrolswitch

Expansion A Expansion B

EPP or SPPparallel port

JTAGPort

SerialPort

Pushbutton

Buf

fer

RS-

232

conv

erte

r

SPROM

3.3VDCregulator

D2E Block Diagram

digilent, inc.Design Resources for Digital Engineers

www.digilentinc.com

DDiiggiilleenntt 22EE SSyysstteemm BBooaarrdd RReeffeerreennccee MMaannuuaall

www.dig i lent inc.com

Revision: March 24, 2004 246 East Main | Pullman, WA 99163 (509) 334 6306 Voice and Fax

Copyright Digilent, Inc. All rights reserved Document: 502-008

Digilab 2E Reference Manual Overview The Digilab 2E (D2E) development board featuring the Xilinx Spartan 2E XC2S200E FPGA provides an inexpensive and expandable platform on which to design and implement digital circuits of all kinds. D2E board features include:

• A Xilinx XC2S200E FPGA; • Dual on-board 1.5A power regulators

(2.5V and 3.3V); • A socketed 50MHz oscillator; • An EPP-capable parallel port for JTAG-

based FPGA programming and user data transfers;

• A 5-wire Rs-232 serial port; • A status LED and pushbutton for basic

I/O; • Six 100-mil spaced, right-angle DIP

socket 40-pin expansion connectors. The D2E board has been designed specifically to work with the Xilinx ISE CAD tools, including the free WebPack tools available from the Xilinx website. Like other Spartan 2 boards in the Digilab family, the D2E board has been partitioned so that only the hardware required by a particular project need be purchased. Several existing peripheral boards

that mate with the expansion connectors are currently available (see www.digilentinc.com), and new boards are frequently added. The low-cost, standard expansion connectors allow new peripheral boards, including wire-wrap or manually soldered boards, to be quickly designed and used. The D2E board ships with a power supply and programming cable, so designs can be implemented immediately without the need for any additional hardware.

50MHzCLK

Xilinx Spartan2EXC2S200E-PQ208

Powerjack

5-9VDC

2.5VDCregulator

StatusLED

Expansion E Expansion F

Exp

ansi

on C

Exp

ansi

on D

Seri

al P

ort

Para

llel

Por

t

Port/progcontrolswitch

Expansion A Expansion B

EPP or SPPparallel port

JTAGPort

SerialPort

Pushbutton

Buf

fer

RS-

232

conv

erte

r

SPROM

3.3VDCregulator

D2E circuit board block diagram

PRELIMINARY

Digilent 2E Reference Manual Digilent, Inc.

Rev: Apr 14, 2002 www.digilentinc.com Page 2 of 10

Functional description The Digilab D2E board has been designed to offer a low-cost and minimal system for designers who need a flexible platform to gain exposure to the Spartan 2E device, or for those who need to prototype FPGA-based designs rapidly. The D2E board provides only the essential supporting devices for the Spartan 2E, and routes all available FPGA signals to standard expansion connectors. Included on the board are 2.5VDC and 3.3VDC regulators, a JTAG configuration circuit that uses a standard parallel cable, basic communication ports including an enhanced parallel port and 5-wire serial port, a 50MHz oscillator, and a pushbutton and LED for rudimentary I/O. The D2E board has been designed to serve as a host for various peripheral boards. The expansion connectors on the D2E board mate with standard 40-pin, 100 mil spaced DIP headers available from any catalog distributor. Expansion connectors provide the unregulated supply voltage (VU), 3.3V, GND, and 37 FPGA signals to peripheral boards, so system designers can quickly develop application- specific peripheral boards. Digilent also produces a collection of expansion boards with commonly used devices. See the Digilent website (www.digilentinc.com) for a listing of currently available boards. Table 1 shows all signals routed on the D2E board. These signals, and the circuits that they connect to, are described in the following sections. Parallel port and FPGA configuration circuit The Digilab 2E board uses a DB-25 parallel port connector to route JTAG programming signals from a host computer to the FPGA. This same connector also routes the computer’s parallel port pins to the FPGA following the EPP port definition contained in the IEEE 1284 standard. A three-state buffer, controlled by a switch, determines whether the JTAG port or EPP port is enabled. With this circuit, the

Power Supplies VU Unregulated power supply voltage – depends on power supply

used. Must be between 5VDC and 10VDC. Routed to regulators and expansion connectors only.

VDD33 FPGA VCCO and VCC for all other devices, routed on PCB plane. 1.5A can be drawn with less than 20mV ripple (typical)

VDD25 FPGA VCCINT routed on PCB plane GND System ground routed to all devices on PCB ground plane Programming and parallel port PWE EPP mode write enable signal (in to FPGA) PD0-PD7 Bi-directional data signals PINT Interrupt signal (out from FPGA) PWT EPP mode wait signal (out from FPGA) PDS EPP mode data strobe (in to FPGA) PRS Reset signal (in to FPGA) PAS EPP mode address strobe (in to FPGA) Serial port RXD Serial port receive data (in to FPGA) TXD Serial port send data (out from FPGA) DSR Serial port data set ready (out from FPGA) CTS Serial port clear to send (out from FPGA) RST Serial port request to send (in to FPGA) On board devices BTN1 User-controllable pushbutton input LED1 User-controllable status LED CLK1 CMOS oscillator connected to GCLK0 Expansion Connectors A4-A40 A bus signals connecting the A & E connectors to the FPGA B4-B14 B bus signals connecting the B & F connectors to the FPGA C4-C40 C bus signals connecting the C connector to the FPGA D4-D40 D bus signals connecting the D connector to the FPGA

Table 1. D2E board signal definitions



FPGA can be configured using the JTAG protocol over the parallel cable. The same cable can then be used (after the switch is repositioned) to move data between the board and the host computer using the high-speed EPP protocol. A separate JTAG header is also provided so that a dedicated programming cable (like the Xilinx Parallel III cable) can be used. The JTAG programming circuit follows the JTAG schematic available from Xilinx, so that the Digilab 2E board is fully compatible with all Xilinx programming tools. The EPP parallel port circuit follows the guidelines in the IEEE 1284 specification, and data rates approaching 2Mbytes/second can be achieved. JTAG and EPP connections are shown in the diagrams below.

Figure 1. Parallel port connectors and signals

The D2E board directly supports JTAG and SPROM configuration. Hardware debugger configuration is supported indirectly. To configure the board from a computer using the JTAG mode, set switch 1 (SW1) in the JTAG position, and attach a power supply and programming cable. The power supply must be connected before the parallel cable, or the board may hang in a non-communicating state. The board will be auto-detected by the Xilinx JTAG programming software, and all normal JTAG operations will be available. To configure the FPGA from an SPROM, load the programmed SPROM into the 8-pin ROM socket (labeled IC6), place SW1 in the PORT position, add jumpers to all mode pins, and apply power. To configure the board using the hardware debugger protocol, a slight board modification is required – a jumper wire must be soldered to the non-VCC side of R45. Insert wire-wrap posts into the SPROM socket, attach the hardware debugger signals to the appropriate posts, and attach the PROG signal to the jumper wire attached to R45. The hardware debugger programming software will now automatically recognize the board, and hardware debugger programming can proceed as normal. Programming circuit detail is shown below. Note that all parallel port signals are routed to the test header J12 for easy connection of test and measurement equipment.

Pin 1

Pin 25

Top view of hole pattern, withcable attaching from this side

Pin EPP signal EPP Function

1 Write Enable (O) Low for read, High for write 2-9 Data bus (B) Bidirectional data lines 10 Interrupt (I) Interrupt/acknowledge input 11 Wait (I) Bus handshake; low to ack 12 Spare NOT CONNECTED 13 Spare NOT CONNECTED 14 Data Strobe (O) Low when data valid

15 Spare NOT CONNECTED 16 Reset (O) Low to reset 17 Address strobe (O) Low when address valid 18-25 GND System ground

Pin 13 Pin 1

Pin 14Pin 25

DB25 parallel port connectorFront view



1 142 153 164 175 186 197 208 219 2210 2311 2412 2513

GND

Data 2 (PD2)

Data 1 (PD1)

Data 0 (PD0)

Data 3 (PD3)

Data 4 (PD4)

Data 5 (PD5)

Data 6 (PD6)

Data 7 (PD7)

Write Enable (PWE)

Interrupt (PINT)

Data Strobe (PDS)

Reset (PRST)

Address Strobe (PAS)

Wait (PWT)

CCLK

DONEDATA IN

INIT

VDD SENSECABLE DET1CABLE DET2

Decoupingthree-statebuffer

GND

Vdd

DB25connector

Program enableswitch (SW1)

JTAG

PORT

Enable

TMS

TCLKTDI

TDO

Pull-up resistors are used on all parallelport signals. They are not shown here.

XilinxSpartan 2EPQ208

P206P205P15

P11P203P10P204P9

P8

P7

P6

P5

P4

P3 P2

P207P159

P157

SPROM

Pull-ups on INIT andDONE not shown

8-DIP

P107P155P153P104

M0M1M2

Jumperblock

Figure 2. Parallel port and programming circuit schematic Serial Port The D2E serial port uses a Maxim MAX3386E RS-232 voltage converter to generate the required RS-232 voltages. Five signals are connected through the RS-232 converter, allowing for partial hardware handshaking. The serial port pin definitions and circuit are shown below. The serial port is provided in part to support the Xilinx MicroBlaze embedded RSIC processor core available from the Xilinx website. The two devices connected to either end of a serial cable are known as the Data Terminal Equipment (DTE) and the Data Communications Equipment (DCE). The DCE was originally conceived to be a modem, but now many devices connect to a computer as a DCE. A DTE device uses a male DB-9 connector, and a DCE device uses a female DB-9 connector. The DTE is considered the source of data, and the DCE the peripheral device. Two DTE devices can be connected via a serial cable only if lines



two and three are crossed – this is known as a null modem cable. A DTE and DCE device can be connected with a straight-through cable. The Digilab 2E board is configured as a DCE device.

DB9 top-downhole pattern; cable

attaches from this side

Pin 1

Pin 6Pin 9

Pin 5

DB9 serial port connectorFront view

Pin 1Pin 9

1 62 73 84 95

GND

MaximMAX3386ERS232 VoltageConverter

RXD

TXD

16

DB9Connector

RTS

CTS

Serial Port Pin Definitions

Pin # Name Function Direction Connected

1 DCD Data carrier detect DCE DTE N 2 RXD Received data DCE DTE Y 3 TXD Transmitted data DCE DTE Y 4 DTR Data terminal ready DCE DTE N 5 SG Signal ground Y 6 DSR Data set ready DCE DTE Y 7 RTS Request to send DCE DTE Y 8 CTS Clear to send DCE DTE Y 9 RI Ring Indicator DCE DTE N


DSR

1713

1415

87

1011

9

P200P201P198P202P199

Figure 3. Serial port circuit schematic Oscillator The Digilab 2E uses a socketed half-size 8-pin DIP oscillator. The board ships with a 50MHz oscillator, allowing for system clocks from virtually DC to 200MHz (using the Spartan 2E DLL circuit and/or clock counter-dividers). Oscillators from 32KHz to 100MHz can easily be substituted, allowing for a wide range of clock frequencies. The oscillator, which is connected to the FPGA GCK0 input (P80), is bypassed with a 0.1uF capacitor and it is located as physically close to the FPGA as possible (trace length is about 10mm). Power Supplies The Digilab 2E board uses two LM317 1.5A voltage regulators to produce 2.5VDC and 3.3VDC supplies. The regulator inputs are driven from an external DC power supply connected to the on-board 2.1mm center-positive power jack. The regulators have 10uF of input capacitance, 20uF of local output capacitance, and 10uF of regulation bypass capacitance. This allows the regulators to produce stable, low noise supplies using inexpensive power supplies, regardless of load (up to 1.5A). The regulator



bodies are soldered to the board for improved thermal dissipation. DC supplies in the range of 5VDC to 10VDC may be used. The Digilab 2E board uses a four layer PCB, with the inner layers dedicated to VCC and GND planes. Most of the VCC plane is at 3.3V, with an island under the FPGA at 2.5V. The FPGA and the other ICs on the board all have 0.1uF bypass capacitors placed as close as possible to the VCC pins. Total board current is dependant on FPGA configuration, clock frequency, and external connections. In test circuits with roughly 50K gates routed, a 50MHz clock source, and a single expansion board attached (the DIO2 board), approximately 200mA +/- 30% of supply current is drawn from the 2.5V supply, and approximately 150mA +/- 50% is drawn from the 3.3V supply. These currents are strongly dependent on FPGA and peripheral board configurations. All FPGA VCCO pins are connected to the 3.3V supply. If other VCCO voltages are required, please contact Digilent for information regarding various options (Digilent can be contacted through www.digilentinc.com). Expansion connectors

The six expansion connectors labeled A-F use 100 mil spaced DIP headers. All six connectors have GND routed to pin 1, VU routed to pin 2, and 3.3V routed to pin 3. Pins 4-40 all route directly to the FPGA. The connectors are organized in pairs, with the A & B, C& D, and E & F pairs placed on the same board edge. Connectors A & B and E & F are routed in parallel, with pairs A & E and B & F sharing identical pin connections to the FPGA. Connectors C & D have all pins routed to separate FPGA pins. All connector pairs are separated by 400 mils, so any peripheral board can be placed in any connector (or pair of connectors). The PQ208 package used on the D2E board allows 122 signals to be routed to the expansion connectors (the remaining 21 available signals are routed to the parallel and serial connectors). Connectors C and D are closest to the FPGA, and all C and D pins are connected to the closest available FPGA pins with the shortest possible route. Thus, the 74 FPGA signals routed to the C & D connectors will exhibit the least amount of signal delay, and data rates of up to 100MHz are attainable. The A & E connectors also

A B

C

D

F E

37

37

37

11 Spartan 2EPQ208

DB

-25

DB

-9

Figure 4. Expansion connector detail

Pin 1: GND

Pin 2: VU

Pin 3: 3.3VPin 39

Pin 40Pin 4

Pin 39

Pin 40



route 37 FPGA signals, but with less favorable routes. Only 11 FPGA signals were left to route to the B & F connectors, so 26 pins on those connectors are not connected. Connector pin definitions follow.



Table 2. Digilab 2E Expansion Connector pinouts

A&E connector B&F connector C connector D connector

Pin Signal S-II pin Pin Signal S-II pin Pin Signal S-II pin Pin Signal S-II pin

1 GND - 1 GND - 1 GND - 1 GND -

2 VU - 2 VU - 2 VU - 2 VU -

3 VDD33 - 3 VDD33 - 3 VDD33 - 3 VDD33 -

4 A4 68 4 B4 194 4 C4 179 4 D4 125

5 A5 64 5 B5 193 5 C5 178 5 D5 122

6 A6 63 6 B6 192 6 C6 176 6 D6 123

7 A7 62 7 B7 191 7 C7 175 7 D7 120

8 A8 61 8 B8 189 8 C8 174 8 D8 121

9 A9 60 9 B9 188 9 C9 173 9 D9 115

10 A10 59 10 B10 187 10 C10 169 10 D10 116

11 A11 58 11 B11 185* 11 C11 168 11 D11 113

12 A12 57 12 B12 182* 12 C12 167 12 D12 114

13 A13 56 13 B13 181 13 C13 166 13 D13 111

14 A14 55 14 B14 180 14 C14 165 14 D14 112

15 A15 49 15 B15 - 15 C15 164 15 D15 109

16 A16 48 16 B16 - 16 C16 163 16 D16 110

17 A17 47 17 B17 - 17 C17 162 17 D17 102

18 A18 46 18 NC - 18 C18 161 18 D18 108

19 A19 45 19 NC - 19 C19 160 19 D19 100

20 A20 44 20 NC - 20 C20 154 20 D20 101

21 A21 43 21 NC - 21 C21 152 21 D21 98

22 A22 42 22 NC - 22 C22 151 22 D22 99

23 A23 41 23 NC - 23 C23 150 23 D23 96

24 A24 40 24 NC - 24 C24 149 24 D24 97

25 A25 36 25 NC - 25 C25 148 25 D25 94

26 A26 35 26 NC - 26 C26 147 26 D26 95

27 A27 34 27 NC - 27 C27 146 27 D27 89

28 A28 33 28 NC - 28 C28 145 28 D28 93

29 A29 31 29 NC - 29 C29 141 29 D29 87

30 A30 30 30 NC - 30 C30 140 30 D30 88

31 A31 29 31 NC - 31 C31 139 31 D31 84

32 A32 27 32 NC - 32 C32 138 32 D32 86

33 A33 24 33 NC - 33 C33 136 33 D33 82

34 A34 23 34 NC - 34 C34 135 34 D34 83

35 A35 22 35 NC - 35 C35 134 35 D35 75

36 A36 21 36 NC - 36 C36 133 36 D36 81

37 A37 20 37 NC - 37 C37 132 37 D37 73

38 A38 18 38 NC - 38 C38 129 38 D38 74

39 A39 17 39 NC - 39 C39 127 39 D39 70

40 A40 16 40 NC - 40 C40 126 40 D40 71 * uses GCLK pin



Pushbutton and LED A single pushbutton and LED are provided on the board allowing basic status and control functions to be implemented without a peripheral board. As examples, the LED can be illuminated from a signal in the FPGA to verify that configuration has been successful, and the pushbutton can be used to provide a basic reset function independent of other inputs. The circuits are shown below.


P77

P69

Vdd

4.7K

4.7K

Pushbutton

80 Ohm

Figure 5. Pushbutton and LED detail Spartan 2E FPGA The block diagram of the Digilab 2E board shows all connections between the FPGA and the devices on the board. All FPGA pin connections are shown in the following table. The Spartan device can be configured using the Xilinx JTAG tools and a parallel cable connecting the D2E board and the host computer. Note that a separate JTAG header that connects directly to the JTAG pins is also provided. For further information on the Spartan FPGA, please see the Xilinx data sheets available at the Xilinx website (www.xilinx.com).

Expansion E

DB-25 parallel port DB-9 serial port

LED

Pushbutton

Clock

SPROM

JTAG

Expansion A

Expansion F

Expansion B Expansion C

Expansion D

37 3737

11

5 413

4

Spartan 2E PQ208

Figure 6. Spartan 2E connection detail



Table 3. Digilab 2E board Spartan 2E FPGA pinout

Pin # Function Pin # Function Pin # Function Pin # Function

1 GND 53 VCCO 105 VCCO 157 TDO 2 TMS 54 M2 106 PROG 158 GND 3 PWT 55 A14 107 INIT 159 TDI 4 PINT 56 A13 108 D18 160 C19 5 PD7 57 A12 109 D15 161 C18 6 PD6 58 A11 110 D16 162 C17 7 PD5 59 A10 111 D13 163 C16 8 PD4 60 A9 112 D14 164 C15 9 PD3 61 A8 113 D12 165 C14 10 PD2 62 A7 114 D14 166 C13 11 PD1 63 A6 115 D9 167 C12 12 GND 64 A5 116 D10 168 C11 13 VCCO 65 GND 117 GND 169 C10 14 VCCINT 66 VCCO 118 VCCO 170 GND 15 PD0 67 VCCINT 119 VCCINT 171 VCCO 16 A40 68 A4 120 D7 172 VCCINT 17 A39 69 LED1 121 D8 173 C9 18 A38 70 D39 122 D5 174 C8 19 GND 71 D40 123 D6 175 C7 20 A37 72 GND 124 GND 176 C6 21 A36 73 D37 125 D4 177 GND 22 A35 74 D38 126 C40 178 C5 23 A34 75 D35 127 C39 179 C4 24 A33 76 VCCINT 128 VCCINT 180 B14 25 GND 77 BTN1* 129 C38 181 B13 26 VCCO 78 VCCO 130 VCCO 182 B12* 27 A32 79 GND 131 GND 183 GND 28 VCCINT 80 CLK1* 132 C37 184 VCCO 29 A31 81 D36 133 C36 185 B11* 30 A30 82 D33 134 C35 186 VCCINT 31 A29 83 D34 135 C34 187 B10 32 GND 84 D31 136 C33 188 B9 33 A28 85 GND 137 GND 189 B8 34 A27 86 D32 138 C32 190 GND 35 A26 87 D29 139 C31 191 B7 36 A25 88 D30 140 C30 192 B6 37 VCCINT 89 D27 141 C29 193 B5 38 VCCO 90 VCCINT 142 VCCINT 194 B4 39 GND 91 VCCO 143 VCCO 195 VCCINT 40 A24 92 GND 144 GND 196 VCCO 41 A23 93 D28 145 C28 197 GND 42 A22 94 D25 146 C27 198 RTS 43 A21 95 D26 147 C26 199 CTS 44 A20 96 D23 148 C25 200 DSR 45 A19 97 D24 149 C24 201 TXD 46 A18 98 D21 150 C23 202 RXD 47 A17 99 D22 151 C22 203 PRS 48 A16 100 D19 152 C21 204 PAS 49 A15 101 D20 153 DIN 205 PDS 50 M1 102 D17 154 C20 206 PWE 51 GND 103 GND 155 CCLK 207 TCK 52 MO 104 DONE 156 VCCO 208 VCCO

* uses GCLK pin

Digilab Digital I/O 1 Peripheral Board

The Digilab Digital I/O Board 1 (DIO1) provides a ready-made source for I/O devices and ports commonly used in digital systems. The DIO1 board can be used with any Digilab system board to create a platform that can host a wide range of projects. Many projects can be implemented immediately without the need for any other components; if further custom circuits are needed, a Digilab breadboard or wirewrap board can be inserted between a system board and DIO1 board. All devices on the DIO1 board are driven directly from an attached system board, keeping system designs as simple as possible. DIO1 board features include: • A 4 digit, seven-segment LED display; • 8 individual LEDs; • 4 momentary pushbuttons; • 8 slide switches; • 3-bit VGA port; • PS2 mouse/keyboard port.

For more information, please see the Digilab DIO1 reference documents available at our website.

Digilab DIO1 Peripheral Board

8 LEDs

4 displays 8 switches

PS2port

Connector B

25

4 buttons

74HC373Latch

Connector A

12

4

8

9

VG

A P

ort

DIO1 Block Diagram

digilent, inc.Design Resources for Digital Engineers

www.digilentinc.com

DDiiggiilleenntt DDIIOO11 MMaannuuaall

TM

www.digi lent inc.com Revision: May 10, 2004 246 East Main | Pullman, WA 99163

(509) 334 6306 Voice and Fax

© Digilent, Inc. 10 pages Doc: 502-009

Overview The Digital I/O board 1 (DIO1) is one of several expansion boards designed to mate with Digilent system boards. The DIO1 is an inexpensive board that contains an assortment of basic digital I/O devices, including buttons, switches, and several LED displays. The DIO1 board can be combined with Digilab system boards to provide a source of ready-made I/O devices, allowing a wide range of projects to be implemented without the need for any other components. DIO1 board features include:

• A four digit seven-segment LED display; • 8 individual LEDs; • A 3-bit VGA port; • 5 momentary pushbuttons; • 8 slide switches; • A PS2 mouse/keyboard port.

Functional description The DIO1 board has been designed to provide a basic, inexpensive platform that contains many of the I/O devices commonly found in digital systems. Unlike the more advanced DIO2 board, the DIO1 board has been designed so that all signals pass directly to an attached system board, so no intermediate logic is required. When mated with a Digilab system board, the DIO1 board can provide a flexible prototyping system that can be operational immediately.

LEDs Eight LEDs are provided for circuit outputs. The LED cathodes are tied to ground via 270-ohm resistors, and the anodes are driven from the 74HC373 (so the LED drive signals are active high).

Figure 2. LED Circuit

Signals All named signals used on the DIO1 board are defined in the Table 1. Voltage levels for all

8 LEDs

4 displays 8 switches

PS2port

Connector B

25

5 buttons

74HC373Latch

Connector A

125

8

9

VG

A P

ort

Figure 1. DIO1 schematic

LD signals

GND

LD1- LD8

RP1270 Ohm

DIO1 Reference Manual Digilent, Inc.

www.digilentinc.com Copyright Digilent, Inc. Page 2

signals arriving from an attached Digilab system board are determined by the system board, but all signals arising on the I/O board derive from the on-board 5VDC regulator (so they are all 5V CMOS signals). The DIO1 board uses a two-layer process, so all signals are available on the top and bottom layers. Many signals are brought to a test point header for easy test and measurement equipment attachment. Power Supply The DIO1 board receives system power from pins 39 and 37 of connectors A and B (which mate to pins 1 and 3 of an attached system boards). Pin 37 provides Vdd from the attached system board (assumed to be 3.3VDC), and pin 39 is connected to ground. Up to 5VDC can be safely applied to the Vdd input pin (pin 37). The DIO1 board typically consumes less than 10mA with no LED’s illuminated, and up to 130mA with all LEDs illuminated (including all segments of the seven-segment display). Seven-segment LED display The DIO1 board contains a modular 4-digit, common anode, seven-segment LED display. In a common anode display, the seven anodes of the LEDs forming each digit are connected to four common circuit nodes (labeled AN1 through AN4 on the DIO1 board). Each anode, and therefore each digit, can be independently turned on and off by driving these signals to a ‘1’ or a ‘0’. The cathodes of similar segments on all four displays are also connected together into seven common circuit nodes labeled CA through CG. Thus, each cathode for all four displays can be turned on and off independently.

This connection scheme creates a multiplexed display, where driving the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession can create a 4-digit display. In order for each of the four digits to appear bright and continuously illuminated, all four digits should be driven once every 1 to 16ms (for a refresh frequency of 60Hz to 1KHz). For example, in a 60Hz refresh scheme, each digit would be illuminated for ¼ of the refresh cycle, or 4ms. The controller must assure that the correct cathode pattern is present when the corresponding anode signal is driven. To illustrate the process, if AN1 is driven high while CB and CC are driven low, then a “1” will be displayed in digit position 2. Then, if AN2 is driven high while CA, CB and CC are driven low, then a “7” will be displayed in digit position 2. If AN1/CB, CC are driven for 4ms, and then AN2/CA, CB, CC

Power Supplies VU Unregulated power supply voltage from

attached system board – typically 5-9VDC. Although connected to the board, this supply is not used on the DIO1 board.

VDD33 Regulated power supply voltage (3.3VDC) from attached system board. All devices on DIO1 board use this supply.

GND System ground VGA signals HS VGA Horizontal Sync signal VS VGA Vertical Sync signal R VGA 1-bit red data G VGA 1-bit green data B VGA 1-bit blue data PS2 signals KCLK PS2 (Keyboard or Mouse) clock signal KDAT PS2 (Keyboard or Mouse) data signal Input devices BTN1-4 Pushbuttons 1 through 4 SW1-

SW8 Slide switches 1 through 8

Output devices LD0-LD8 Discreet LEDs 1 through 8 CA-CF Seven-segment display cathodes AN1-

AN3 Seven-segment display anodes

Table 1. DIO1 board signal definitions



are driven for 4ms in an endless succession, the display will show “17” in the first two digits. An example timing diagram is provided to the right.

.

Push Buttons Outputs from the 4 momentary-contact push buttons are normally low, and are driven high only while the button is actively pressed. The buttons exhibit a worst-case bounce time of about 1ms. A 74HC14 Hex Schmidt Trigger inverter provides the debounce filtering and ESD protection. The button outputs are brought out directly to pins on interface connector B.

a1

Cathodes -- connected toCPLD pins via 100Ω resistor

Anodes -- connected to CPLDvia transistors for greater current

Vdd

a b c d e f g dp

a2a3a4

AN1

AN2

AN3

AN4

Cathodes Digit 1 Digit 2 Digit 3 Digit 4

Refresh period = 1ms to 16ms

Digit period = Refresh / 4

Seven segment display refresh signals and timings

Figure 3. (a) Seven segment display detail. (b) common anode display configuration. (c) segement illumination patterns for decimal digits. (d) segment illumination truth table.

Common anode

a

f

e

d

c

bg

a f g e d c b(a) (b)

(c)

Digit Illuminated SegmentShown a b c d e f g

0 1 2 3 4 5 6 7 8 9

(d)

Vdd

GND

RP8&94.7KOhm

Vdd

ToConnector

Administrator

打字機文字

0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0



Switches The eight slide switches can be used to connect either Vdd or GND to eight pins on interface connecter B. The switches exhibit about 2ms of bounce, and no active debouncing circuit is employed. A 4.7K-ohm series resistor is used for nominal input protection. PS2 port The DIO1 board includes a 6-pin mini-DIN connector that can accommodate a PS2 mouse or PS2 keyboard connection. Both the mouse and keyboard use a two-wire serial bus (including clock and data) to communicate with a host device, and both drive the bus with identical signal timings. Both use 11-bit words that include a start, stop and odd parity bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown below. The clock and data signals are only driven when data transfers occur, and otherwise they are held in the “idle”

state at logic ‘1’. The timings define signal requirements for mouse-to-host communications and bi-directional keyboard communications.

PS2 Connector front view

Pin 1

Pin 5Pin 6

Bottom-uphole pattern

PS2 Pin Definitions

Pin Function 1 Data 2 Reserved 3 GND 4 Vdd 5 Clock 6 Reserved

1

53

24

6

GND

Vdd

ToConnector

RP6 & 74.7 KOhm

TCK

TSU

Edge 0 Edge 10

CLK

DATA

TCK

TSU

Clock timeData-to-clock setup time

30us5us

50us25us

Symbol Parameter Min Max

THLD Clock-to-data hold time 5us 25us

THLD

TCK

'1' stop bit'0' start bit



Keyboard The keyboard uses open collector drivers so that either the keyboard or an attached host device can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use simple input-only ports). The clock and data signals (PS2C and PS2D) are connected directly to pins on the B connector. A PS2-style keyboard uses scan codes to communicate key press data (nearly all keyboards in use today are PS2 style). Each key has a single, unique scan code that is sent whenever the corresponding key is pressed. If the key is pressed and held, the scan code will be sent repeatedly once every 100ms or so. When a key is released, a “F0” key-up code is sent, followed by the scan code of the released key. If a key has a “shift” character that is

different than the non-shift character, the same scan code is sent whether the shift key is pressed or not, and the host device must determine which character to use. Some keys, called extended keys, send an “E0” ahead of the scan code (and they may send more than one scan code). When an extended key is released, a “E0 F0” key-up code is sent, followed by the scan code. Scan codes for most keys are shown in the figure below.

A host device can also send data to the keyboard. Below is a short list of some often-used commands. ED Turn on/off Num Lock, Caps Lock, and

Scroll Lock LEDs. The keyboard acknowledges receipt of an “ED” by returning an “FA”, after which the host send another byte to set LED status: Bit 0 sets Scroll Lock; bit 1 sets the Num Lock; and Bit 2 sets Caps lock. Bits 3 to 7 are ignored.

EE Echo. Upon receiving an echo command, the keyboard replies with the same scan code (“EE”).

F3 Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA”, after which the host sends a second byte to set the repeat rate.

FE Resend. Upon receiving a resend

command, the keyboard will re-send the last scan code sent.

FF Reset. Resets the keyboard. The keyboard should send data to the host only when both the data and clock lines are high (or idle). Since the host is the “bus master”, the keyboard should check to see whether the host is sending data before driving the bus. To facilitate this, the clock line can be used as a “clear to send” signal. If the host pulls the clock line low, the keyboard must not send any data until the clock is released (host-to-

ESC76

` ~0E

TAB0D

Caps Lock58

Shift12

Ctrl14

1 !16

2 @1E

3 #26

4 $25

5 %2E

Q15

W1D

E24

R2D

T2C

A1C

S1B

D23

F2B

G34

Z1Z

X22

C21

V2A

B32

6 ^36

7 &3D

8 *3E

9 (46

0 )45

- _4E

= +55

BackSpace66

Y35

U3C

I43

O44

P4D

[ 54

] 5B

\ |5D

H33

J3B

K42

L4B

; :4C

' "52

Enter5A

N31

M3A

, <41

> .49

/ ?4A

Shift59

Alt11

Space29

AltE0 11

CtrlE0 14

F105

F206

F304

F40C

F503

F60B

F783

F80A

F901

F1009

F1178

F1207 E0 75

E0 74

E0 6B

E0 72



keyboard data transmission will not be dealt with further here). The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at around 20 - 30KHz) when the data is sent, and data is valid on the falling edge of the clock. Mouse The mouse outputs a clock and data signal when it is moved; otherwise, these signals remain at logic ‘1’. Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21, and 32 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown below. Data is valid at the falling edge of the clock, and the clock period is 20 to 30KHz. The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits – a 1’

1 indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement – the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators – a ‘1’ means overflow has occurred). If the mouse moves continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and Right button presses (a ‘1’ indicates the button is being pressed).

L R 0 1 XS YS XY YY P X0 X1 X2 X3 X4 X5 X6 X7 P Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P1 0 1 00 11

Idle stateStart bit Stop bit

Start bitStop bit

Start bitStop bit

Idle state

Mouse status byte X direction byte Y direction byte



VGA port The five standard VGA signals Red (R), Green (G), Blue (B), Horizontal Sync (HS), and Vertical Sync (VS) are routed directly from the A connector to the VGA connector. A series resistor is used on each color line to provide 3-bit color, with 1 bit each for Red, Green, and Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals remain in the VGA-specified 0V – 0.7V range. The HS and VS signals are TTL level.

VGA signal timings are specified, published, copyrighted and sold by the VESA organization (www.vesa.org). The following VGA system and timing information is provided as an example of how a VGA monitor might be driven in 640 by 480 mode. For more precise information, or for information on higher VGA frequencies, refer to document available at the VESA website (or experiment!).

VGA systems and signal timings for a 60Hz, 640x480 display

DB15 VGA connectorFront view

Pin 1

Pin 6

Pin 11

Pin 5

Pin 10

Pin 15

Pin 1

Pin 15

DB15 through-hole pattern asseen from the top

1 6

112 7

123 8

134 9

1451015

GND

DB15Connector

To R on Connector BRed

Green

Blue

Horizontal Sync

Vertical Sync

To G on Connector B

To B on Connector B

To HS on Connector B

To VS on Connector B

470

470

470



CRT-based VGA displays use amplitude modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permitivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays (so the “signals” discussion below pertains to both CRTs and LCDs). CRT displays use electron beams (one for red, one for blue and one for green) to illuminate phosphor that coats the inner side of the display end of a cathode ray tube (see drawing below). Electron beams emanate from “electron guns”, which are a finely pointed, heated cathodes placed in close proximity to a positively charged annular plate called a “grid”. The electrostatic force imposed by the grid pulls away rays of energized electrons as current flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger electrostatic force that results from the entire phosphor coated display surface of the CRT being charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they accelerate to impact on the phosphor coated display surface. The phosphor surface glows brightly at the impact point, and the phosphor continues to glow for several hundred microseconds after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will glow. Between the grid and the display surface, the beam passes through the neck of the CRT

where two coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons), they can be bent by these magnetic fields. Current waveforms are passed through the coils to produce magnetic fields that cause the electron beams to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom. Information is only displayed when the beam is moving in the “forward” direction (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and the frequency at which the electron beam can be modulated determine the display resolution. Modern VGA displays can accommodate different resolutions, and a VGA controller circuit dictates the resolution by producing timing signals to control the raster patterns. The controller must produce TTL-level synchronizing pulses to set the frequency at

which current flows through the deflection coils, and it must ensure that pixel (or video) data is applied to the electron guns at the

Cathode ray tube display system

Anode (entire screen)

High voltage supply(>20kV) Control board

Deflection coilsGrid

Electron guns(Red, Blue, Green)

guncontrolgrid

controldeflection

control

R,G,B signals (to guns)

Sync signals(to deflection control)

Cathode ray tube

Cathode ray

VGA cable



Currentthroughhorizontaldefletioncoil

Stable current ramp - informationdisplayed during this time

Retrace - noinformationdisplayedduring thistime

Total horizontal timeHorizontal display time

Horizontal sync signalsets retrace frequency

retrace timetime

HS

"back porch""front porch"

VGA displaysurface

640 pixels are displayed each timethe beam travels across the screen

pixel 0,639pixel 0,0

pixel 479,0 pixel 479,639

correct time. Video data typically comes from a video refresh memory, with one or more bytes assigned to each pixel location (the DIO1 board uses 3-bits per pixel). The controller must index into video memory as the beams move across the display, and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel. The VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data based on the pixel clock. The pixel clock defines the time available to display 1 pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies falling in the 60Hz to 120Hz range. The number of lines to be displayed at a given refresh frequency defines the horizontal “retrace” VGA Signal Timing

A VGA controller circuit decodes the output of a horizontal-sync counter driven by the pixel clock to generate HS signal timings. This counter can be used to locate any pixel location on a given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to generate VS signal timings, and this counter can be used to locate any given row. These two continually running counters can be used to form an address into

TS

Tdisp

Tpw

Tfp

Tbp

TS

Tdisp

Tpw

Tfp

Tbp

Sync pulse timeDisplay timeVS pulse widthVS front porchVS back porch

16.7ms15.36ms

64 us320 us928 us

416,800384,000

1,6008,000

23,200

521480

21029

Symbol ParameterTime Clocks Lines

Vertical Sync

32 us25.6 us3.84 us640 ns

1.92 us

800640961648

ClocksHorizontal SyncTime



video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so the designer can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation. Connector pinouts

The connector pinouts are shown below. Separately available tables show pass-through connections for the devices on the DIO1 board when the board is attached to various system boards – i.e., one table is available showing the FPGA connections to the DIO1 devices for a D2 system board, another table is available showing the FPGA connections for a D2E board, a third for the D2XL board, etc.

J2 (B) connector J1 (A) Connector Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 1 CA 11 CF 21 A1 31 n/c 30 BLU 2 SW1 12 SW6 22 LD1 32 LD6 32 PS2D 3 CB 13 CG 23 A2 33 n/c 33 GRN 4 SW2 14 SW7 24 LD2 34 LD7 34 PS2C 5 CC 15 DP 25 A3 35 n/c 35 RED 6 SW3 16 SW8 26 LD3 36 LD8 36 HS 7 CD 17 BTN2 27 A4 37 VDD33 37 VDD 8 SW4 18 BTN1 28 LD4 38 LDG 38 VS 9 CE 19 BTN4 29 n/c 39 GND 39 GND

10 SW5 20 BTN3 30 LD5 40 VU 40 VU

Digilent Board Interconnect Table Digilent, Inc.

D2E to DIO1 Interconnect Tables Dio1 Pinout D2E Pinout

Connector P2 Connector E and A Connector C Pin Signal Pin Signal Pin Signal 1 CA 39 A39 17 39 C39 127 2 SW1 40 A40 16 40 C40 126 3 CB 37 A37 20 37 C37 132 4 SW2 38 A38 18 38 C38 129 5 CC 35 A35 22 35 C35 134 6 SW3 36 A36 21 36 C36 133 7 CD 33 A33 24 33 C33 136 8 SW4 34 A34 23 34 C34 135 9 C 31 A31 29 31 C31 139 10 SW5 32 A32 27 32 C32 138 11 CF 29 A29 31 29 C29 141 12 SW6 30 A30 30 30 C30 140 13 CG 27 A27 34 27 C27 146 14 SW7 28 A28 33 28 C28 145 15 DP 25 A25 36 25 C25 148 16 SW8 26 A26 35 26 C26 147 17 BTN2 23 A23 41 23 C23 150 18 BTN1 24 A24 40 24 C24 149 19 BTN4 21 A21 43 21 C21 152 20 BTN3 22 A22 42 22 C22 151 21 A1 19 A19 45 19 C19 160 22 LD1 20 A20 44 20 C20 154 23 A2 17 A17 47 17 C17 162 24 LD2 18 A18 46 18 C18 161 25 A3 15 A15 49 15 C15 164 26 LD3 16 A16 48 16 C16 163 27 A4 13 A13 56 13 C13 166 28 LD4 14 A14 55 14 C14 165 29 11 A11 58 11 C11 168 30 LD5 12 A12 57 12 C12 167 31 9 A9 60 9 C9 173 32 LD6 10 A10 59 10 C10 169 33 7 A7 62 7 C7 175 34 LD7 8 A8 61 8 C8 174 35 BTN5 5 A5 64 5 C5 178 36 LD8 6 A6 63 6 C6 176 37 VCC 3 VCC VCC 3 VCC VCC 38 4 A4 68 4 C4 179 39 GND 1 GND GND 1 GND GND 40 2 VU VU 2 VU VU

Administrator

矩形

Administrator

打字機文字

E

Digilent Board Interconnect Table Digilent, Inc.

Dio1 Pinout D2E Pinout

Connector P1 Connector F and B Connector D Pin Signal Pin Signal Pin Signal 1 39 39 D39 70 2 40 40 D40 71 3 37 37 D37 73 4 38 38 D38 74 5 35 35 D35 75 6 36 36 D36 81 7 33 33 D33 82 8 34 34 D34 83 9 31 31 D31 84 10 32 32 D32 86 11 29 29 D29 87 12 30 30 D30 88 13 27 27 D27 89 14 28 28 D28 93 15 25 25 D25 94 16 26 26 D26 95 17 23 23 D23 96 18 24 24 D24 97 19 21 21 D21 98 20 22 22 D22 99 21 19 19 D19 100 22 20 20 D20 101 23 17 17 D17 102 24 18 18 D18 108 25 15 15 D15 109 26 16 16 D16 110 27 13 13 D13 111 28 14 14 D14 112 29 11 B11 185 11 D11 113 30 12 B12 182 12 D12 114 31 BLU 9 B9 188 9 D9 115 32 PS2D 10 B10 187 10 D10 116 33 GRN 7 B7 191 7 D7 120 34 PS2C 8 B8 189 8 D8 121 35 RED 5 B5 193 5 D5 122 36 HS 6 B6 192 6 D6 123 37 VCC 3 VCC VCC 3 VCC VCC 38 VS 4 B4 194 4 D4 125 39 GND 1 GND GND 1 GND GND 40 2 VU VU 2 VU VU

Digilab 2E digilent, inc.tylee/Courses/FPGA... · Digilab 2E FPGA Development Board The Digilab 2E (D2E) FPGA-based development board makes an excellent prototyping platform for moderate

Documents