Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification 1 Ashish Amonkar, Principal Design Engineer, Cypress Semiconductor, Kurt Takara, Mentor, a Siemens Business, Avinash Agrawal, Mentor, a Siemens Business,
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Did Power Management Break My CDC Logic? An Integrated ......An Integrated Approach to Power Domain and Clock Domain Crossing Verification 1 Ashish Amonkar, Principal Design Engineer,
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Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and
Clock Domain Crossing Verification
1
Ashish Amonkar, Principal Design Engineer, Cypress Semiconductor,
Kurt Takara, Mentor, a Siemens Business,
Avinash Agrawal, Mentor, a Siemens Business,
AGENDA
2
• CDC P checks – Why,Challenges
• CDC PA checks – Flow
• CDC PA checks – Commands
• CDC PA checks – Testbench integration
Low Power Design & Verification - Why• Problem of Today’s Complex SoC Design:
– Leakage power becoming issue below 65 nm
– Dynamic power remains as an issue for decades
– Market Demands: longer battery, IoT, handheld
• Solution: – Control the Supply
– Partitioning design in multiple power domains• Helps to run the design with different voltage
• Helps to accommodate different ON/OFF etc.
• Conventional HDL do not have notion of power domains – No method to distribute power supply network
– No method for switching power ON or OFF or switching voltage values
• Power management needs to be verified early in the design process
• IEEE-1801/UPF enables power management and verification
3
Multi-voltage
Power Gating Power Gating with Retention
Low-power stand by
DVS/AVS
Blocks of chip can run 1.2V, 1.0, 0.9V
Some block of chip is OFF, while other running in 1.2V, 1.0V, 0,9V
The OFF block state and data can be retain
Some blockmay need to run at possible low voltage to hold state and data
Dynamic voltage scaling and adaptive voltage scaling is very performance dependent
Chip Power Management Trends
AAA, Integrated Approach to Power Domain/Clock domain crossing checks May 2019
Power Aware Design – UPF • In Design Verification and Implementation Flow (DVIF)
– UPF is a TCL based language provides the notion of Power Intent
• Power Intent - actually the power specification of a designe.g.
– How many power domains are required in the design?
– How to define the primary supply for each domain?
– What protection strategies are required?
• UPF LRM IEEE-1801: specifies syntax/semantics to define power intents – There are multiple version of UPF from 1.0, 2.0, 2.1, 3.0 …
• However, UPF works as a side file with HDL in the DVIF
• The verification and implementation tools– Share common semantics and extends the HDL with UPF artifacts
Your Initials, Presentation Title, Month Year4
create_power_domain –elements {.}
set_isolation <-clamp_value –
isolation_signal …>
……
Power Aware Verification - Why
• Partitioning Issues:– Incorrect implementation of system power modes– Cyclic domain state interdependencies
• Control Sequence Issues:– Power down/up control sequence errors– Power state transition and sequencing errors– Failure to reset after power down/up
• Power Management Issues– Incorrectly structured power switching network– Incorrect powering of logic elements
• Structural Issues:– Missing, incorrect, or redundant isolation strategies and/or cells – Missing, incorrect, or redundant strategies and/or level shifters– Missing, incorrect, or redundant strategies and/or retention registers
Your Initials, Presentation Title, Month Year
PA Dynamic
Verification
PA Static
Verification
5
CDC Power Aware Verification - Why
6
• CDC-PA handles UPF-extended HDL designs by doing two things:
– Static verification of the UPF logic.
– Analysis of clock domain crossings involving UPF logic.
• CDC analysis of the design with UPF logic can uncover clock domain crossing issues where both power domains and clock domains are involved
Table 1. CDC-PA Schemes
Scheme Description
pa_combo_logic
UPF adds combinational logic to a crossing.
pa_iso_en_no_sync
UPF isolation cell enable signal does not have a proper synchronizer.