DHD Lab File work

7/25/2019 DHD Lab File work

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1

Experiment No. 1

Object:

To design and simulate the AND gate circuit using DATAFLOW Modeling.

Apparatus:

Xilinx ISE !." so#t$are %it& Acti'e( )DL& Student Edition

Theory:

Input Output

A B Y=A.B

* * *

* *

* *

Fig+ Truth ta,le o# AND -ATE

13EEBCS004

Amit Kumar



2

V!" #o$e:

li,rar ieee/

use ieee.std0logic012.all/

entit and0gate is

3ort 4 a + in std0logic/

, + in std0logic/

+ out std0logic5/

end and0gate/

architecture data#lo$ o# and0gate is

,egin

67 a and ,/

end architecture/

Test Bench :entit and0t, is

end and0t,/

architecture test,ench o# and0t, is

com3onent and0gate

3ort4 a + in std0logic/

, + in std0logic/

+ out std0logic 5/

end com3onent/

signal a + std0logic +7 8*8/ signal , + std0logic +7 8*8/

signal + std0logic/

,egin

uut+ and0gate 3ort ma34a&,&5/

3rocess

,egin

a678*8/ ,678*8/

$ait #or "9 ns/

a678*8/ ,6788/

$ait #or "9 ns/

a6788/ ,678*8/ $ait #or "9 ns/

a6788/ ,6788/

$ait #or "9 ns/

end 3rocess/

end/

13EEBCS004

Amit Kumar



3

Fig+ Simulation o# AND -ate

Fig+ To3 :ie$ o# AND -ate

Fig+ ;TL Schematic o# AND -ate

%esu&t :

The AND gate circuit is designed and simulated success#ull.

13EEBCS004

Amit Kumar



4

Experiment No. '

Object:

To design and simulate the O; gate circuit using DATAFLOW Modeling.

Apparatus:


Theory:

Input Output

A B Y=A(B

* * *

*

*

Fig+ Truth ta,le o# O; -ATE

13EEBCS004

Amit Kumar



5

V!" #o$e:

li,rar ieee/


entit or0gate is


, + in std0logic/

+ out std0logic5/

end or0gate/

architecture data#lo$ o# or0gate is

,egin

67 a or ,/

end architecture/

test bench:

entit or0t, is

end or0t,/

architecture test,ench o# or0t, is

com3onent or0gate


, + in std0logic/

+ out std0logic 5/

end com3onent/

signal a + std0logic +7 8*8/

signal , + std0logic +7 8*8/

signal + std0logic/

,egin

uut+ or0gate 3ort ma34a&,&5/

3rocess

,egin

a678*8/ ,678*8/

$ait #or "9 ns/

a678*8/ ,6788/

$ait #or "9 ns/ a6788/ ,678*8/

$ait #or "9 ns/

a6788/ ,6788/

$ait #or "9 ns/

end 3rocess/

end/

13EEBCS004

Amit Kumar



6

Fig+ Simulation o# O; -ate

Fig+ To3 :ie$ o# O; -ate

Fig+ ;TL Schematic o# O; -ate

%esu&t :

The O; gate circuit is designed and simulated success#ull.

13EEBCS004

Amit Kumar



7

Experiment No. )

Object:

To design and simulate the NOT gate circuit using DATAFLOW Modeling.

Apparatus:


Theory:

Input Output

A Y=not*A+

*

*

Fig+ Truth ta,le o# NOT -ATE

13EEBCS004

Amit Kumar



8

V!" #o$e:

li,rar ieee/


entit not0gate is


+ out std0logic5/

end not0gate/

architecture data#lo$ o# not0gate is

,egin

67 not a/

end architecture/

test bench:entit not0t, is

end not0t,/

architecture test,ench o# not0t, is

com3onent not0gate

3ort4a + in std0logic/

+ out std0logic 5/

end com3onent/


signal + std0logic/ ,egin

uut+ not0gate 3ort ma34a&5/

3rocess

,egin

a678*8/

$ait #or "9 ns/

a6788/

$ait #or "9 ns/

end 3rocess/

end/

13EEBCS004

Amit Kumar



9

Fig+ Simulation o# NOT -ate

Fig+ To3 :ie$ o# NOT -ate

Fig+ ;TL Schematic o# NOT -ate

%esu&t :

The NOT gate circuit is designed and simulated success#ull.

13EEBCS004

Amit Kumar



10

Experiment No. ,

Object:

To design and simulate the NAND gate circuit using DATAFLOW Modeling.

Apparatus:


Theory:

Input Output

A B Y=not*A.B+

* *

*

*

*

Fig+ Truth ta,le o# NAND -ATE

13EEBCS004

Amit Kumar



11

V!" #o$e:

li,rar ieee/


entit nand0gate is


, + in std0logic/

+ out std0logic 5/

end nand0gate/

architecture data#lo$ o# nand0gate is

,egin

67 a nand ,/

end architecture/

Test Bench:entit nand0t, is

end nand0t,/

architecture test,ench o# nand0t, is

com3onent nand0gate


, + in std0logic/

+ out std0logic 5/

end com3onent/



signal + std0logic/

,egin

uut+ nand0gate 3ort ma34a&,&5/

3rocess

,egin

a678*8/ ,678*8/

$ait #or "9 ns/

a678*8/ ,6788/

$ait #or "9 ns/

a6788/ ,678*8/

$ait #or "9 ns/

a6788/ ,6788/

$ait #or "9 ns/

end 3rocess/

end/

13EEBCS004

Amit Kumar



12

Fig+ Simulation o# NAND -ate

Fig+ To3 :ie$ o# NAND -ate

Fig+ ;TL Schematic o# NAND -ate

%esu&t :

The NAND gate circuit is designed and simulated success#ull.

13EEBCS004

Amit Kumar



13

Experiment No. -

Object:

To design and simulate the NO; gate circuit using DATAFLOW Modeling.

Apparatus:


Theory:

Input Output

A B Y=not*A(B+

* *

* *

* *

*

Fig+ Truth ta,le o# NO; -ATE

13EEBCS004

Amit Kumar



14

V!" #o$e:

li,rar ieee/


entit nor0gate is


, + in std0logic/

+ out std0logic5/

end nor0gate/

architecture data#lo$ o# nor0gate is

,egin

67 a nor ,/

end architecture/

test bench:

entit nor0t, is

end nor0t,/

architecture test,ench o# nor0t, is

com3onent nor0gate


, + in std0logic/

+ out std0logic 5/

end com3onent/



signal + std0logic/

,egin

uut+ nor0gate 3ort ma34a&,&5/

3rocess

,egin

a678*8/ ,678*8/

$ait #or "9 ns/

a678*8/ ,6788/

$ait #or "9 ns/ a6788/ ,678*8/

$ait #or "9 ns/

a6788/ ,6788/

$ait #or "9 ns/

end 3rocess/

end/

13EEBCS004

Amit Kumar



15

Fig+ Simulation o# NO; -ate

Fig+ To3 :ie$ o# NO; -ate

Fig+ ;TL Schematic o# NO; -ate

%esu&t :

The NO; gate circuit is designed and simulated success#ull.

13EEBCS004

Amit Kumar



16

Experiment No.

Object:

To design and simulate the XO; gate circuit using DATAFLOW Modeling.

Apparatus:


Theory:

Input Output

A B Y=A xor B

* * *

*

*

*

Fig+ Truth ta,le o# XO; -ATE

13EEBCS004

Amit Kumar



17

V!" #o$e:

li,rar ieee/


entit xor0gate is


, + in std0logic/

+ out std0logic5/

end xor0gate/

architecture data#lo$ o# xor0gate is

,egin

67 a xor ,/

end architecture/

Test Bench:entit xor0t, is

end xor0t,/

architecture test,ench o# xor0t, is

com3onent xor0gate


, + in std0logic/

+ out std0logic 5/

end com3onent/



signal + std0logic/

,egin

uut+ xor0gate 3ort ma34a&,&5/

3rocess

,egin

a678*8/ ,678*8/

$ait #or "9 ns/

a678*8/ ,6788/

$ait #or "9 ns/

a6788/ ,678*8/

$ait #or "9 ns/

a6788/ ,6788/

$ait #or "9 ns/

end 3rocess/

end/

13EEBCS004

Amit Kumar



18

Fig+ Simulation o# XO; -ate

Fig+ To3 :ie$ o# XO; -ate

Fig+ ;TL Schematic o# XO; -ate

%esu&t :

The XO; gate circuit is designed and simulated success#ull.

13EEBCS004

Amit Kumar



19

Experiment No. /

Object:

To design and simulate the XNO; gate circuit using DATAFLOW Modeling.

Apparatus:


Theory:

Input Output

A B Y=not*A xor B+

* *

* *

* *

Fig+ Truth ta,le o# XNO; -ATE

13EEBCS004

Amit Kumar



20

V!" #o$e:

li,rar ieee/


entit xnor0gate is


, + in std0logic/

+ out std0logic5/

end xnor0gate/

architecture data#lo$ o# xnor0gate is

,egin

67 a xnor ,/

end architecture/

test bench:

entit xor0t, is

end xor0t,/

architecture test,ench o# xor0t, is

com3onent xor0gate


, + in std0logic/

+ out std0logic 5/

end com3onent/



signal + std0logic/

,egin

uut+ xor0gate 3ort ma34a&,&5/

3rocess

,egin

a678*8/ ,678*8/

$ait #or "9 ns/

a678*8/ ,6788/

$ait #or "9 ns/ a6788/ ,678*8/

$ait #or "9 ns/

a6788/ ,6788/

$ait #or "9 ns/

end 3rocess/

end/

13EEBCS004

Amit Kumar



21

Fig+ Simulation o# XNO; -ate

Fig+ To3 :ie$ o# XNO; -ate

Fig+ ;TL Schematic o# XNO; -ate

%esu&t :

The XNO; gate circuit is designed and simulated success#ull.

DHD Lab File work

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