iv DEVICE TECHNOLOGY FOR NANOSCALE III-V COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTORS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Jenny Ruey-Chen Hu December 2011
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iv
DEVICE TECHNOLOGY FOR
NANOSCALE III-V COMPOUND SEMICONDUCTOR
FIELD EFFECT TRANSISTORS
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
Jenny Ruey-Chen Hu
December 2011
http://creativecommons.org/licenses/by-nc/3.0/us/
This dissertation is online at: http://purl.stanford.edu/hh851xd2122
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Philip Wong, Primary Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Krishna Saraswat, Co-Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Yoshio Nishi
Approved for the Stanford University Committee on Graduate Studies.
Patricia J. Gumport, Vice Provost Graduate Education
This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.
iii
iv
Abstract
As silicon CMOS technology reaches its fundamental scaling limits, alternative
materials such as high mobility III-V compounds have proven to be strong contenders for
extending high performance logic. However, most promising demonstrations of III-V
FET/HEMTs have micron-scale source/drain spacing despite gate lengths on the
nanometer scale. III-V semiconductor devices have historically relied on alloyed ohmic
contacts which require large spacings to prevent shorting between the source and drain
after alloying, where contacts can diffuse up to hundreds of nanometers. This severely
limits the scalability of III-V logic technology. Non-alloyed contacts offer a practical
route to greatly reduce the III-V device footprint for application in future technology
nodes.
In this dissertation, I demonstrate a route to non-alloyed contacts by shifting the
pinned III-V Fermi level to reduce the metal/n-GaAs and metal/n-InGaAs Schottky
barrier heights. The Fermi level is controlled by the insertion of thin dielectrics in a
metal-insulator-semiconductor (MIS) contact structure. The MIS contact is studied
across a wide range of metal and dielectric materials, and found to have great flexibility
in the material selection. I will also discuss the use of bi-layer high-κ dielectrics, and
report results which show that despite an overall thicker dielectric, there is an additional
reduction in the barrier height and contact resistance beyond that of a single dielectric
MIS. This MIS contact is then integrated in an InGaAs MOSFET as a non-alloyed
source/drain contact, though it can also be applied to Schottky Barrier FETs. I will
conclude by discussing possible physical mechanisms of the observed barrier height
reductions, by examining the effects of fixed charge and electronic dipoles.
iv
Acknowledgements
First of all, I would like to thank my advisor, Professor H.-S. Philip Wong for all his
support and guidance the last few years. I have learned a lot from him in not only in
research, but also in my view on life and career. In particular, I really appreciate his
positive attitude and excitement towards research, which never fails to motivate me to
learn more. I would also like to thank my co-advisor Professor Krishna Saraswat whose
doors was always open to me, and eager to help me progress in my research.
Next, I would like to thank several of the people who have helped me a lot in both
discussions and lab work : Aneesh Nainani, Ze Yuan, Saeroonter Oh, Masaharu
Kobayashi, Joseph Chen, Donghun Choi, Eunji Kim, and Byungha Shin.
My work also relied heavily on the availability of the ALD tool, and I want to thank
Yoonyoung Chung, Yasuhiro Oshima, and J Provine for helping make this possible. I
would also like to acknowledge Dr. Jim McVittie for all his expertise and ensuring that
that my research would go smoothly.
I also need to thank all my friends and colleagues who made my life at Stanford very
enjoyable. I feel blessed to have made so many good friends in CIS and in the
Nanoelectronics group.
Finally, I would like to thank my parents and brother for their wholehearted love and
support all these years. This dissertation is dedicated to them.
Table 2.4. Summary of the fitted density (ρ), thickness (t), and roughness for the
Al2O3 / SiO2 / Si structure corresponding to the measurement shown in Figure 2.7.
surface contaminants or oxidization that could affect the measurements. Figure 2.10
shows the experimentally measured and simulated intensity vs. 2θ for Al2O3, with the
fitted parameters given in Table 2.4. The silicon wafer, silicon native oxide, and high-κ
film are all included in the simulated structure. Despite a 30 sec native oxide etch in HF
immediately prior to loading samples into the ALD, there was still roughly 1nm of SiO2
present in all the high-κ films on Si.
Table 2.4 summarizes the measured density (ρ), thickness (t), and roughness of
the films, and provides a comparison with reported crystalline densities and thicknesses
measured by ellipsometry. These films are all deposited at 250oC, and the properties are
expected to change for different deposition temperatures. The thicknesses measured by
0.1 2.1 4.1 6.1 8.1
Intensity (arb. u
nits)
2θ (deg)
Measured
Simulated
21
the two methods agree well and differ only by 1nm. Since film thickness is one of the
fitting parameters for the simulated XRR data, agreement with the ellipsometer measured
thickness provides some confidence in the density values. The HfO2 and TiO2 film
densities measured by XRR were found to be close to the reported crystalline values, but
the Al2O3 density was measured to be significantly lower than the bulk crystalline density.
This lower density can be due to the low temperature ALD process, where the density
may increase with higher deposition temperatures. The effect of the temperature on
density can vary from material to material, depending on the adsorption, dissociation, and
reaction of the precursors.
ALD cycles
Ellipsometer thickness(nm)
Crystallineρ (g/cm3)
ρ (g/cm3) t (nm) Roughness
(nm)
AlOx 140 14.5 3.9 3.04 ± 0.10 13.62 ± 0.03 0.47
HfOx 200 15.7 9.8 9.84± 0.37 14.28± 0.03 0.52
TiOx 380 16.3 4.2 4.02 ± 0.16 16.03± 0.21 0.85
Table 2.5 Summary of ALD cycles, measured thicknesses, density, and
roughness.
2.5 Band Alignment by SRPES To better understand the electrical behavior of devices, it is necessary to know the
bandgap and band alignment between materials. In this case it is between the various
high-k dielectrics and the GaAs or InGaAs substrate. Synchrotron Radiation
Photoemission Spectroscopy (SRPES) was used to determine these band parameters. The
SRPES experiments were performed at beamline 8-1 of the Stanford Synchrotron
Radiation Lightsource (SSRL), which provides a tunable range of monochromatic
photons up to 160eV. The use of the low energy synchrotron radiation results in
increased surface sensitivity and allows measurement of the top 2-3 monolayers of the
surface with great accuracy. The valence band (VB) offset between the dielectric/GaAs and dielectric/InGaAs
were measured by determining the binding energy difference between the VB spectra of
22
the substrate and dielectric [35-37]. For more accurate measurements, the energy shift
induced by the surface charging during photoemission must also be accounted for by
aligning the VB spectra to a reference peak. In this case the Ga 3d core level peak was
chosen as the reference. Using Al2O3/GaAs as an example, Figure 2.11a illustrates a measured valence
band offset of ∆EV = 3.2 eV. The Al2O3 band gap was extracted to be 6.4 eV from the Al
2p energy loss spectrum (Figure 2.11b) and the conduction band offset calculated to be
∆EC = 1.8 eV. As with the stoichiometry and density, the measured Al2O3 bandgap is
lower than the ideal crystalline value [38] of 8.7eV. Though this is less than the ideal
value, it is comparable to those measured by other researchers [39] for similarly
deposited ALD Al2O3. The measured band offsets of other dielectric/GaAs interfaces were measured in
the same way, with values summarized through band diagrams in Figure 2.12.
Figure 2.11. (a) Aligned valence band spectra of Al2O3/GaAs and the GaAs
substrate, illustrating a ∆EV of 3.2eV. (b) Al2p energy loss spectrum showing the
Al2O3 band gap to be 6.4eV.
-2 0 2 4
Inte
nsity
(a.u
)
Binding Energy (eV)
VB GaAsVB Al2O3/GaAs
3.2eV
70 75 80 85
hυ = 120 eV Al2p
6.4eV
Inte
nsit
y (a
.u)
Binding Energy (eV)
(a) (b)
23
Figure 2.12. Measured band gap and band offsets of (a) Al2O3, (b) TiO2, (c)
HfO2, and (d) ZrO2 on GaAs. The band diagrams are all aligned to the GaAs (EG
= 1.42eV) to better illustrate the differences between the dielectrics.
2.6 Summary In this chapter we provided an overview of the III-V materials and ALD
dielectrics that will be used throughout the rest of this thesis for the gate stack and
source/drain contacts. The III-V native oxides cause severe Fermi level pinning so
surface passivation treatments and special precaution to minimize oxygen exposure prior
to ALD are critical. Understanding the ALD operation principle, recipe development, and
temperature dependencies are also necessary to optimize the material properties. From
the atomic concentration measurements by XPS, density calculation by XRR, and band
alignment measurements by SRPES it is apparent that the dielectric properties can differ
greatly from the ideal crystalline properties. As a result, knowledge of the actual material
properties is important in understanding the electrical characteristics and will be helpful
in the following chapters.
1.8 eV
1.4 eV
3.2 eV
Al2O36.4eV
∆EC =
∆EV =
0.5 eV
1.4 eV
1.6 eV
TiO23.5eV
∆EC =
∆EV =
2.3 eV
1.4 eV
2.2 eV
HfO25.9eV
∆EC =
∆EV =
2.2 eV
1.4 eV
2.1 eV
ZrO25.7eV
∆EC =
∆EV =
(a) (b) (c) (d)
24
Chapter 3
MOS Gate Stack
In this chapter, we investigate the effect of forming gas annealing (FGA) on n-
type and p-type In0.53Ga0.47As MOS capacitors with ALD Al2O3 high-κ dielectric. The as-
deposited samples have a significant amount of fixed charge in the bulk of the gate
dielectric and at the dielectric/semiconductor interface, but through FGA, we successfully:
(1) reduce the amount of bulk and interface fixed charge in the Al2O3, and (2) improve
the Al2O3/InGaAs interface. The effect of the annealing temperature (300 - 400oC) and
ambient (N2 and forming gas (FG)) are investigated in detail. We find that there exists a
tradeoff where higher annealing temperatures result in a lower DIT, but comes at the cost
of higher gate leakage. Furthermore, by comparing the effect of annealing in inert N2
versus FG, we discover that hydrogen passivation of dangling bonds and border traps is
responsible for reducing the DIT, while the thermal budget is responsible for minimizing
the fixed charges. Finally, we study the benefit of FGA on InGaAs nMOSFET device
performance and demonstrate that the on-current increases by 25% after annealing at
350oC for 30 min. A thorough understanding of the impact of FGA is crucial for
threshold voltage tuning and improvement of the InGaAs MOSFET gate stack.
3.1 Introduction High mobility III-V compound semiconductors are strong contenders for
extending high performance CMOS logic beyond the limitations of silicon [40]. InGaAs
surface channel MOSFETs have demonstrated high performance devices [11, 41, 42]
with fairly good interfaces due to the “self-cleaning” benefit of ALD Al2O3 and HfO2
25
high-κ dielectrics on III-V semiconductors [43]. In III-V MOSFET fabrication, post
deposition anneals (PDA) in O2 or N2 are often employed, but annealing in forming gas
(FG) ambient is rarely used. Recently, there have been reports on the benefit of hydrogen
annealing in passivating the defects in ALD Al2O3 and HfO2 on InGaAs [44-46]. Kim et
al. [45] first reported that hydrogen anneals can greatly reduce the frequency dispersion
of the accumulation capacitance in Pt/Al2O3/n-In0.53Ga0.47As MOS capacitors
(MOSCAPs) and attributed the dispersion to border traps. These results were confirmed
by Shin et al. [46] who used density functional theory to calculate the energy levels of Al
and O dangling bonds that correspond with the observed fixed charges in the oxide, and
further suggested that hydrogen from FGA can passivate these dangling bonds. Building upon these reported results, we find that instead of attributing all the
benefits of FGA to hydrogen alone, both hydrogen passivation and the thermal budget
together contribute to the improvement of the interfacial properties. In previous studies of
the Al2O3/In0.53Ga0.47As interface, MOSCAPS with only one metal workfunction was
investigated under a single annealing condition of FGA at 400oC without a control study
in an inert ambient. Also, studies were limited to n-type MOS capacitors and no work has
been done on the p-type InGaAs MOSCAPs that are used to fabricate InGaAs
nMOSFETs. Furthermore, these MOSCAPs have only been electrically characterized
through capacitance-voltage measurements and the impact of FGA on the leakage current
has not been reported. For III-V MOSFETs, the gate leakage is an important performance
metric for determining the ION/IOFF ratio, off-state power consumption, and scalability of
the effective oxide thickness (EOT). In this work, we investigate the effect of FGA on n-type and p-type In0.53Ga0.47As
MOS capacitors with Al2O3 high-κ dielectric across a wide range of metal workfunctions
(ΦM) from Al (ΦM = 4.1 eV) to Pt (ΦM = 5.65 eV). The as-deposited gate dielectric was
found to contain a considerable amount of bulk and interface fixed charge which causes
the MOSFET flat band voltage (VFB) to change significantly with dielectric thicknesses,
leading to undesirable changes in the threshold voltage. We first demonstrate the benefit
of FGA through an alignment of the VFB across MOSCAPs with different oxide
thicknesses, which indicates the successful reduction of fixed charges in the Al2O3. This
26
was achieved for a range of metal workfunctions, so the effect was dependent on the gate
metal used. We then investigate in more detail the effect and tradeoffs of the annealing
temperature (300 - 400oC) and ambient (N2 and FG) on the capacitance-voltage (C-V),
current-voltage (I-V), and interface trap density (DIT). Finally, we apply the optimized
annealing conditions to InGaAs nMOSFETs to demonstrate the benefit of FGA at the
transistor level.
3.2 III-V MOSCAP 3.2.1 Device Fabrication Process
We study both n-type and p-type MOS capacitors to better understand the effect
of FGA on InGaAs pMOSFETs and nMOSFETs. The p-type MOSCAPs were fabricated
on MBE grown 300nm thick p-In0.53Ga0.47As (Be doped 6x1015 cm-3) lattice matched to
the p+-InP substrate and in-situ capped with 50nm of arsenic to prevent oxidation. The
samples are organically degreased then loaded into the ALD chamber for As-decapping
at 400oC for 5 min, followed by in-situ ALD Al2O3 deposition. The n-type MOSCAPs
were fabricated on 40nm thick n-In0.53Ga0.47As (Si doped 1x1018cm-3) epitaxially grown
on n+-InP substrates. The samples underwent an organics degrease and NH4OH pre-clean
treatment immediately prior to loading into the ALD chamber. For both types of
MOSCAPs, 50, 75, 100, and 125 cycles of ALD Al2O3 were deposited at 300oC using
trimethylaluminum (TMA) and H2O precursors, with TMA being the starting pulse. The
film thicknesses were measured to be 4.7nm, 7.0nm, 9.2nm, and 12.0 nm. Metal top
electrodes were then e-beam evaporated through shadow masks, followed by the
deposition of Ti/Pt backside ohmic contacts. Post metallization annealing at near atmospheric pressure was performed in a
quartz tube furnace in FG (5%H2 + 95%N2) and N2 ambients. The samples were
organically degreased in acetone, methanol, and isopropanol immediately prior to loading
into the furnace at room temperature. FG (or N2) is first flown at 5L/min for 15 min to
clear the gas lines and to ensure that there is no oxygen present in the quartz tube prior to
annealing. The furnace is then baked at 100oC for 30 min to desorb any moisture and
27
oxygen from the samples and quartz tube that may be present from the opening/closing of
the tube. Next, the FG (or N2) flow rate is reduced to 2L/min, and the samples are
annealed at 300, 350, and 400oC for 30 min. After annealing, the furnace is cooled down
to room temperature, and samples are not removed until the furnace is below 50oC.
Annealing in FG and N2 were carried out in the same furnace following the exact
experimental procedure.
3.2.2 Electrical Characterization
A. VFB Alignment and Reduction of Frequency Dispersion with FGA
Figure 3.1a shows the as-deposited C-V characteristics for Pt/Al2O3/n-InGaAs at
1MHz for different oxide thicknesses. The shift in VFB with Al2O3 thickness indicates the
presence of fixed charge in the film. After a FGA at 400oC for 30min these charges were
successfully minimized, as illustrated in Figure 3.1b by the alignment of the VFB. It is
interesting to note that after FGA, the thinner 50cy Al2O3 samples had a negative shift in
VFB, while the thicker 100cy samples had a positive shift in VFB. This confirms the
presence of charge in both the bulk of the dielectric and at the oxide/semiconductor
interface and indicates that the charge at the Al2O3/InGaAs interface is negatively
charged, while the charge throughout the oxide is positively charged. This non-uniform
distribution of fixed charge was also observed by Shin et al. [46] despite having MOS
capacitors fabricated using different surface pre-clean treatments and ALD films.
Through an in-situ XPS characterization during ALD, Shin et al. [46] discovered that the
Al2O3 is oxygen rich near the interface and aluminum rich away from the interface,
which offers a good explanation for the nature of the change in charge across the oxide. In the inset of Figure 3.1b, a direct comparison of measurements taken between
before and after FGA shows a clear reduction in C-V stretch out, indicating a decrease in
the DIT. This is achieved while maintaining a near-constant accumulation capacitance, so
there is no interfacial oxide formed and no change in the dielectric constant. However,
the sharper C-V transition comes at the cost of an increase in hysteresis from 120mV to
140mV and an increase in leakage current. Both observations will be discussed in detail
28
in the next section. In measuring C-V across a range of frequencies from 1kHz to 1MHz,
there is a sharp contrast between before and after FGA measurements (Figure 3.2). After
FGA there is a noticeable decrease in the frequency dependent VFB shift and frequency
dispersion in the accumulation regime. The C-V dispersion in the inversion regime is also
smaller after FGA, possibly due to the reduction of trap assisted inversion in the as-
deposited sample. DIT measurements by conductance and high frequency – low frequency
(HF-LF) methods [47] confirm a decrease in the DIT from midgap to valence band, where
after FGA, the as-deposited midgap DIT of 5.3x1012 was reduced to 1.6 x1012 cm-2eV-1. It is important to note that when the samples were annealed in a furnace that is
kept at 400oC, the leakage current was a few orders higher. The difference can be that in
opening the furnace and loading samples at the elevated temperature of 400oC, any
impurities or oxygen will be incorporated into the sample. Also, the purging of the gas
lines at room temperature, tube furnace baking at 100oC prior to sample loading, and
cooling down to < 100oC prior to sample unloading all appear to be critical steps in
maintaining cleanliness in the annealing process.
Figure 3.1. (a) C-V for Pt/Al2O3/n-InGaAs with 50, 70, and 100 cycles of ALD.
The as deposited samples have an oxide thickness dependent VFB shift which
indicates the presence of significant oxide charge. (b) After a FGA at 400oC for
30 min there is VFB alignment across all thicknesses. Inset: C-V for 100cy of
Al2O3 showing a steeper C-V transition after FGA.
-3 -2 -1 0 1 20.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-3 -2 -1 0 1 2 3
ΔHYS
= 140mV
f = 1 MHzΔ
HYS= 120mV
t = 4.7 nm t = 6.7 nm t = 9.2 nm
Capa
cita
nce
/ Cm
ax
Voltage (V)
Ideal VFB
(a) As-Deposited (b) After FGA Annealing
2 0 2
V
AfterFGA
BeforeFGA
V
29
Figure 3.2. MOSCAP C-V of Pt/Al2O3/n-InGaAs across many frequencies from
1kHz to 1MHz. (a) As deposited, there is significant frequency dependent VFB
shift. From the HF-LF method [32], we measured a midgap DIT of 5.3x1012 cm-
2eV-1. (b) After FGA at 400oC for 30 min, the frequency dependent VFB shift is
greatly reduced from 380mV to 100mV, along with a factor of three reduction in
the midgap DIT to1.6 x1012 cm-2eV-1 (Figure 3.6).
By investigating different metal gates, we find the alignment of VFB and reduction
of frequency dispersion by FGA is not limited to MOSCAPs with hydrogen catalyst
metals (Ni, Pd, and Pt), since these same effects were also observed in MOSCAPs with
Al and Ti metal gates. To quantify the effect, VFB was extracted using several methods
from the theoretical flat band capacitance, integration of the quasi-static C-V for surface
potential, and second differentiation of the inverse capacitance, which all resulted in the
same general trend. The VFB reported here was extracted from the 1MHz high frequency
C-Vs (CHF) by taking the second derivative of (1/CHF)2 with respect to the gate voltage
[32]. For the as-deposited 100cy case, VFB is fairly close to the ideal VFB = ΦM-χ ,
Table 4.3. Summary of Si and Ge MIS contact literature.
Prior to our work, the MIS contact structure has only been investigated for
elemental semiconductors Si and Ge, and as described in the beginning of this section,
III-V semiconductors would also benefit from the ability to reduce the Schottky barrier
height. We demonstrate for the first time the use of MIS contacts on compound
semiconductor materials GaAs and In0.53Ga0.47As, and implement an optimized contact to
the source/drain of an InGaAs MOSFET. Furthermore, in the Ge MIS literature each
research group focused on only one or two combinations of dielectric and metal materials
so there was no comprehensive study of how these two parameters affect the minimal
achievable contact resistance. In this chapter, we investigate the use of SiN, Al2O3, HfO2,
ZrO2, TiO2, and ZnO dielectrics, along with a study of how the deposition temperature
can affect the contact behavior. Substrate doping and a wide range of metal work
functions from Y (ΦM = 3.1eV) to Pt (ΦM = 5.65eV) were also studied to provide a more
complete understanding. Although the results are based on III-V semiconductors, the
understanding can also be extended to Si and Ge MIS. The results from this chapter will
aid in the elucidation of the underlying physical mechanism behind the reduced barrier
heights discussed in the next chapter.
54
4.3 Device Fabrication
For the initial III-V substrate, GaAs is chosen for its large bandgap to facilitate
ΦB,eff extraction, and also as a baseline III-V material to develop a contact structure that
can be extended to other more technologically relevant III-V materials such as InGaAs,
GaSb, and InSb for future CMOS. The MIS contact fabrication started with the use of
lightly doped (2x1016cm-3) MBE grown n-GaAs to emphasize the thermionic emission
current over the barrier and to more accurately extract barrier height values. For GaAs,
the native oxide forms a low density, high surface states interface which causes strong
Fermi level pinning. Therefore, great care needs to be taken in minimizing the formation
of native oxide during contact fabrication. The samples underwent an organics degrease
by sonication in a 1:1 acetone and methanol solution, followed by rinsing in deionized
(DI) water for 1 minute. The native oxide was then removed by soaking the samples in a
dilute HCl solution (1:1 = DI water : 29% HCl) for 3 minutes, followed by a 20sec DI
water rinse with agitation. Immediately after the rinsing step the samples were immersed
in 5% ammonium sulfide (NH4)2S solution for sulfur passivation. After soaking for
15min the samples were removed and rinsed well in DI water and dried by nitrogen gun
and immediately loaded into the ALD chamber to minimize native oxide formation.
Sulfur passivation in (NH4)2S has been shown to terminate the substrate with Ga-S and
As-S bonding[27] which helps prevent further oxidation. The bonding is stable for up to
30 minutes in air, however, the time between passivation and dielectric deposition were
still minimized and kept under 5 minutes. The dielectric films were deposited by RF sputtering in the AJA tool and ALD in
the Cambridge Nanotech Savannah tool. Amorphous SiN was sputtered from a
stochiometric Si3N4 target at 200oC under Ar/N2 ambient, where bias and heat were
applied to achieve a dense and uniform film. Al2O3, HfO2, ZrO2, TiO2, and ZnO were
ALD deposited using standard pulse and purge times. Table 4.4 summarizes the
precursors used and the deposition temperature. The deposition temperatures were
mostly higher than in the standard recipe for higher quality, denser films. The maximum
temperature of 250oC was used in most cases, except for ZrO2 and ZnO were at higher
55
temperatures the precursors would no longer adsorb well on the sample surface. To
minimize GaAs native oxide formation, the metal organic precursor was used as the
starting pulse, to follow with the self-cleaning [43] observed in Al2O3 and HfO2. After the dielectric deposition, the samples were loaded into shadow mask holders
and the diodes were defined by metal evaporation in Innotec. The metal thickness
depended on the material and varied from 75nm for Pt to 150nm for Al. When the front
metal is finished, the shadow mask holders were flipped and the backside of the samples
were lightly scratched using a diamond scriber in crosshatch patterns to remove the
native oxide immediately prior to loading the samples for the 50nm Ti + 150nm Au back
contact deposition in Innotec. The final device structure along with a cross sectional TEM
is shown in Figure 4.6.
Film Metal Precursors ALD Reaction Temp.
Al2O3 TMA (CH3)3 Al + H2O 250oC
TiO2 TDMAT [(CH3) 2N]4 Ti + H2O 250oC
HfO2 TDMAH [(CH3) 2N] Hf + H2O 250oC
ZrO2 TEMAZ (CH3C2H5)4 Zr + H2O 200oC
ZnO DEZn (C2H5) 2Zn + H2O 160oC
Table 4.4. Summary of the ALD precursors and deposition temperature.
Figure 4.6. (a) Schematic diagram of the contact structure. (b) Cross sectional
TEM image of the Al/SiN/n-GaAs contact, illustrating an amorphous, uniform
SiN film of the expected 2nm thickness.
2e16 cm-3 n-GaAs
n+ GaAs10 nm
Al
n-GaAs
SiN 2.1 nm300 nm
Insulator Metal
56
Insulator Thickness
Con
tact
Res
ista
nce
(log
)
RSB Branch RT Branch
Insulator Thickness
Insulator Tunneling Dominates
Barrier Height
Dominates
Con
tact
Res
ista
nce
(log
)
Optimal Thickness
RSB Branch RT Branch
4.4 Electrical Characterization
4.4.1 Contact Resistance Measurement The contact resistance (RC) of the MIS can be modeled as two resistances in series:
(1) RT, a tunneling resistance through the insulator, and (2) RSB, a resistance associated
with the barrier. With no insulator, the highly pinned Schottky barrier causes RSB to
dominate RC. With a thin insulator present, assuming a reduced ΦB,eff, the lower RSB
would reduce the overall RC. However, as the insulator thickness is further increased, the
current becomes tunneling limited and the increasing RT begins to dominate, resulting in
a high RC. Figure 4.7 illustrates the overall expected RC vs. tINS curve provided that the
effective barrier height is successfully reduced. A tradeoff exists between a reduced ΦB,eff
and an increased RT, where there exists an optimal tINS to minimize RC.
Figure 4.7. (a) The RSB branch decreases with insulator thickness as ΦB,eff
reduces, while the RT branch increases with thickness due to tunneling limitations.
(b) Schematic of RC vs. tINS after RT and RSB are connected in series. There exists
an optimal insulator thickness for minimal contact resistance, which arises from
the tradeoff between a reduced barrier and and an increased tunneling resistance.
(a)
(b)
57
RC was measured using the contact end resistance method [32] with the setup
shown in Figure 4.8a. Since this is not a simple two terminal method, the absolute
current and voltages used in the measurement will change with the contact resistance. In
the contact end resistance method, current is forced through two contacts and the voltage
drop is measured across another two, where the contact resistance is given by : RC = ∆V/I.
According to Schrӧder [32], the applied current should be varied such that the voltage
drop is only a few tens of mV. The measured contact resistance of a Al/SiN/n-GaAs diode is shown in Figure
4.8b, and is found to display the expected RC vs. tINS curve. One key point is the existence
of a minimum RC for tINS > 0, which proves successful reduction in ΦB,eff, or else RC
would only increase with tINS. The optimal tINS is found to be about 2nm, but this could
depend on the metal, dielectric, and semiconductor used.
Figure 4.8. (a) RC measurements using the contact end resistance method [32].
Figure from Ref#[71]. (b) RC ratios are taken relative to the Schottky case. The
Al/SiN/n-GaAs MIS shows the expected RC tradeoff with dielectric thickness.
It should be noted that these MIS contacts have been made on low doped
substrates to minimize the tunneling current through the barrier and to emphasize the
thermionic emission current over the barrier. This allows for a more accurate extraction
of the barrier height and highlights the effect of changes in ΦB,eff. However, low doping
results in higher RC, so RC ratios taken relative to the Schottky case, are reported here.
Much lower absolute RC can be achieved by simply increasing the doping.
Rsh
Rc Rc
VI
Substrate
Metal pad
SiN
0 1 2 3 410-3
10-2
10-1
100
Cont
act
Resi
stan
ce R
atio
Dielectric Thickness (nm)
Al/SiN/GaAs(a) (b)
58
4.4.2 Diode Current Measurement
Diode current was measured for back-to-back Schottky diodes to eliminate the
large resistance contributions from the series resistance and the back contact resistance
due to the lightly doped substrate. The back-to-back diode measurement is illustrated in
Figure 4.9a, where in both positive and negative biasing only the reverse current is
measured. Fortunately, the ΦB,eff modulation is mostly reflected through changes in the
reverse current, where maximum reverse current is desired for ohmic contacts. As shown
in Figure 4.9b for an Al/SiN/n-GaAs diode, by simply increasing the SiN thickness, the
reverse current is transformed from rectifying Schottky behavior, to increased conduction,
to tunneling limited, where the arrow indicates the direction of change. In fact, the
reverse current for a Al/SiN(3.6nm)/n-GaAs is greater than that of a Al/n-GaAs Schottky
diode, clearly indicating a reduction in ΦB,eff with a non-zero SiN thickness. Otherwise,
with no change in the effective barrier height, the reverse current should only decrease
with increasing SiN thickness, due to the thicker SiN tunnel barrier.
Figure 4.9. (a) Illustration of the back-to-back diode measurement setup where
only the reverse current is measured. (b) Back-to-back Al/SiN/n-GaAs diode
measurements demonstrate the effective modulation of ΦB,eff by the SiN thickness.
Figure 4.16. Effective barrier height vs. metal work function for Schottky diodes
and MIS contacts. There is a roughly parallel shift in ΦB,eff independent of ΦM.
The overall change in the barrier heights of Schottky barriers (without SiN) and
MIS contacts (with SiN) are summarized in Figure 4.16Figure 4.. Initially, the GaAs
surface is strongly pinned between 0.6 to 0.8 eV, but after inserting SiN, ΦB,eff is reduced
to 0.2 to 0.4 eV. However, even though ΦB,eff is reduced, the surface is still strongly
pinned because ΦM varies by 1.5 eV but ΦB,eff only changes by 0.2 eV. The reasoning
behind the change in barrier height will be discussed in detail in the following chapter. The lowest achieved barrier height is 0.18eV using Er, and even though it is a
significant reduction from the pinned 0.75eV, it is still far from the desired near zero
barrier height. As mentioned in the beginning of this section, the reported ΦB,eff is related
to the electrical behavior and not the actual difference in the Fermi level between the
metal and semiconductor, as traditionally defined for Schottky barriers. In fact, the
measured effective barrier height is actually larger than the actual barrier height, and this
can be understood by looking at how ΦB,eff is extracted. From the equations in Figure
4.14c, ΦB,eff is measured through how much the current changes with temperature. For a
greater change per change in temperature, ΦB,eff is smaller. However, MIS contacts have a
tunneling current through the insulator component that doesn’t change with temperature.
In this case, if the tunneling resistance dominates and the current is attenuated, then there
is less change with temperature and ΦB,eff is larger. When the tunneling current is small,
the extracted value should not be affected.
4.4.5 Effect of Insulator Material
The effect of the dielectric on the MIS contact is studied first by comparing the
use of Al2O3 and SiN. Figure 4.17 explores the RC and tINS tradeoff, where SiN appears
to be the better candidate for contact applications due to its lower achievable RC. The one
order of magnitude lower RC of SiN suggests it may be possible to achieve an even RC
with the use of alternative dielectrics. The results also highlight the large effect of the
band offset on the tunneling resistance RT in the MIS structure. The band offsets of Al2O3
66
(∆EC=2.75eV) and SiN (∆EC=1.5eV) only differ by 1.25eV, but the intrinsic exponential
dependence of the tunneling current on the potential barrier amplifies this difference.
Figure 4.17. Comparison of the RC vs. tINS tradeoff for SiN and Al2O3. SiN appears to
be the better candidate for contact applications due to its lower ∆EC of 1.5eV.
To further understand the RC tradeoffs involved, additional dielectrics (HfO2,
ZrO2 and TiO2) are investigated in Figure 4.18a. It is rather surprising that all of the MIS
formed using these dielectrics show a reduction in RC and ΦB,eff. It appears that the GaAs
effective barrier height can be tuned by using many different dielectrics, broadening the
applicability of these contacts. However, each of the dielectrics has a different RC
tradeoff, so the minimum achievable contact resistance depends on how the dielectric
material affects the RSB and RT branches. The RT branch is limited by tunneling through
the dielectric barrier, where the tunnel barrier height depends on the dielectric to
semiconductor ∆EC (Figure 4.18). Materials with a lower ∆EC can reduce the slope and
shift the RT branch outwards to the right (Figure 4.18c). The ∆EC for these materials are
provided in Chapter 2. The effect of the dielectric on RSB depends on the amount of
reduction in ΦB,eff, so if the underlying mechanism is due to an interface dipole, then a
larger dipole would give RSB a steeper slope and shift outwards towards the left. The
ideal dielectric would be one that has a larger ∆ΦB,eff and zero or even negative band
offset (∆EC for n-type and ∆EV for p-type) to reduce the tunneling penalty on RC. Of the
investigated materials, TiO2 formed the best single dielectric MIS because it has both a
0 1 2 3 410-3
10-2
10-1
100
101
Cont
act
Resi
stan
ce R
atio
Dielectric Thickness (nm)
Al/Al2O3/GaAs Al/SiN/GaAs
67
large dipole and a small conduction band offset.
Figure 4.18. (a) RC vs. tINS tradeoff between different dielectrics for
Al/dielectric/GaAs MIS. (b) The tunneling barrier height depends on the
dielectric/semiconductor conduction band offset. (c) Dielectric materials affect
both the RSB and RT branches, so the tradeoff for each dielectric depends on the
dipole magnitude and the ∆EC. See Chapter 2 for the measured ∆EC values.
4.4.6 Summary
Figure 4.19 summarizes how changing the various material parameters affects the
overall RC vs. tINS tradeoff. For an ultra low contact resistance on n-type substrates, a
0 1 2 3 4
Contact R
esistance Ra
tio
Dielectric Thickness (nm)
Al2O3SiNTiO2HfO2ZrO2
Al2O3SiNTiO2HfO2ZrO2
102
101
100
10‐1
10‐2
10‐3
10‐4
10‐5
∆EC Tunnel Current
Insulator Thickness
Con
tact
Res
ista
nce
(log
)
RSB Branch RT Branch
ΔEC ↓Dipole↑
(b) (c)
(a)
68
combination of high electrically active doping, low metal work function, and low tunnel
barrier heights area necessary for an overall low effective barrier heights.
Figure 4.19. Schematic of RC vs. tINS. The effect of different metals, dielectrics,
and substrates on the tradeoff between RC and insulator thickness is shown.
4.5 III-V MOSFET S/D Contacts After studying the MIS contact on GaAs, we turn to more technologically relevant
higher electron mobility material InGaAs. The substrate composed of a 300nm thick
(doping density of 1x1016 cm-3) MBE grown In0.53Ga0.47As that is lattice matched to the
InP wafer (Figure 4.20a). The MIS is fabricated in a similar fashion to the GaAs MIS
contacts, with the exception of an ammonium hydroxide NH4OH passivation using 1:1
DI water diluted solution for 5 min rather than the HCl + (NH4)2S step. Although sulfur
also passivates the InGaAs surface, the use of HCl is undesirable because it etches the
InP substrate rather quickly and can significantly roughen up the back of the samples
making it difficult to use the substrate for a back contact. The etch products could also
potentially redeposit on the InGaAs surface. The RC vs. tSiN for the InGaAs MIS (Figure 4.20b) shows a similar trend as the
GaAs MIS in contact resistance and barrier height reduction. However, the contact
resistance is only reduced by one order of magnitude because InGaAs is a more
conductive material with a smaller bandgap of 0.75eV as compared to the 1.42eV of
Insulator Thickness
NominalRSB
Con
tact
Res
ista
nce
(log
)
Lower RT : Doping ↑
Higher RT :ΦM↑ or ∆EC↑
69
GaAs. The Fermi level of InGaAs also pins closer to the conduction band than GaAs
indicates the successful reduction in barrier height.
Since the InGaAs MIS has been shown to shift the metal/semiconductor Fermi
level, the next step is to apply this non-alloyed, highly scalable MIS contact to an
In0.53Ga0.47As MOSFET and demonstrate the compatibility of the non-alloyed contact
technique with existing III-V MOSFET fabrication. This is an important step forward as
any proposed process module must have a demonstrated path for being incorporated in a
fully integrated device process flow.
For the implementation of this MIS S/D contact structure, gate last In0.53Ga0.47As
MOSFETs with a Ni/Al2O3/InGaAs gate stack were fabricated (Figure 4.21). The
channel material was MBE grown p-type In0.53Ga0.47As (Be-doping of 6x1015 cm-3) in-
situ capped by 50nm of arsenic to prevent oxidation. After an organics degrease, samples
were loaded into an atomic layer deposition (ALD) chamber and the As capping layer
was desorbed at 400oC for 5 min, followed by 30nm of Al2O3 deposited at 300oC using
trimethyl-aluminium (TMA) and H2O precursors to serve as a sacrificial implantation
oxide. The samples were then patterned and wet etched to define mesas for device
isolation and fabrication of contact resistance structures. S/D regions were selectively
implanted with Si at 30keV and 80keV with a dose of 2x1012cm-2, then rapid thermal
annealing (RTA) activated at 600oC for 30s in N2. The 30nm thick Al2O3 capping layer is
critical in preventing arsenic desorption from the InGaAs surface. The sacrificial
Insulator
1e16 cm-3 n-InGaAs
1e16 cm-3 n-InAlAs
n+ InP
100 nm
300 nm
0 1 2 3 4 5
10-1
100
Cont
act
Resi
stan
ce R
atio
SiN Thickness (nm)
Al/SiN/In0.53Ga0.47As(a) (b)
70
implantation oxide was then stripped in 2% HF, followed by native oxide removal in
NH4OH immediately prior to loading in the ALD chamber for 10nm of Al2O3 gate oxide.
Figure 4.21. Schematic view of the fabricated InGaAs MOSFET with 10 nm
ALD Al2O3 gate oxide. Cross-hatched area represents the implanted regions.
Next, a 75nm Ni gate electrode was lift-off patterned and e-beam evaporated. A 50nm
Al2O3 field oxide was used for further device isolation and contact area definition. After a
(NH4)2S sulfur treatment, an ultrathin amorphous silicon nitride was sputtered from a
Si3N4 target at 200oC, followed by Al evaporation for S/D contacts. Circular transmission line method (TLM) structures were used to characterize the
contacts because they have the advantage of self isolation [32] so current can only flow
from the central contact to the surrounding contact. The TLM was fabricated together
with the MOSFET Source/Drain contacts and should reflect the behavior of the S/D
contacts. Different gap sizes between contacts pads were used with dimensions of 5, 10,
15, 20, 25, 30, 40, and 60 μm. The results were quite linear, as shown in Figure 4.22a.
Contact resistance measurements of the different MIS contacts show a similar RC
vs. tINS trend as observed in the diode structure (Figure 4.22b). However, the lowest
achieved ρC of 2.9x10-3 Ω-cm2 still remains fairly high due to the low S/D doping implied
from the large parasitic resistance (RSD) of 90 Ω-mm, extracted by plotting total
resistance (RTOT) vs. gate length (LG), where RTOT = VD/ID in the linear operation [32]
(Figure 4.22c). The S/D active doping is calculated to be between 1.6x1016 and 2.5x1016
cm-3 using the measured sheet resistance of 1300 Ω/, simulated junction depth of 200 -
300nm from SRIM (Stopping and Range of Ions in Matter)[77] , and doping dependent
S/D to G spacing = 1, 2, or 4μm
p‐InGaAs(6x1015 cm‐3)
p+ InP Substrate
300 nm
p‐InGaAs (Be doped 1x1017 cm‐3) 200 nm
S DG
Isolation Oxide
10nm Al2O3Gate OxideB
m
d
im
in
u
w
m
m
(
(
mobility from
opants is in
mprove dop
nduces nega
sing a fully
with higher d
Figure
results
of diff
fairly g
Electr
measurement
midgap inter
0.
3.0x10
6.0x10
9.0x10
1.2x10
1.5x10
Tota
l Res
ista
nce
(Ω)
a)
(c)
m a Caughe
nsufficient,
ant activatio
ative charge
self-consist
doping, partly
e 4.22. (a) Ci
s show similar
ferent dimens
good gate sta
rical charact
ts of MOSCA
rface trap de
0 10 20.0
02
02
02
03
03
Dis
ey-Thomas
but as men
on, but will
s and interf
tent NEGF s
y due to the
ircular TLM d
r RC trends as
ions. (d) MO
ck with a mid
terization of
APs (Figure
ensity (DIT)
0 30 40 50stance (μm)
71
based mode
ntioned earl
l also cause
face traps w
showed that
thinner optim
data illustrati
s from diodes
OSCAP C-V fr
dgap DIT of 1.
f the fabrica
e 4.22d) illus
) of 1.6 x10
0 60
el[78]. This
lier, higher
e arsenic de
which degra
t there can b
mal tINS for h
ing linearity.
s. (c) RTOT vs.
from 2kHz to
6 x1012 cm-2e
ated MOSFE
strates a fair
012 cm-2eV-1
0.0
5.0x10-3
1.0x10-2
1.5x10-2
A
Cont
act
Resi
stiv
ity
(Ω-c
m2 )
(b)
0
0.1
0.2
0.3
0.4
Capa
cita
nce
(uF/
cm2 )
(d)
level of e
temperatur
sorption in
ade the mob
be continual
higher subst
(b) TLM me
. L plot from
1MHz demo
eV-1.
ETs gate sta
rly good gate1
measured
Al Schottky Al/1.5n
-20
1
2
3
4
Volta
Ni/Al2O3/In0.MOSCAP
f = 2 kHz
tOX = 10 nm
to 1 MHz
lectrically a
re annealing
the InGaAs
bility. Simul
l reduction i
trate dopings
easurement
MOSFETs
nstrating a
ack through
e dielectric w
by the high
Al/2nm SiNnm SiN
0 2age
.53Ga0.47As
active
g can
s that
lation
in RC
s[76].
C-V
with a
h-low
72
frequency method [32]. The DIT matches those of simple MOSCAPS fabricated using
shadow masks, which suggests that the gate stack was not degraded through fabrication. MOSFET measurements of ID-VG in Figure 4.23a show an enhancement mode
device with good gate control and low gate leakage that is almost three orders of
magnitude lower than the on-current. The ID-VD in Figure 4.23b shows linear behavior in
low VD. In the case of severe current degradation by series resistance, the current
behavior at low drain biases would become quadratic because the series resistance would
overshadow any changes in the channel resistance.
Figure 4.23. Implementation of the Al/2nm SiN contact in a surface channel
enhancement mode InGaAs nMOSFET with L=10 μm and W = 320 μm. (a) The
ID-VG does not show significant gate leakage. (b) The ID-VD shows linear
behavior in low VD, whereas for severe series resistance it would be quadratic.
In our III-V MOSFET fabrication process, the processing temperature is a
limiting factor as there is a trade off with higher Si dopant activation and lower channel
effective mobility. This thermal budget limit in the dopant activation of InGaAs results in
our low active source/drain doping concentration. If the dopant activation were to
increase, the contact resistance would decrease from the larger tunneling current
component. Dopant activation may be improved by using different dopants such as Ge,
carbon, and sulfur, but we have not studied this and instead used Si because it is the most
common donor element. Another possibility is the use of metastable laser annealing to
-1 0 1 2 3 410-4
10-3
10-2
10-1
100
101
102
Al/2nm SiN ContactL = 10 μm
VD = 0 to 4VVT = 0.2 V
I D [μA
/μm
]
V G [ V ]0 1 2 3 4
0
5
10
15VG = 0 to 4V
I D [μA
/μm
]
VD [ V ]
(a) (b)
73
achieve doping levels that exceed the solid solubility limit. By using a reflective gate
metal, higher activation can be achieved without damaging the gate stack. This has been
studied recently on InGaAs [79] and Ge [80], and could greatly improve our MOSFETs. The purpose of this work is not to demonstrate the lowest possible RC on the
highest performing III-V MOSFET, but rather to prove the concept and implement this
scalable MIS contact structure for III-V MOSFETs. The scalability is a physical
scalability that arises from the absence of contact alloying. The physical contact sizes
demonstrated here are large due to equipment restrictions of a contact mask aligner for
lithography and a sputtering tool to deposit the ultrathin silicon nitride, but in principle,
with the use of better lithography tools and an ALD to deposit the silicon nitride, very
small dimensions can be achieved. We show that the MIS contact structure can be implemented in a MOSFET
structure. With our work as a starting point, there are still many more metal and
dielectric materials to be explored, and a much lower contact resistance could be
achieved using this structure with the optimal material combination.
4.6 Summary The MIS contact structure has demonstrated great promise on Si, Ge, and III-V
materials through the use of a variety of thin dielectrics to reduce the effective electrical
barrier height and contact resistance of a pure metal-semiconductor contact. The effect of
the metal work function, semiconductor doping, and insulator material have been
investigated, where the overall minimum achievable contact resistance and barrier height
depend on the material properties. For a low contact resistance, both heavy doping and
low barrier heights are required. The single dielectric MIS contact demonstrated barrier
heights as low as 0.27eV using SiN, but this can most likely be further reduced with the
use of different combinations of materials. There exists great flexibility in the choice of
dielectrics and metals for the contact design. This MIS contact structure has been
successfully demonstrated on InGaAs nMOSFETs, which can be applied to make
scalable non-alloyed ohmic contacts for other III-V semiconductor MOSFETs, and also
74
tunable barrier heights for III-V Schottky barrier FETs.
\
Chapter 5
Physical Mechanism of Single
Dielectric MIS Contacts
Expanding on the experimental results of the single dielectric MIS contacts in the
previous chapter, we discuss in detail the underlying physics for the observed barrier
height reductions. The Fermi level is discovered to be shifted rather than unpinned as
reported in Si and Ge MIS literature and summarized in Chapter 4. The effect of bulk
fixed charge in the ALD dielectric films are also studied for the first time and found to
contribute to barrier height lowering. Fixed charge in combination with interface dipoles
provide a more thorough understanding of the MIS contacts. Though this study is based
on III-V MIS, the results can be extended to the understanding of Si and Ge MIS contacts.
5.1 Introduction In the previous chapter, we demonstrated a reduction of the effective barrier
height of metal/n-GaAs and metal/n-In0.53Ga0.47As junctions using MIS contacts with a
variety of metals (Y, Er, Al, Ti, W) and dielectrics (SiN, Al2O3, TiO2, ZrO2, HfO2, ZnO).
The barrier height lowering was verified through direct measurements and deduced from
increased diode current and reduced contact resistance. The MIS contact structure allows
us to engineer non-alloyed ohmic contacts for the source/drain of III-V MOSFETs.
However, in order to do so, we need a thorough understanding of how the dielectric is
75
able to reduce ΦB,eff.
Despite of efforts by several research groups, there is still no complete
understanding of how these MIS contacts work. Two possible explanations for the
observed reduction in ΦB,eff have been reported in the Si and Ge MIS contact literature,
but there has not been a clear consensus. The explanations are heavily dependent upon
the chosen Fermi level pinning theory, where the origin of the pinning varies with the
model. The two considered here are the metal induced gap states (MIGS) and bond
polarization theories. Studying how these theories can explain the MIS contact behavior
will allow us to gain a better in depth understanding of the underlying mechanism.
5.2 Fermi-level Pinning Theories
According to the Schottky-Mott theory [67], when a metal and semiconductor are
brought into contact, the two Fermi levels align so the semiconductor Fermi level at the
interface is modified. The potential barrier ΦB between the two should ideally be set by
the metal work function ΦM and semiconductor electron affinity χe, where ΦB = ΦM – χe
for an n-type semiconductor. However, in reality, this dependence is not experimentally
observed. Schottky barrier heights tend to be pinned at a value roughly independent of
ΦM.
Figure 5.1. Experimentally measured Schottky barrier heights on n-GaAs for
different metal work functions. The metal/GaAs interface appears strongly
pinned. Figure from Ref# [4].
ND = 1 x 1016 cm-3
0.3 eV
3 eV
76
As illustrated in Figure 5.1 from the experimentally measured Schottky barrier
heights vs. metal workfunction plot, the metal/GaAs Fermi level is strongly pinned
between 0.7 and 0.9 eV. Even though ΦM varies by 3eV, the barrier height only varies by
0.3 eV, indicating the barrier height is almost independent of the metal workfunction. Currently, there exists several Fermi level pinning theories, where the origin of
the pinning states varies with the model. Two popular theories are the metal induced gap
states (MIGS) and bond polarization theories.
5.2.1 Metal Induced Gap States Theory
The MIGS theory was first proposed by Heine [68] in 1965, and later supported
by Tersoff [69]. The basis of this theory is that the tail of the electron wave functions
from the metal can decay into the semiconductor in the forbidden band gap energy range,
creating intrinsic states known as the metal-induced gap states. Near the valence band,
these states are found to be mostly donor-like, and near the conduction band they are
mostly acceptor-like. The charge neutrality level (ECNL) is then the energy level at which
the interface states change from mostly donor-like to acceptor-like. In a
metal/semiconductor junction, the charging of these states by the penetrating electron
wave function from the metal creates a dipole charge which causes the Fermi level to
align to minimize the dipole charge towards zero, effectively pulling the EF at the
interface towards ECNL. For example, if the metal EFM is initially above ECNL, then as they are brought into
contact a dipole with a negative charge on the semiconductor side would be created, as
shown in Figure 5 Figure 5.2. Since filled acceptor-like interface states result in negative
charges and empty donor-like interface states result in positive charges, the shaded area
represents the total negative charge on the dielectric side while the light-gray region
represents the total positive charge. After the metal and semiconductor are in contact,
charge transfer through emptying the acceptor states or filling the donor states will
proceed until the net charge is zero.
77
21) 0.1(1
1S−+
=∞ε
Figure 5.2. Distribution of the metal induced gap states. The left side shows the energy band diagram and the right side shows the charging of the interface. Figures from Ref# [81].
From experimental measurements, the barrier heights of large bandgap ionic
semiconductors were found to have much more dependence on ΦM than small bandgap
covalently bonded semiconductors. This was explained by the dependence of the states
on the asymptotic charge decay length λ. Ionic semiconductors have shorter decay
lengths, so there is negligible DOS away from the interface. A short λ decreases the
ability for MIGS to screen the effect of metal electronegativity, which allows ΦM to have
some modulation of the barrier height. This dependence of the Schottky barrier height on
λ can be modeled using a pinning factor S [82], where materials with a shorter λ would
lead to a larger S, and vice versa. S is empirically found to be inversely related to the
dielectric constant ε∞ and for 1 ≥ S ≥ 0, a smaller S indicates stronger pinning. As shown
in Figure 5.3, semiconductors tend to have smaller S than oxides and dielectrics, which
explains why there generally does not exist Fermi level pinning in metal/oxide junctions. To calculate the barrier height ΦB, the pinning effect can be thought of as an
effective barrier metal work function ΦM,eff in contrast to the normally referenced metal
work function in vacuum ΦM. The equations are shown below:
ΦM,eff = S ΦM + ( 1 – S ) ΦCNL
ΦB = ΦM,eff – χe
total positive charge(empty donor-like)
total negative charge(occupy acceptor-like)
78
Figure 5.3. (a) Illustration of the relation between S and ε∞. (b) The pinning
factor S ranges from 0 to 1. The slopes show that a smaller S leads to a higher
degree of pinning of EF to ECNL. Figures from Ref# [81].
5.2.2 Bond Polarization Theory
Tung’s bond polarization theory [70] is similar to the MIGS theory in the idea of
gap states being the source of Fermi level pinning. The difference in Tung’s theory from
the MIGS theory is in the idea that the gap states arise from the bond polarization of the
chemical bonds at the metal semiconductor interface, while in MIGS, it is assumed that
the distribution of gap states is determined entirely by the semiconductor with no
dependence on the metal. In actuality, there must be a rearrangement of charge in
forming the chemical bonds between the metal and semiconductor in order to satisfy
thermodynamics and the minimization of interface energy. When a semiconductor comes into contact with a metal, the two wavefunctions
interact, forming new wavefunctions at the interface where the electronic states are not
fully metal or semiconductor-like, but rather a mixture of the two. This transition layer or
interface specific region (ISR) is illustrated in Figure 5.4. The width of the ISR is
dependent upon the screening length which is usually a few lattice spacings. An
assumption of this model is that charge transfer is limited only to atoms on the immediate
interface planes. However, in reality, there is some additional chemical shift due to the
second and third neighboring planes, but it is smaller in comparison with the first
neighboring plane.
(a) (b)
79
Figure 5.4. Energy band diagram and crystal potential distribution at a metal-
semiconductor interface, illustrating the concept of the interface specific region.
Figure from Ref#[70].
When in contact, minimization of the total interface energy causes the metal and
semiconductor charge density to relax, creating an interface dipole that pins the Fermi
level. Looking more closely at ISR in Figure 5.4, μM represents the internal chemical
potential of the metal, and μS represents the internal ionization energy of the
semiconductor, both internal bulk properties. The interface dipole is represented by e∆ISR,
which is the difference between the averaged potential across the interface. The Schottky
barrier height is related through ΦB,p = EFINT
- EVBINT = μM – μS – e∆ISR .
5.3 Fermi-Level Depinning vs. Shifting When we apply these two Fermi level pinning theories to the MIS contact, each
theory has a different effect on the Fermi level. These two differ mainly in the choice of
the ideal dielectric material, how you form ohmic contacts to n-type and p-type
semiconductors, and how the metal work function affects the MIS barrier height.
In accordance with the MIGS theory, by inserting a thin insulator between metal
and semiconductor, the metal electron wave function is attenuated in the insulator prior to
penetrating into the semiconductor. This would result in fewer charges available to drive
the interface EF towards ECNL, which unpins the Fermi as shown in Figure 5.5. This
Metal Semiconductor
Interface Specific Region (ISR)
80
reasoning was used to explain the observed depinning of metal/Si [66] and metal/Ge
Fermi levels [71, 72]. The ideal dielectric would be: (1) sufficiently thick to allow the
wavefunction to decay, (2) have a large pinning factor S=1 to be more effective in
depinning the Fermi level and to minimizing potential pinning of the metal/insulator, and
(3) have ∆EC = 0 to eliminate the tunneling penalty of the dielectric. From the bond polarization theory, by inserting a thin insulator an electronic
dielectric dipole is created between the insulator and the semiconductor or native oxide
that induces a barrier shift (Figure 5.5) that shifts the Fermi level. This dipole can be
visualized as modifying the effective metal work function (ΦM,eff) and the interface
specific region, where for a given semiconductor the magnitude of the dipole effect
depends mainly on the insulator material. The ideal insulator for n-type ohmic contact
applications would be one that forms: (1) a large positive dipole equal to the pinned ΦB,
and (2) has ∆EC = 0 to reduce the tunneling penalty on RC.
Figure 5.5. Schematic band diagrams: (a) Schottky barrier with a pinned Fermi
shifting through dipole formation at the interface
Metal Semiconductor
ΦB
ECEF
EV
Metal
Tunneling Current
ΦB,eff
Insulator
Semiconductor
+ -
EC
EV
(a) (b) (c)
Pinned Fermi level Unpinned Fermi level by MIGS reduction
Shifted Fermi level by dipole formation
81
The MIS contact behaviors under the two theories differ in how the ohmic
contacts to n-type and p-type semiconductors are made (Table 5.1). In the case of Fermi-
level depinning, the same dielectric that unpins the Fermi level would be used, followed
by low ΦM metals such as Al and Ti for n-type contacts to tune the barrier height towards
0, and high ΦM metals such as Au and Pt for p-type contacts. n the case of Fermi-level
shifting, the metal work function is not as critical. Instead, the dielectric properties are
more important in creating n-type and p-type contacts. Different dielectrics are needed to
create dipoles pointing to opposite directions to either shift the Fermi level towards the
conduction or valence bands.
Fermi-Level Depinning Fermi-Level Shifting
Theory MIGS Bond Polarization
Ohmic contact for n-type and p-type
Different metal, same dielectric. Same metal, different dielectric.
n-type Low WF metals (Al, Ti) Dielectrics that shift EF towards E
C
p-type High WF metals (Au, Pt) Dielectrics that shift EF towards E
V
Effect of ΦM on ΦB,eff
ΦB,eff
is modulated by the metal workfunction.
Roughly constant change in ΦB,eff
that is independent of the metal.
Table 5.1. Summary of how Fermi level depinning and shifting affect the MIS contact behavior.
To test the MIGS Fermi level depinning theory, p-type MIS contacts are
fabricated using high ΦM metal Pt with dielectrics known to reduce ΦB,eff in n-type MIS
contacts. Figure 5.6 shows the Rc vs. insulator thickness plot for Pt/TiO2/p-GaAs and
Pt/HfO2/p-GaAs MIS contacts. Unlike the n-type MIS contacts, RC only continuously
increases with insulator thickness which indicates there is no reduction in the barrier
height. If there were a ΦB,eff reduction, there would be a decrease in RC resulting in an
optimal insulator thickness. Since Pt with a high ΦM near the GaAs valence band edge
was used, the surface does not appear to be unpinned. Although the difference in ∆EC
amd ∆EV could be a factor, it is possible that there is a dipole created at the
dielectric/semiconductor interface that shifts the Fermi level towards the conduction band.
This can explain the favorable n-type and unfavorable results on p-type MIS contacts.
82
Figure 5.6. P-type MIS contacts do not reduce ΦB,eff, suggesting the Fermi level
is shifted towards the conduction band by the dielectrics, rather than depinned.
To further investigate the differences between the two theories, the effect of the
metal work function on the effective barrier height is studied. If the Fermi-level is
depinned, then the MIS ΦB.eff should be tuned by ΦM through the relation ΦB,eff = ΦM - χe,.
On the other hand, if the Fermi-level is shifted in the MIS contact, then there would be a
roughly constant change in the Schottky barrier and ΦB,eff that is independent of ΦM. To
study this, metal/SiN/n-GaAs MIS using Y (ΦM = 3.1eV), Er (ΦM = 3.1eV), Al(ΦM =
4.1eV), Ti(ΦM = 4.3eV), and W (ΦM = 4.5eV) were fabricated, and the effective barrier
heights measured as described in the previous chapter. Figure 5.7 plots the measured
barrier height vs. metal work function for the Schottky and MIS contacts. The ΦB,eff
reduction appears to be roughly 0.4eV to 0.5eV for all samples independent of the pinned
ΦB and ΦM used, which agrees with the expectation of a constant dipole magnitude that is
independent of the metal, and only dependent upon the insulator/semiconductor interface
properties. The shift for Er and Y metals is slightly greater at 0.51eV, but this may be due
to the high reactivity of the metals, where possible oxidation may alter the interface. It is
important to note that despite a reduction in ΦB,eff, the surface is still strongly pinned
since ΦM varies by 1.5eV but ΦB,eff only changes by 0.2eV. The surface is now pinned at
a location closer to the conduction band.
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
0 0.5 1 1.5 2 2.5
Contact R
esistance Ra
tio
Dielectric Thickness (nm)
Pt / TiO2 / pGaAsPt / HfO2 / pGaAs
83
Figure 5.7. The roughly parallel shift in ΦB,eff independent of ΦM confirms the
dielectric dipole induced shift of roughly 0.4 to 0.5eV.
The extracted ΦB,eff for different ΦM do suggest the formation of an electric dipole,
and this dipole could arise from differences in oxygen density as reported in Si MIS [75].
For the sputtered SiN on GaAs, the structure is more accurately represented by
metal/SiON/native oxide/GaAs. Through XPS, the SiN film was found to contain roughly
15% oxygen due to the residual oxygen present in the chamber and in the Ar/N2 gases
used in sputtering. The sulfur passivation may lead to a reduction of the oxygen density at
the direct interface, in which case differences in the oxygen density can lead to charge
transfer from SiON to the GaAs native oxide, creating the observed positive dipole. However, the similarity in the reduction of ΦB,eff in Al/Al2O3/GaAs and
Al/SiON/native oxide/GaAs structures despite very different interfaces suggests a
possible alternative mechanism. ALD Al2O3 has been found to have a “self-cleaning”
effect on the III-V native oxide where As2O3 and GaO are removed through a ligand
exchange process, so very minimal native oxide remains at the Al2O3/GaAs interface [43].
The same is true for ALD HfO2 on GaAs. In contrast, sputtered SiN most likely leaves
the surface with native oxide and some sputtering damage. ALD TiO2, ZrO2, and ZnO
may have surfaces in between the two cases. For these dissimilar interfaces essentially
with and without oxygen to have the same positive dipole, both need transfer of oxygen
atoms from the dielectric to GaAs or native oxide. The considerably different interfaces
therefore suggests that there may be another reason for the observed ΦB,eff reduction.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
3 3.5 4 4.5 5
Barr
ier
Hei
ght (
eV)
Metal Work Function (eV)
Metal/n‐GaAs Schottky DiodeMetal/SiN/n‐GaAs
Y, Er Al Ti
W
0.51 eV0.40 eV
0.41 eV
0.38 eV
84
5.4 Fixed Charge
Even though the MIS contact behavior appears to be due to Fermi-level shifting,
the exact origin of this shift in Fermi level is not well understood. A dipole at the
dielectric/semiconductor interface is a possibility, but from the bond polarization theory,
the dipole should only be created at the interface and determined by only a few atomic
planes. If the dipole is determined by a few layers of material, then the optimal
thicknesses should be much smaller than the experimentally found 2nm.
Furthermore, the MIS contacts behavior appears to be independent of the different
pre-ALD surface passivation (Figure 5.8). Al/TiO2/n-GaAs MIS fabricated using
ammonium hydroxide and ammonium sulfide surface passivation have very different
interface properties, yet they display nearly the same RC vs. insulator thickness tradeoff.
(NH4)2S passivation leaves the surface As rich and with Ga-S termination [27], while
NH4OH leaves the surface fairly stoichiometric. If the Fermi level shifting were due to
only a dipole at the interface, then the interface properties should have a large effect on
the dipole magnitude, barrier height reduction, and contact resistance.
Figure 5.8. The RC vs. TiO2 thickness tradeoff plot for Al/TiO2/n-GaAs MIS
contacts appears to be independent of the surface passivations.
0 1 2 3 4
Contact R
esistance Ra
tio
TiO2 Thickness (nm)
Al/TiO2/nGaAs
250C NH42S
250 NH4OH (NH4)2 S PassivationNH4OH Passivation
100
10‐1
10‐2
10‐3
10‐4
10‐5
85
The combined reasoning of : (1) optimal thickness more than a few atomic planes,
(2) similar behavior of MIS with different dielectric/semiconductor interfaces, and (3)
barrier height reduction independent of native oxide presence all suggest that dipole
formation at the dielectric/semiconductor interface cannot be the sole reason for the
Fermi level shift. This implies there is another element that has not yet been considered. From the material properties studied in Chapter 2, the ALD dielectrics were
mostly found to be non-stoichiometric throughout the film. In the case of Al2O3, instead
of the ideal crystalline O to Al ratio of 1.5, the ratio was measured to be 1.82 with 35.4%
Al 2p and 64.6% O 1s atomic concentrations. The film density of 3.04 g/cm3 is also
significantly lower than the reported 3.9 g/cm3 of bulk crystalline Al2O3 [83]. As with the
stoichiometry and density, the measured bandgap of 6.4eV is also smaller than the ideal
crystalline value [38] of 8.7eV. These structural non-idealities can affect the electrical
properties of the film through the presence of defects that leave the film oxygen rich and
electrically behave as fixed charge. It seems that the dielectric properties itself can be an
important factor. Since it is not possible to extract QF in ultrathin MIS, MOSCAPs with
thicker dielectric were used as a vehicle to extract these values. To investigate the electrical non-idealities caused by fixed charge present at the
insulator-semiconductor interface and inside the film, C-V characteristics of as-deposited
Pt/Al2O3/n-InGaAs MOSCAPs with 50, 75, and 100 cycles of ALD Al2O3 were measured
in Chapter 3. Fixed charge densities were extracted from the VFB dependence on oxide
thickness. As deposited ALD film had a significant amount of positive bulk fixed charge
(QF = 1.9x1019 cm-3), and after FGA annealing at 300oC for 30min, the dangling bonds
were passivated and the fixed charges were minimized (QF = 4.1x1018 cm-3). To understand how the positive fixed charge in the oxide would affect the MIS
contacts, Al/Al2O3/GaAs MIS were also annealed in FGA to remove QF. Al metal spiking
through the ultrathin Al2O3 was a concern, but it didn’t appear to be an issue. If there
were metal spiking, the contacts would have a Schottky behavior independent of the
Al2O3 thickness, but a dependence on the thickness was observed. Figure 5.9 illustrates
how the RC vs. Al2O3 thickness tradeoff changed after annealing. As deposited, there
86
exists an optimal thickness for minimal RC which indicates a reduction in ΦB,eff. After
FGA, the MIS contact behavior changed entirely. There is no longer a decrease in RC
which implies that there is also no reduction of ΦB,eff in the annealed MIS. The
monotonic increase of RC after annealing is due to the tunneling limitation the oxide
imposes on the current conduction, but the slope of the tunneling resistance limited
branch in the RC trade-off appears less steep after annealing. This is possibly due to a
change in the tunneling barrier either by changes in the band structure or densification of
the film. The presence of fixed charge appears to be responsible for the observed
reduction in the barrier height using ultrathin insulators.
Figure 5.9. After removing the positive fixed charge in Al/Al2O3/n-GaAs MIS by
annealing in FGA at 300oC for 15 min (a) there is no longer a reduced barrier
height so the tunneling resistance branch dominates, and (b) the current decreases.
0.0 0.5 1.0 1.5 2.0
Contact R
esistance Ra
tio
Al2O3 Thickness (nm)
FGA Annealed
As Deposited
103
102
101
100
10‐1
10‐2
10‐3
-1 -0.5 0 0.5 1
10-8
10-6
10-4
10-2
100
Voltage [V]
As DepositedSchottky
FGA 300oC10Å Al2O3
As Deposited10Å Al2O3
100
10-2
10-4
10-6
10-8
-1 -0.5 0 0.5 1
(a)
(b)
|Current| [A/cm
2 ]
Voltage [V]
87
To verify the effect of QF, MIS contacts were fabricated using different ALD
Al2O3 deposition temperatures, where lower temperature film results in more positive
fixed charge [84]. In comparing the 250oC and 300oC samples (Figure 5.10), the 250oC
film with higher QF achieved an overall lower RC. This further supports the idea of QF
modulating the barrier height on the semiconductor side. However, it is unlikely that all
the observed MIS contact behavior is due to positive/negative bulk or interface fixed
charge since materials can have a wide range of defects and impurities.
Figure 5.10. Al/Al2O3/n-GaAs RC vs. tINS comparing samples with ALD deposition
temperatures of 250 and 300oC. The lower RC in the 250oC sample with more fixed
charge further verifies the importance of positive QF in the ΦB,eff reduction.
For example, in the case of HfO2, the flatband voltage of as-deposited MOSCAP
C-Vs with different oxide thicknesses are aligned (Figure 5.11a), which shows a minimal
amount of fixed charge is present in the HfO2 film. However, after annealing the
Al/HfO2/GaAs MIS in FGA, there is also a sharp increase in RC (Figure 5.11b) even
though there is no significant amount of fixed charge to be removed by the FGA. From
the MOSCAP studies in Chapter 2, FGA reduces not only QF but also DIT. In the case of
MIS, during FGA annealing, hydrogen could also be passivating the dangling bonds at
the dielectric/semiconductor interface which would change or remove the interface dipole.
The overall mechanism of MIS contacts seems to be a combination of fixed charge and
dipoles, dependent upon the specific dielectric material used.
0.0 0.5 1.0 1.5 2.0 2.5
Contact Re
sistan
ce Ratio
Al2O3 Thickness (nm)
T = 300oCLess Fixed Charge
T = 250oCMore Fixed Charge
100
10‐1
10‐2
10‐3
88
Figure 5.11. (a) Pt/HfO2/InGaAs MOSCAP C-Vs for different oxide thicknesses.
The VFB does not have a thickness dependent shift so there should be minimal
amount of fixed charge in the film. (b) After annealing in FGA at 300oC for 15
min, the Al/HfO2/n-GaAs MIS contact resistance increased greatly.
Band diagrams are used to illustrate the overall effect of dipoles and fixed charge
on Schottky (Figure 5.12a) and MIS contacts (Figure 5.12b). The current reported MIS
interface dipole models [75, 85] can explain the observed reduction in ΦB,eff by modeling
the dipoles as changes in the vacuum level (Figure 5.12c), where in the case of extremely
large dipole magnitudes the surface will be in accumulation (Figure 5.12d). However,
this same effect on ΦB,eff can also be achieved using positive fixed charge to increase the
amount of potential that is dropped across the insulator to reduce the semiconductor
-4 -2 0 2 40.2
0.4
0.6
0.8
1
Cap
acita
nce
/ Cm
axVoltage
7.5 nm10 nm12.5 nm
Pt / HfO2/InGaAsMOSCAP
As Deposited
0 1 2 3
Contact R
esistance Ra
tio
Dielectric Thickness (nm)
Al / HfO2 / n‐GaAs
FGA 300oC
As Deposited
103
102
101
100
10‐1
10‐2
10‐3
(a)
(b)
89
(a) Schottky (b) MIS (c) Small (d) Large Barrier Contact Dipole Dipole
(e) Small (f) Large (g) Moderate Fixed Charge Fixed Charge Charge + Dipole
Figure 5.12. Schematic band diagrams illustrating how the presence of electronic
dipoles and fixed charge can affect ΦB,eff. (a) A Schottky barrier with a large
depletion width in the semiconductor. (b) In the MIS structure, some of the
potential is dropped across the insulator, which reduces the depletion width and
semiconductor barrier height. (c) A small electronic dipole at the
insulator/semiconductor interface can cause a change in the vacuum level. (d) A
larger dipole can in fact push the semiconductor surface to be in accumulation.
(e) With fixed charge in the oxide, more potential is dropped across the insulator
and the barrier height is reduced. (f) A larger amount of fixed charge amplifies
the effect and can induce negative charge in the semiconductor. (g) If both fixed
charge and interface dipole are present, then there is a further reduction in ΦB,eff.
++++ΦB
++ +++
EVAC
ECEF
EV
+++++
+++ ++ΦB,eff +
+++ ++++
ΦB,eff++++
+ -+
+ -ΦB,eff
ΦB,eff
++++
+++
+++ + ΦB,eff
+
+++
++
+++
++
+
ΦB,eff
+++++++++
++
+
++ -
90
depletion charge (Figure 5.12e). In the case of extremely large amount of positive fixed
charge, the effect is amplified and electrons can be induced to the surface, bringing the
semiconductor into accumulation (Figure 5.12f). For the cases of large dipole or large
fixed charge where the surface is in accumulation, the tunneling distance through the
semiconductor is greatly reduced from the Schottky barrier case, particularly for low
doped substrates. Depending on the depletion width and Schottky barrier height, by
reducing the tunneling distance through the semiconductor, the tunneling penalty through
the insulator is reduced, which further increases the overall current and decreases RC.
From the known non-idealities in the dielectric, the Al/Al2O3/GaAs MIS behavior
appears to be due to the presence of QF, whereas the Al/HfO2/GaAs MIS behavior is due
to dipole formation. The situation for other dielectrics is unclear as each material needs to
be studied in detail. The overall effect of dipoles and fixed charge can be additively or
subtractively combined, depending on the direction of the dipole and the sign of QF, so
the MIS behavior can also be due to a combination of the two (Figure 5.12g).
5.5 Discussion In efforts to elucidate the ΦB,eff reduction, the MIS contact has been modeled and
compared with reported experimental results [86, 87]. Lin et. al modeled the mechanism
as a combination of Fermi level depinning and the presence of an interfacial dipole due to
polar/non-polar surfaces [86], and Wagner et al. used the MIGS theory to model two
dipoles at both the metal/insulator and insulator/semiconductor interfaces [87]. These
explanations can provide the basis for an initial understanding of the experimental
observations, but the dielectrics in these theoretical works were assumed to be ideal,
crystalline structures. In reality, as illustrated in this chapter, these dielectrics are non-
ideal, non-stoichiometric amorphous materials that could have a significant amount of
defects and impurities. These structural non-idealities of the film: oxygen rich
stoichiometry, low density, and smaller bandgap indicate that the material properties are
difficult to model, whereby use of the ideal crystalline properties may result in very
different electrical behavior of MIS contacts.
91
5.6 Summary We investigated how the two Fermi level pinning theories would affect MIS
contacts. Under the MIGS theory the Fermi level would be unpinned by the MIS, and
under the bond polarization theory the Fermi level would be shifted by the creation of an
interface dipole. Looking at n-type versus p-type MIS contacts, it was discovered that the
lack of a barrier height reduction in p-type contacts could be due to a shift in the Fermi
level towards the conduction band. Fermi level shifting was further confirmed through a
study of MIS ΦB,eff vs. ΦM where inserting the ultrathin dielectrics reduced the barrier
heights by a constant amount across all ΦM, so ΦB,eff was not tuned by ΦM. Across all the
studied dielectrics, the presence of native oxide or use of different surface passivations
did not seem to affect the MIS contact behavior, alluding to a missing factor. After
evaluating the physical non-idealities of the ALD Al2O3 film through stoichiometry,
density, and bandgap measurements, the structural non-idealities were found to
electrically manifest as bulk and interface fixed charges that contribute to the observed
barrier height reduction. The effect of fixed charge has not been considered before and
combined with interface dipoles provides a more thorough understanding of the MIS
contacts. Though this study was based on III-V MIS, the results can be extended to the
understanding of Si and Ge MIS contacts.
5.7 Future Work To better understand the underlying mechanisms behind the barrier height
reduction in MIS, further materials characterization of dielectrics would be helpful to
understand which MIS are dominated by fixed charge and which are dominated by
electronic dipoles. A thorough study of the effect of the deposition temperature for
different dielectrics on MIS and MOSCAPS for the different dielectrics would also be
helpful in quantifying and distinguishing between bulk and interface fixed charges. The
exact origin of the dielectric/semiconductor dipole is still unknown, and study of the
interface dipoles in GaAs MOSCAPs can assist in the understanding.
92
In this chapter, the effect of thermal annealing on MIS was studied for the first
time. These results show that FGA annealing which is commonly used in CMOS
fabrication to improve the gate stack can drastically increase the RC of MIS contacts. This
can potentially limit the application of MIS contacts to MOSFETs, so a more detailed
study of the allowed thermal budget is necessary in order to understand how these
contacts could be integrated into CMOS. Also, a thermal annealing study of a wider
range of dielectrics could be helpful in finding if there are any dielectrics where the
contact resistance reduces with annealing.
93
Chapter 6
Bilayer Dielectric MIS Contacts
In this chapter, we expand on the previous chapter’s use of single dielectric MIS contacts
to include bilayer dielectric MIS to continue to shift the Fermi level and to reduce the
contact resistance. ALD HfO2, Al2O3, TiO2, and ZrO2 are chosen to form the bilayer high-
κ dielectric stacks. In studying high-κ/high-κ interfaces, we find that despite a thicker
dielectric, there is further reduction in ΦB,eff beyond that of a single dielectric, which can
be explained by the formation of a high-κ/high-κ dipole. This MIS structure provides
great flexibility in the design of source/drain contacts for III-V transistors.
6.1 Introduction The single dielectric MIS has been investigatred in the previous chapter to
alleviate the metal/semiconductor Fermi level pinning on Ge [71-74], GaAs [85], InGaAs
[85, 88], and GaSb [89] using a variety of high-κ dielectrics. More recently, Coss et
al.[75] used bilayer dielectrics AlOx/SiOx and LaOx/SiOx to shift the Fermi level towards
the valence band and conduction band to reduce the metal/n-Si and metal/p-Si effective
barrier heights (Figure 6.1). The authors explained this was due to electronic dipole
formation between the high-κ and SiO2, where the AlOx/SiOx and LaOx/SiOx form
dipoles pointing in opposiite directions. These bilayer MIS contacts were integrated on
FinFETs as a single metal dual dipole source/drain contacts for NMOS and PMOS. From
the ID-VD curves the samples with the MIS contacts had much higher current indicating
lower contact resistance than the control contacts without dielectrics. The use of bilayer
dielectrics to create electronic dipoles to further shift the Fermi level pinning seems
94
promising is obtaining ohmic contacts. Prior to this work, the use of bilayer dielectrics
had not been studied on III-V semiconductors.
Figure 6.1. (a) Schematic of the investigated bilayer dielectrics. (b) Illustration of how the high-κ/SiO2 dipoles affect the band alignments. (c) Extracted barrier heights for varying dielectric thicknesses show the Si Fermi level is tuned towards the conduction and valence bands. (d) ID-VD of FinFETs comparing the effect of MIS and the control contacts. The lower contact resistance of the MIS translates into higher drive current. Figures are from Reference#[75].
6.2 Background Electronic dipoles at high-κ/SiO2 were first discovered when high-κ dielectrics
were integrated into the Si CMOS gate stack to scale down the effective oxide thickness
while increasing the physical thickness to reduce gate tunneling leakage [90-92]. Since
high-κ materials do not passivate the Si surface and inevitably form a SiO2 interfacial
layer after thermal processing, high-κ/SiO2 bilayer dielectrics are typically used for the
gate stack. In studying the use of different high-κ materials, it was observed that there
were uncontrollable flatband and threshold voltage shifts that would affect the CMOS
operating voltages [91, 93, 94]. These VFB shifts were present for a wide range of high-κ
TaNLaOxSiO2
Si
TaNAlOxSiO2
Si
10 - 20 Å
10 Å
TaN
AlOx SiO2
Φm,eff
Evacuum
EC
EFEV
p-Si
dtunneling
∆ΦSBH(a) (c)
(b) (d)
95
dielectrics, and found to arise from the high-κ/SiO2 interface itself rather than from the
bulk of the high-k material [95]. As shown in Figure 6.2a, when the SiO2 thickness is
fixed and the high-κ GeO2 thickness varied, the VFB shift occurs when the GeO2 is first
introduced and did not change with further increase in the GeO2 thickness, indicating the
VFB shift is not due to fixed charges in the GeO2. In performing a survey of materials,
Kita et al. [96] noticed that the high-κ materials that resulted in a positive VFB shift were
ones that had a greater oxygen density than SiO2 (Figure 6.2b). The reverse was also true,
where materials with a lower oxygen areal density resulted in a negative VFB shift. The
idea of oxygen areal density (σ) comes from the volume difference in the oxide
molecules, where different volumes lead to differences in the areal density of the oxygen.
The number of oxygen atoms per unit area is approximated by Vu-2/3 where Vu is defined
as the volume of the structure containing a single oxygen atom. Differences at the high-
κ/SiO2 interface can drive an equalization of σ where the oxygen atom from the higher
density material moves to the lower density material, leaving behind a positively charged
oxygen vacancy and a dipole that shifts the MOSCAP VFB (Figure 6.2c).
Figure 6.2. (a) C-V of MOSCAPs with and without high-κ GeO2. A constant VFB shift was observed regardless of the GeO2 thickness, implying the shift is due to a dipole at the GeO2/SiO2 interface rather than fixed charge in the GeO2. (b) Survey of high-κ materials and their corresponding VFB shifts. (c) Illustration of the equalization of the oxygen areal density through oxygen transfer at the interface and dipole formation. Figures are from Reference#[95].
(a)
(c)
(b)
96
However, despite electronic dipoles being formed at high-κ/SiO2 due to
differences in σ, researchers found there was no dipole present at high-κ/high-κ interfaces
even though there are also differences in σ [91, 92]. To pinpoint the location of the dipole,
trilayer high-κ/high-κ/SiO2 gate stacks were fabricated, and the thicknesses of the two
high-κ layers were separately modified to see the effect on VFB (Figure 6.3). No VFB shift
was observed in changing the thickness of the upper high-κ in contact with the gate
electrode (blue line), and a VFB shift was only observed when the thickness of the lower
high-κ in contact with the SiO2 was changed (red line). Fixed charge was eliminated as a
reason for the VFB changes because if fixed charge were responsible, as the dielectric
thickness is increased and more fixed charge is incorporated in the film, there would be a
more significant effect on VFB. From these findings it was concluded that electronic
dipoles only exist at high-κ/SiO2 interfaces. This was true for the A12O3/HfO2/SiO2 [91],
HfO2/Y2O3/SiO2 [91], and HfO2/Al2O3/SiO2 [91, 92] material systems. It was concluded that there are no dipoles at high-κ/high-κ interfaces, but this
appears to contradict their reasoning of dipole formation by differences in the oxygen
areal density. Their results may be unique to the particular material systems studied, so to
investigate this, we studied the properties of bilayer MIS to see if it is possible form
dipoles at high-κ/high-κ interfaces to further shift the Fermi level and to minimize ΦB,eff.
Figure 6.3. (a) VFB shift of NiSi/A12O3/HfO2/SiO2/Si MOSCAPs with varying dielectric thicknesses. The blue line indicates the effect of change the bottom high-κ dielectric, and the red shows the effect of changing the upper high-κ thickness. (b) VFB shift of NiSi/HfO2/Y2O3/SiO2/Si MOSCAPs. Figures are from Reference#[91].
(a) (b)
97
6.3 Device Fabrication
The high-κ/high-κ bilayer MIS contacts were fabricated in the same way as the
single dielectric MIS contacts. We used lightly doped (2x1016cm-3) MBE grown n-GaAs
to emphasize the thermionic emission current over the barrier and to more accurately
extract barrier height values. The samples underwent an organics degrease by sonication
in a 1:1 acetone and methanol solution, followed by rinsing in deionized (DI) water for 1
minute. The native oxide was then removed by soaking the samples in a dilute HCl
solution (1:1 = DI water : 29% HCl) for 3 minutes, followed by a 20sec DI water rinse
with agitation. Immediately after the rinsing step the samples were immersed in 5%
ammonium sulfide (NH4)2S solution for sulfur passivation. After 15min the samples were
removed and rinsed well in DI water and dried by nitrogen gun and immediately loaded
into the ALD chamber to minimize native oxide formation. The bilayer ALD films were deposited in the Cambridge Nanotech Savannah
ALD using standard pulse and purge times. Table 6.1 summarizes the precursors used
and the deposition temperature. The deposition temperatures were mostly higher than in
the standard recipe for higher quality, denser films. The maximum temperature of 250oC
was used in most cases, except for ZrO2 and ZnO were at higher temperatures the
precursors would no longer adsorb well on the sample surface. To minimize GaAs native
oxide formation, the metal organic precursor was used as the starting pulse, to follow
with the self-cleaning[43] observed in Al2O3 and HfO2. For the bilayer dielectrics, the two ALD materials are deposited in-situ without
breaking vacuum. After the ALD deposition, the samples were loaded into the shadow
mask holders and the diodes were defined by 150nm Al metal evaporation in Innotec.
When the front metal is finished, the shadow mask holders were flipped and the backside
of the samples were lightly scratched using a diamond scriber in crosshatch patterns to
remove the native oxide immediately prior to loading the samples for the 50nm Ti +
150nm Au back contact deposition in Innotec.
98
Film Metal Precursors ALD Reaction Temp.
Al2O3 TMA (CH3)3 Al + H2O 250oC
TiO2 TDMAT [(CH3) 2N]4 Ti + H2O 250oC
HfO2 TDMAH [(CH3) 2N] Hf + H2O 250oC
ZrO2 TEMAZ (CH3C2H5)4 Zr + H2O 200oC
ZnO DEZn (C2H5) 2Zn + H2O 160oC
Table 6.1. Summary of the ALD precursors and deposition temperature.
6.4 Electrical Characterization
6.4.1 Diode Current
For the bilayer MIS, TiO2 is chosen as the bottom dielectric layer in most of the
investigated samples because it achieved the lowest RC in the single dielectric MIS
contact. The low RC is most likely due to the combination of a large dipole magnitude
and a low conduction band offset for minimal penalty of tunneling through the dielectric. TiO2/Al2O3 was the first bilayer dielectric stack investigated because it had the
largest difference in the calculated oxygen areal densities (Figure 6.2B). As a starting
point, the TiO2 thickness was first held constant at 13Å (30cy of ALD), and the Al2O3
was varied between 0 and 20Å. Figure 6.4 summarizes the measured Al/Al2O3/TiO2/n-
GaAs MIS diode currents. In comparison with the single dielectric Al/13Å TiO2/n-GaAs
MIS diode, by adding Al2O3 to the dielectric stack there was a continuous increase in the
reverse current with 3 to 7Å Al2O3. This indicates there is an additional ΦB,eff reduction
beyond that introduced at the TiO2/n-GaAs interface, because otherwise the addition of
Al2O3 should only reduce the current. This result is counter-intuitive in that adding a
larger bandgap insulator for an overall thicker dielectric can actually increase the current
by more than an order of magnitude and reduce ΦB,eff. However, this can be explained by
the presence of dipoles similar to those found in the Si bilayer MIS contacts that further
shift the Fermi level. This TiO2/Al2O3 dipole would have to point in the same direction as
99
that of the dielectric/semiconductor interface dipole in single dielectric MIS. When the
Al2O3 thickness is increased beyond 7Å, the current eventually becomes limited by the
tunneling current through the dielectric, and the reverse current decreases. This current
tradeoff with the Al2O3 thickness is similar to that of the single dielectric MIS contacts,
which further suggests a same underlying mechanism. To find the optimal thickness for maximum current and minimal contact
resistance, the Al2O3 thickness was held constant at 7Å (7cy of ALD) and the TiO2 was
varied between 6.5 and 30Å (15 to 70cy of ALD). From the measured diode current
shown in Figure 6.5, the current continually increased for 6 to 13Å and decreased for 13
to 30Å of TiO2. This continuous trend demonstrates that the dependence of the current
on the ALD thickness is consistent and strengthens the credibility of the data. The overall
optimal thickness was found to be 13Å TiO2 and 7Å Al2O3.
Figure 6.4. MIS diode current of Al/TiO2/n-GaAs and Al/Al2O3/TiO2/n-GaAs
with a constant 13Å TiO2 thickness. The increase in both the forward and
reverse currents with the addition of larger bandgap material Al2O3 is counter
intuitive and indicates a further reduction in ΦB.eff beyond that achieved by the
TiO2 single dielectric MIS.
-1 -0.5 0 0.5 1
10-6
10-4
10-2
100
Curr
ent
(A/c
m2 )
Voltage (V)
13Å TiO2
13Å TiO2 + 3Å Al
2O
3
13Å TiO2 + 5Å Al
2O
3
13Å TiO2 + 7Å Al
2O
3
13Å TiO2 + 10Å Al
2O
3
13Å TiO2 +15Å Al
2O
3
13Å TiO2 + 20Å Al
2O
3
Al Schottky
Add TiO2
Add Al2O3
ΦB,eff
Al n-GaAs
Al2O3
TiO2
Tunneling Current
+ -+ -
GaAs
Al2O3TiO2
Al
100
Figure 6.5. Al/Al2O3/TiO2/n-GaAs MIS diode current with a constant 7Å Al2O3
thickness and varying TiO2 thickness. The optimal TiO2 thickness for maximum
current is 13Å or 30cycles of ALD.
This bilayer MIS contact behavior was also found in TiO2/HfO2 (Figure 6.6) and
TiO2/ZrO2 (Figure 6.7) dielectric stacks, suggesting that there is a dipole present at
multiple TiO2/high-κ interfaces. For a constant 13Å TiO2, the corresponding optimal
thicknesses for maximum current were 8.5Å HfO2 (10cy) and 16Å ZrO2 (20cy).
Figure 6.6. Diode current of Al/HfO2/TiO2/n-GaAs with a constant 13Å TiO2
(30cy) thickness and varying HfO2 thickness. The optimal HfO2 thickness for
maximum current is 8.5Å or 10cycles of ALD.
-1 -0.5 0 0.5 1
10-6
10-4
10-2
100
|Cur
rent
| (A
/cm
2 )
Voltage (V)
TiO2 30cy + Al
2O
3 7cy
TiO2 25cy + Al
2O
3 7cy
TiO2 15cy + Al
2O
3 7cy
Al2O
3 7cy
Al Schottky
Thicker TiO2
-1 -0.5 0 0.5 1
10-6
10-4
10-2
100
Voltage (V)
TiO2 60cy + Al
2O
3 7cy
TiO2 70cy + Al
2O
3 7cy
TiO2 50cy + Al
2O
3 7cy
TiO2 40cy + Al
2O
3 7cy
TiO2 30cy + Al
2O
3 7cy
Al Schottky
Thicker TiO2
-1 -0.5 0 0.5 1
10-6
10-4
10-2
100
|Cur
rent
| (A
/cm
2 )
Voltage (V)
Al SchottkyTiO
2 30cy
TiO2 30cy + HfO
2 5cy
TiO2 30cy + HfO
2 7cy
TiO2 30cy + HfO
2 10cy
Thicker HfO2
-1 -0.5 0 0.5 1
10-6
10-4
10-2
100
Voltage (V)
Al SchottkyTiO
2 30cy + HfO
2 25cy
TiO2 30cy + HfO
2 20cy
TiO2 30cy + HfO
2 15cy
TiO2 30cy + HfO
2 12cy
TiO2 30cy + HfO
2 10cy
ThickerHfO2
101
Figure 6.7. Diode current of Al/ZrO2/TiO2/n-GaAs with a constant 13Å TiO2
(30cy) thickness and varying ZrO2 thickness. The optimal ZrO2 thickness for
maximum current is 16Å or 20cycles of ALD.
In comparing the maximum achievable current using the three bilayer dielectrics
(Figure 6.8.), TiO2/Al2O3 resulted in the largest reverse current, 45 times higher than the
TiO2 MIS and 4 orders of magnitude greater than the Al/n-GaAs Schottky current.
TiO2/ZrO2 had the smallest improvement of only 5 times over that of the TiO2 MIS.
\
Figure 6.8. Comparison of the maximum current in Al/Al2O3/TiO2/n-GaAs,
Al/HfO2/TiO2/n-GaAs and Al/ZrO2/TiO2/n-GaAs bilayer MIS at their optimal
thicknesses. TiO2/Al2O3 resulted in the largest reverse current.
-1 -0.5 0 0.5 1
10-6
10-4
10-2
100
Curr
ent
(A/c
m2 )
Voltage (V)
Al SchottkyTiO
2 30cy
TiO2 30cy + ZrO
2 5cy
TiO2 30cy + ZrO
2 10cy
TiO2 30cy + ZrO
2 15cy
TiO2 30cy + ZrO
2 20cy
TiO2 30cy + ZrO
2 25cy
Add TiO2
Add ZrO2
-1 -0.5 0 0.5 1
10-6
10-4
10-2
100
Curr
ent
(A/c
m2 )
Voltage (V)
Al Schottky13Å TiO2
13Å TiO2 + 16Å ZrO2
13Å TiO2 + 8.5Å HfO2
13Å TiO2 + 7Å Al2O3
> 4 orders of magnitude
5X
20X45X
Al
GaAs
ZrO2TiO2
102
6.4.2 Contact Resistance
These contacts were further evaluated through RC measurements by modeling the
bilayer MIS (Figure 6.9) as two resistances in series: a tunneling resistance through the
dielectric (RT) and a resistance associated with the barrier (RSB), where there exists an
optimal insulator thickness (tINS) to minimize RC. Figure 6.10 illustrates the measured contact resistance vs. dielectric thickness
tradeoff of Al/Al2O3/TiO2/n-GaAs. By holding one dielectric thickness constant and
varying the thickness of the other and vice versa, the optimal thicknesses for minimal
contact resistance can be found. This point was 13Å TiO2 + 7Å Al2O3, and the values
agree with the optimal point from the diode current.
Figure 6.9. Schematic of RC vs. tINS. An optimal thickness exists to minimize RC, arising from the tradeoff between a reduced barrier RSB and an increased RT.
Figure 6.10. Optimization of the TiO2 and Al2O3 thicknesses for minimum RC by holding on thickness constant and varying the other and vice versa.
Insulator Thickness
Optimal Thickness
Tunneling Resistance
Dominates (RT)
Barrier Height Dominates
(RSB)
Con
tact
Res
ista
nce
(log)
RT RSB
1.0E‐06
1.0E‐05
1.0E‐04
1.0E‐03
1.0E‐02
1.0E‐01
0 1 2 3
Contact R
esistance Ra
tio
Dielectric Thickness (nm)
Vary TiO2 + 0.7nm Al2O3
1.3nm TiO2 + Vary Al2O3
1.3nm TiO2
0.7nmAl2O3
103
In comparing the measured RC vs. tINS tradeoff of the single and bilayer MIS
contacts (Figure 6.11a), it is clear that the bilayer TiO2/Al2O3 contact achieves a lower
RC than both the contacts with TiO2 and Al2O3 alone, and the same is true for TiO2/HfO2
(Figure 6.11b). For a fixed 1.3nm TiO2, varying the Al2O3 or HfO2 thickness results in a
RC tradeoff very similar to that of a single dielectric MIS. Again, this implies a similar
underlying mechanism, with an additional contributing dipole at the TiO2/Al2O3 interface.
Figure 6.11. (a) RC vs. tINS for MIS contacts using TiO2, Al2O3, and TiO2 + Al2O3. In Al/Al2O3/TiO2/n-GaAs, RC is reduced beyond that of just TiO2. Without the presence of a high-κ/high-κ dipole, adding a dielectric material should only increase RC. (b) MIS contacts with TiO2, HfO2, and TiO2 + HfO2 dielectrics show the same trends as TiO2 + Al2O3.
0 1 2 3
Con
tact
Res
ista
nce
Rat
io
Dielectric Thickness (nm)
Al2O 3
TiO2
TiO2+Al2O3
1.3nmTiO2
100
10-1
10-2
10-3
10-4
10-5
10-6
Al2O3TiO2TiO2 + Al2O3
0 1 2 3
Con
tact
Res
ista
nce
Rat
io
Dielectric Thickness (nm)
HfO2TiO2TiO2 + HfO2
1.3nmTiO2
101
100
10-1
10-2
10-3
10-4
10-5
10-6
HfO2TiO2TiO2 + HfO2
(a)
(b)
104
These electronic dipoles appear to be present for several high-k/high-k interfaces,
since TiO2/HfO2 and TiO2/ZrO2 bilayer dielectrics also have a lower RC than their single
dielectric counterparts (Figure 6.12). The TiO2/Al2O3 and TiO2/HfO2 samples performed
very similarly, and this is due to the tradeoff between the dipole magnitude (RSB) and
conduction band offset (RT). The TiO2/Al2O3 can have the largest dipole from having the
greatest difference in oxygen areal density, but Al2O3 is also a material that has a larger
bandgap and conduction band offset to TiO2. This would result in a smaller RSB but larger
RT, while the TiO2/HfO2 samples would have a larger RSB but smaller RT. The exact RC
tradeoff depends on the magnitude of the differences between the two samples.
Figure 6.12. RC vs. tINS for MIS contacts using TiO2 + HfO2, TiO2 + ZrO2, and
TiO2 + Al2O3 bilayer dielectrics.These bilayer MIS contacts result in lower Rc
than their single dielectric MIS contact counterparts, which further indicates the
presence of a high-κ/high-κ dipole. The absolute minimum RC is achieved by
the TiO2 + Al2O3 contact.
A summary of the lowest achieved contact resistance for all of the single and
bilayer dielectric MIS contacts studied is provided in Figure 6.13. Even with the addition
of a larger bandgap dielectric that adds to the tunneling resistance, there is still a drastic
reduction in RC over the single dielectric MIS. With the bilayer contacts, there are more
material choices in the contact design, and possibly room to continue to reduce RC.
1.0E‐06
1.0E‐05
1.0E‐04
1.0E‐03
1.0E‐02
1.0E‐01
1.0E+00
0 1 2 3 4
Contact R
esistance Ra
tio
Total Dielectric Thickness (nm)
TiO2
TiO2+ZrO2
TiO2 +HfO2
1.3nm TiO2
105
Figure 6.13. Summary of minimum RC of single and bilayer MIS.
6.4.3 Effective Barrier Height In the absence of a model that accurately depicts the behavior of the bilayer MIS
contacts and captures both thermionic and tunneling currents, the thermionic emission
model [32] is used to extract ΦB,eff through diode measurements between 233 to 353 K.
The extracted value is not equal to the difference in Fermi levels of the metal and
semiconductor since the insulator is not accounted for, but it is representative of the
electrical behavior. The effective barrier height represents MIS contacts that are
electrically equal to Schottky diodes with the same ΦB. Figure 6.14 summarizes the
measured ΦB,eff and shows the bilayer contacts achieve the best performance with the
lowest ΦB,eff, and pose a significant improvement over the single dielectric MIS contacts.
Figure 6.14. Summary of the effective barrier height of single and bilayer MIS.
1.0E‐06
1.0E‐05
1.0E‐04
1.0E‐03
1.0E‐02
1.0E‐01
1.0E+00
Contact R
esistance Ra
tio
Single Dielectric MIS Contact
Bilayer MIS Contact
Al SiN TiO2 HfO2 Al2O3 ZrO2 TiO2 + TiO2 + TiO2 + Schottky HfO2 Al2O3 ZrO2
0.10.20.30.40.50.60.70.80.9
Schottky SiN Al2O3 TiO2 HfO2 TiO2 + Al2O3
TiO2 + HfO2
Bar
rier H
eigh
t (eV
) Single Dielectric MIS Contact
Bilayer MIS Contact
Al SiN Al2O3 TiO2 HfO2 TiO2 + TiO2 + Schottky Al2O3 HfO2
106
6.4.4 Inverted Dielectric Layers To verify the existence of a dipole, TiO2+Al2O3 bilayer MIS were fabricated with
the two dielectrics layers inverted. If fixed charge were responsible, as discovered in the
single dielectric MIS, then RC of Al/TiO2/Al2O3/GaAs and Al/Al2O3/TiO2/GaAs samples
would be not too different. If dipoles were responsible, then inverting the two dielectrics
would flip the dipole direction and change a low resistance into a high resistance sample. Figure 6.15 illustrates the contact resistance tradeoff of the Al2O3 single dielectric
(green line) and bilayer dielectric MIS (red and blue lines) with a fixed TiO2 thickness of
1.3nm and a varying Al2O3 thickness. As discussed in the previous chapter, as the Al2O3
thickness is increased, positive fixed charge begins to accumulate in the film so more
potential is dropped across the dielectric and ΦB,eff is reduced. The lower ΦB,eff in
Al/Al2O3/n-GaAs is reflected through a reduction in the contact resistance. In the case of
Al/TiO2/Al2O3/GaAs, when the Al2O3 thickness is increased from 0.5 to 1nm, there is
expected to be a buildup of positive fixed charge or creation of an Al2O3/GaAs dipole to
lower ΦB,eff and RC. However, the contact resistance only increases with Al2O3 thickness.
This can be explained by the presence of a TiO2/Al2O3 dipole pointed in the opposite
direction to cancel the benefit of Al2O3. The magnitude of this TiO2/Al2O3 dipole would
have to be greater than that of the Al2O3/GaAs dipole and the fixed charge effect.
Figure 6.15. Summary of minimum RC of single and bilayer MIS.
GaAs
Al2O3
TiO2
Al
++
GaAs
Al2O3
TiO2
Al
++
0 0.5 1 1.5 2
Contact R
esistance Ra
tio
Al2O3 Thickness (nm)
1.3nm TiO2 + Vary Al2O3
Vary Al2O3 + 1.3nm TiO2
Al2O3 Only
1.3nmTiO2
13Å TiO2 + Vary Al2O3Vary Al2O3 + 13Å TiO2
Al2O3 Only
102
101
100
10‐1
10‐2
10‐3
10‐4
10‐5
10‐6 Al
Al2O3
TiO2
++++++
+
++
++
+
++
+
++
+
+
+ - + -
Al
Al2O3
TiO2
++++
++
+
++
++
+
++
+
++
+
+
- + + -
107
These results of the inverted bilayer dielectric Al/TiO2/Al2O3/GaAs increasing the
contact resistance of Al/TiO2/GaAs MIS agree well with reports [97] of Pt/TiO2/Al2O3/Ge
decreasing the gate leakage of Pt/TiO2/Ge by more than six orders of magnitude at VFB
with only 1nm of Al2O3 (Figure 6.16). The large reduction in the leakage current with
ultrathin Al2O3 does not appear to be due to just the reduction of tunneling current
through the larger band offset material. From our results, the addition of the Al2O3
interlayer would create a TiO2/Al2O3 dipole which in this case would increase the ΦB,eff
of the MOS structure. Similar results were also reported for Pt/TiO2/Al2O3/InGaAs
structures significantly reducing the gate leakage of Pt/TiO2/InGaAs [98].
Figure 6.16. Gate leakage of Pt/TiO2/Ge MOSCAPs with and without an Al2O3
interlayer. By inserting 30cycles or 3nm of Al2O3 the leakage current is reduced
by more than six orders of magnitude. Figures are from Reference#[97].
6.4.5 TiO2 Degradation Over Time
The bilayer MIS studied in this chapter all contained TiO2, and through
measurements over time, the TiO2 was found to be unstable and degraded. This change in
resistance agrees with results from TiO2 RRAM [99] and TiO2’s sensitivity to oxygen
[100] and hydrogen [101]. The formation of titanium interstitials or oxygen vacancies has
been suggested as the mechanism for changes in the resistance [101]. Figure 6.17
illustrates how the diode currents for several structures changed over the course of a few
days. There was no clear trend, as some films became more resistive while others become
108
more conductive. However, for a given sample the trend over time was consistent, as
shown through the measured contact resistance in Figure 6.17d. In between the
measurements the samples were stored in nitrogen ambient to minimize exposure and
reaction with oxygen. With these safe guards, the samples were found to require a few
days before the resistances were significantly different. As a precaution, the time between
each fabrication step was minimized, and the samples were always measured within an
hour after fabrication. The experimental results were found to be repeatable, with
overlaying data points from samples fabricated on different days, which demonstrates
that the instability of the TiO2 did not affect our reported results. The TiO2 degradation
over time can be avoided by capping the surface with a thick SiO2 film to prevent
exposure to air, but would require a slightly different device structure (Figure 6.18).
Figure 6.17. Diode current measured immediately, 3 days, 6 days, and 9 days after fabrication, with changes saturating by day 9. There was no apparent trend in the resistance change even among the same materials (a) 20cy TiO2 + 12cy HfO2 (b) 30cy TiO2 + 12cy HfO2 (c) 40cy TiO2 + 12cy HfO2 (d) Summary of RC changes for the various bilayer MIS over time.
-1 -0.5 0 0.5 110-3
10-2
10-1
100
|Cur
rent
| (A
/cm
2 )
Voltage
Day 0 Day 3Day 6 Day 9
20cy TiO2 +
12cy HfO2
-1 -0.5 0 0.5 110-3
10-2
10-1
100
|Cur
rent
| (A
/cm
2 )
Voltage
Day 0 Day 3Day 6 Day 9
30cy TiO2 +
12cy HfO2
-1 -0.5 0 0.5 110-3
10-2
10-1
100
|Cur
rent
| (A/
cm2 )
Voltage
Day 0 Day 3Day 6 Day 9
40cy TiO2 +
12cy HfO2
0.1
1
10
0 3 6 9
Contact Resistance Ratio
Day
30cy TiO2 + 25cy ZrO2
20cy TiO2 + 12cy HfO2
30cy TiO2 + 7cy Al2O3
40cy TiO2 + 12cy HfO2
30cy TiO2 + 12cy HfO2
(a) (b)
(c) (d)
109
GaAs
TiO2
AlAl2O3
SiO2SiO2
(a) (b)
Figure 6.18. (a) Current device structure. (b) Device structure needed to prevent
TiO2 degradation over time.
6.5 Discussion The exact reasoning for the observed reduction in ΦB,eff in the high-κ/high-κ MIS
is still being studied. However, it seems possible that it is due to dipoles formation at the
high-κ/high-κ interface, similar to the dipoles reported at SiO2/high-κ interfaces that
manifest as shifts in the MOSFET VFB [91, 93, 94]. These dipoles are cited to arise from
differences in the electronegativity (χ) [90, 102] or oxygen areal density (σ) [96] of the
two materials. Interface dipoles are reported to be formed due to discontinuities in the elements’
electronegativities that generate dipoles at both the high-κ/SiO2 interface and within the
high-κ material [102]. In the high-κ, the amorphous structure and the great screening
ability prevents buildup of a net dipole. However, at the high-κ/SiO2 interface there is a
difference in the dielectric constant or screening ability of the two materials which allows
a net dipole to build up (Figure 6.19a). In studying how doping of HfO2 changes the
HfO2/SiO2 dipole, the electronegativity of the dopant atoms were discovered to determine
the magnitude of the net dipole and therefore the shifts in VFB (Figure 6.19b). Although interface dipoles induced by differences in dielectric screening and χ
can explain the observed HfO2/SiO2 dipoles the electronegativities and dielectric
constants of high-κ materials are much closer in value (Table 6.2), and it is unclear if the
results from ab-initio modeling of doped HfO2/SiO2 (ionic/covalent bonds) interfaces is
directly applicable to high-κ/high-κ interfaces (ionic/ionic bonds).
GaAs
TiO2
Al
Al2O3
110
(a) (b)
Figure 6.19. (a) Schematic of net dipole build up due to screening ability
differences at the interface. (b) Illustration of how the dipole magnitude changes
with the electronegativity of the dopant atom. Figures are from Reference#[102].
Pauling Electronegativity
Work Function (eV)
Dielectric Constant of
Oxide Formed Si 1.91 4.7 3.9
Ti 1.54 4.33 80
Zn 1.65 4.3 8.3
Al 1.61 4.08 9
Zr 1.33 4.05 25
La 1.1 4 27
Hf 1.3 3.9 25
Y 1.22 3.1 15
O 3.61
Table 6.2. Electronegativity, work function, and dielectric constant of the
elements corresponding to the investigated dielectrics.
111
In the case of the oxygen areal density theory [96], when two materials are placed
in contact there is a transfer of oxygen from the higher σ to the lower σ material, resulting
in a positively charged vacancy and a dipole pointing towards the higher σ material. Kita
et al. define σ as the number of oxygen atoms per unit area, where the unit structure is
defined as the structure containing a single oxygen atom. The calculation of the unit
DensityWeightMolecularStructureUnitVStructureUnitofVolume u ==
112
literature citing that dipoles are not formed at high-κ/high-κ interfaces. The difference can
be attributed to the specific high-k materials studied. Previous reports include Al2O3/HfO2
[92] and HfO2/Y2O3 [91] interfaces, while the dipoles at the TiO2/Al2O3, TiO2/HfO2, and
TiO2/ZrO2 interfaces that we report here have not been investigated before. Also, it is
possible that the difference can be due to the thermal annealing steps used in the reported
literature [91, 92] that could change the dipole or cause some intermixing between the
layers. The high temperature annealing between 500-640oC for 30 to 60sec in nitrogen
atmosphere was most likely used to improve the SiO2/Si interface for MOSCAPs. In our
case, the samples are measured as deposited without any annealing process. To investigate the effect of RTA annealing, we fabricated four MIS samples with
Al metal on n-GaAs substrates using TiO2, Al2O3, Al2O3+TiO2, and TiO2+Al2O3
dielectrics. The single and bilayer samples allow us to separate the effects in the high-κ
film and at the high-κ/GaAs interface from ones at the high-κ/high-κ interface. After ALD
deposition and prior to metal evaporation, some of the samples underwent RTA anneals at
300oC or 500oC for 60 seconds in nitrogen ambient. As shown below in Figure 6.20, the
single layer MIS contact resistances do not change significantly with RTA annealing,
indicating there is not a significant change in both the fixed charge and the high-κ/GaAs
dipole. There is a slight decrease in the contact resistance with higher temperature
annealing, but this can be explained by densification of the films that increase the
tunneling current through the ultrathin dielectrics. On the other hand, RTA annealing had a large effect on the bilayer MIS contacts.
By alternating the TiO2 and Al2O3 dielectrics in the bilayer, the as deposited contact
resistances are very different. This can be due to several factors: (1) the inverted dipole
at the high-κ/high-κ interface, (2) the different dielectric/semiconductor dipole, and (3)
the change in the fixed charge distribution. RTA annealing at 300oC had only a small
effect on the contact resistances. However, after annealing at 500oC, the two bilayer MIS
changed significantly and the contact resistances became roughly equal. From the single
dielectric MIS results, RTA annealing does not change the dielectric/semiconductor
dipole and the fixed charge, so the difference can be attributed to a change at the high-
κ/high-κ interface either through intermixing between the two layers or the removal of
113
the dipole. Typically high thermal budgets tend to cause intermixing of materials, but
there are some cases, such as for HfO2/SiO2 where after annealing there is phase
separation and the interface between materials becomes more defined[103]. Further
materials characterization is needed to difference between the two.
Figure 6.20. Effect of RTA annealing on the contact resistance of Al/dielectric/n-
GaAs single dielectric and bilayer MIS.
In comparing our results with the reports of the absence of a high-κ/high-κ dipole,
their annealing step may have significantly changed or removed the interface dipole.
There are no measurements of the as deposited samples, so it is difficult to pinpoint the
exact effect of annealing in their material structure. In our samples the annealing had a
large effect, but this may also be due to the lower crystallization temperature of TiO2 that
caused our films to have a greater sensitivity to the thermal anneals. One possible counterargument to our results is the fact that despite the annealing
step, Kita et al. [96] still observed dipoles at the high-κ/SiO2 interface. However, this
could be due to differences in bonding where high-κ/high-κ (ionic/ionic bonding) and
high-κ/SiO2 (ionic/covalent bonding) layers could have varying thermal stabilities. As a
result, the annealing step may have changed the high-κ/high-κ dipole, but not affect the
high-κ/SiO2 dipole.
As Dep RTA at 300C RTA at 500C
Contact R
esistance Ra
tio
30cy TiO27cy Al2O3
100
10‐1
10‐2
10‐3
10‐4
10‐5
10‐6
13Å TiO2
7Å Al2O3
7Å Al2O3 + 13Å TiO2
13Å TiO2+ 7Å Al2O3
As Dep RTA at 300oC RTA at 500oC
GaAs
TiO2
Al
Al2O3
GaAs
Al2O3
Al
TiO2
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6.6 Summary In summary, we successfully demonstrated RC and ΦB,eff tuning of Al/n-GaAs
junctions using ALD TiO2/high-κ bilayer MIS contacts, where the two high-κ dielectrics
in combination further shift the Fermi level and reduce ΦB,eff beyond that of a single
dielectric MIS. The underlying mechanism is believed to be the formation of a high-
κ/high-κ dipole through an equalization of the oxygen areal density at the interface
(Figure 6.21). To our knowledge, there is no published literature studying high-κ/high-κ
dipoles, so this may be one of the first papers suggesting the presence of dipoles at high-
κ/high-κ interfaces. This opens doors to the exploration of a multitude of other high-
κ/high-κ dielectrics to ultimately achieve ΦB,eff ≤ 0. The ideal bilayer dielectric stack
would be one that optimizes the tradeoff between the dipole magnitude (RSB) and
conduction band offset (RT). Figure 6.22 summarizes how these two parameters change
for different dielectric materials. This bilayer MIS structure provides much more flexibility in the design of ideal
source/drain contacts for III-V MOSFETs and Schottky Barrier FETs. So far, most reports
of MIS contacts on Si, Ge, and GaSb are based on single dielectrics, where the additional
of another dielectric material may be able to achieve lower barrier height and contact
resistances. Further study of the dipole interaction and effective work function will lead
to a better understanding of the physics behind metal/III-V contacts as well as contacts to
other semiconductors.
Figure 6.21. Schematic of the transfer of oxygen from the higher σ to lower σ
material, leaving behind a positively charged oxygen vacancy and adding a
negatively charged ion on the other side to form the dipole.
TiO2
Al2O3
TiO2
Al2O3Dipole
O2-
Vo2+
115
Figure 6.22. Summary of the conduction band offsets and calculated σ ratios
taken relative to TiO2 for the investigated dielectrics.
6.7 Future Work Dipole formation through an equalization of the oxygen areal density is one
reported explanation that is consistent with our experimental observations, but it may not
be the correct explanation. To more conclusively determine the mechanism, we need to
study dielectrics that create dipoles pointing in the opposite direction from what we have
studied. In particular, TiO2/Y2O3 and TiO2/La2O3 bilayers would be invaluable in
verifying the oxygen areal density theory, where σY2O3/σTiO2 = 0.84 and σLa2O3/σTiO2 =
0.80 indicate dipoles pointing towards TiO2. Also, the effect of RTA annealing on high-κ /high-κ interfaces needs to be further
examined to clarify the differences with those reported in literature [91, 92]. It should be
determined whether or not there is intermixing at the interface that destroys the dipole
after annealing. Low angle XRD before and after annealing of multi-structures would be
helpful in seeing whether the XRD peaks are blurred or sharpened [103]. In addition, it
would be helpful to study the effects of annealing on other bilayer MIS structures without
TiO2 to see if the low crystallization temperature of TiO2 is a contributing factor to our
annealing results.
‐1.0
‐0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.8
0.9
1.0
1.1
1.2
1.3
Y2O3 ZnO SiO2 TiO2 SiON ZrO2 HfO2 Al2O3
∆E C
Band
Offset (eV
)
Areal Oxygen Den
sity Ratio
σ / σ TiO2∆EC Band Offset (eV)
Y2O3 ZnO SiO2 TiO2 SiON ZrO2 HfO2 Al2O3
116
Chapter 7
Conclusions
7.1 Thesis Contributions The contributions of this thesis include the first demonstration of the MIS contact
on III-V compound semiconductors. Prior to this work the MIS contact structure was
only studied on elemental semiconductors Si and Ge. However, the behavior of binary
and ternary compounds could differ. GaAs and InGaAs MIS contacts were verified to
successfully reduce the contact resistance and effective electrical barrier height as
compared to their Schottky counterparts. These results are rather counter intuitive in that
inserting an ultrathin dielectric layer can in fact reduce the contact resistance. A
comprehensive study of how metal workfunction, semiconductor doping, and insulator
material affect the electrical behavior was also conducted for the first time. In Si and Ge
MIS contact literature only a maximum of one or two dielectric and metal gate materials
were studied at a time, so the understanding was limited to the specific materials.
Through our study of a wide range of materials, we were able to draw more generalized
conclusions.
This thesis also elucidates understanding of the strong metal/III-V Fermi level
pinning from studying how the MIS contact reduces the effective barrier height. We were
able to pinpoint the mechanism to be due to a shift in the Fermi level rather than the
previously reported Fermi level unpinning, which suggests the bond polarization theory
offers a better explanation of Fermi level pinning than the metal induced gap states theory.
117
Through investigating a wide range of dielectric materials coupled with thermal
annealing studies of the MIS contacts, the observed electrical behavior was discovered to
be caused by a combination of dipole formation at the dielectric/semiconductor interface
and presence of bulk fixed charge in the dielectric materials. Prior to this work, fixed
charge was never considered to contribute to the observed MIS barrier height lowering,
and we believe the fixed charge results can be applied to the Si and Ge MIS behavior
reported in the literature. Further contribution is made in the first use of high-κ/high-κ bilayer MIS contacts
that demonstrated a significant improvement over the single dielectric MIS contacts.
Previously, bilayer MIS contacts have been studied on Si, but they were limited to
SiO2/high-κ dielectric interfaces. The use of a thermally grown ultrathin SiO2 has limited
this concept to Si substrates, while the use of two high-κ dielectrics can be applied to any
semiconductor, including III-V and Ge. The underlying mechanism was discovered to be
due to the presence of high-κ/high-κ dipoles that are reported for the first time. We also
provided a comparison between single and bilayer MIS contact resistance and show the
evolution of changes across different dielectric thicknesses, whereas SiO2/high-κ MIS
reports only offered a comparison with the Schottky counterpart and did not include the
effect of dielectric thickness on the contact resistance. Overall, this thesis provides a more thorough understanding of the reasoning
behind the observed MIS contact behavior, which enables a better prediction of optimal
material properties for minimal contact resistance.
7.2 Future Directions In continuing to explore MIS contacts, it would be helpful to study the dielectric
properties in more detail through further materials characterization. Also, since ALD
material properties can change significantly with deposition temperatures, it would be
interesting to see how the deposition temperature affects the MIS electrical behavior and
to correlate those changes with changes in the dielectric density, stoichiometry, and band
offsets. Similarly, a more comprehensive study of the effect of thermal annealing can
118
offer a deeper understanding of the thermal stability and limitations of these MIS contacts.
If the thermal effects on the contact behavior can be predicted, then it may be possible to
further optimize and minimize the contact resistance. For bilayer dielectric MIS contacts, it would be beneficial to study a greater
number of high-κ/high-κ combinations to offer a more generalized summary of electronic
dipoles and bilayer contacts. In particular, TiO2/Y2O3 and TiO2/La2O3 dielectrics are
interesting in that through simple calculation they should form dipoles pointing in the
opposite direction of what was observed in this work. So far in III-V MIS contacts the
Fermi level has only been shifted towards the conduction band, while no dielectrics have
been demonstrated a shift of the Fermi level towards the valence band. Finally, this MIS contact structure can be applied to more III-V semiconductors
and even other semiconductors such as CNT and graphene. Essentially the use of
ultrathin dielectrics to shift the Fermi level through fixed charge and dipole formation can
be applied to any material that experiences Fermi level pinning.
7.3 Concluding Remarks In this thesis we demonstrated the use of an inserted insulator for reducing the
metal/III-V effective barrier height for a large selection of materials. However, there are
still many difficulties in achieving ohmic contacts due to the finite tunneling resistance
through the dielectrics. The lack of thermal stability is also a problem, especially as the
contact resistance increased several orders of magnitude after a 30 minute forming gas
anneal. In current CMOS technology, wafers need to undergo a forming gas anneal to
improve the gate stack quality and also need to withstand some thermal cycle processing
in subsequent process steps. Therefore, for MIS contacts to become a promising contact
technology, it is necessary to: (1) find dielectric materials with zero or negative band
offsets, (2) develop the ability to introduce fixed charge, (3) controllably tune dipole
direction and magnitude, and (4) use thermally stable materials. Nevertheless, even if
these conditions cannot be met, the idea of using ultrathin dielectrics to shift the Fermi
level may still have other applications outside of CMOS contacts.
119
Appendix A :
Piece Processing
Items to Purchase:
⋅ Glassware – Purchase your own glassware from the chemistry stock room because most processing steps will require you to use beakers. Outside beakers may be contaminated with some unknown materials or nanoparticles. It is also a good habit to have dedicated glassware for certain groups of chemicals and to use different tweezers for each group.
⋅ Tweezers – Carbon tipped tweezers give much better grip of samples. SNF stock room point tweezers are good for grabbing from the side, but from the top it will chip off pieces. Grip is very useful during litho when timed hotplates are needed
⋅ Kapton dots – Often times for SNF tools you will need to mount your small pieces onto a carrier wafer, such as in Innotec for metal deposition or Matrix for resist removal. The Kapton dots are pre-cut circles so it avoids the mess of kapton tape sticking to scissors.
Lithography Tips:
⋅ For contact mask design you should put multiple layers on one mask since for small pieces you will only be using a few dies so there is no need to have one mask per layer.
⋅ Do not make deep scribe marks on the back because sometimes you can lose vacuum for either the resist coating or contact aligner.
⋅ For resist spinning on Headway or Laurel, be sure to use blue tape from the stock room on the back of your samples to get better vacuum. However, make sure you
120
remove this take before the resist baking.
⋅ Karl Suss Contact Aligner : For alignment use the small single piece chuck. If it is not available you can cut the 4” yellow circular tape from the SNF stock room to block up most of the holes on the 4” wafer chucks.
⋅ Hot Plates: If there is foil present on the hot plate, unwrap it for small piece processing. The foil does not lie completely flat and with extremely small pieces sometimes the foil can lift upwards and the temperature may be lower.
Silicon Carrier Wafers:
⋅ 4” Si carrier wafers are useful in tools that only take 4” wafers such as the RTA, FGA, and ALD. These dummy wafer 4” Si wafers have etched down grooves to hold the pieces.
⋅ Fabrication details:
1. Thermally grow 100nm of SiO2 2. Pattern the wafer with resist. Kapton tape on a blank old mask can be used
to design a detailed pattern to be used with Karl Suss. Another option is painting resist directly on the edges of the wafer.
3. Dry etch the SiO2 patter. It is important to use dry etch rather than wet etch so SiO2 remains on the back of the wafer.
4. Use the SiO2 as a mask to wet etch the Si wafer in heated TMAH.
0.5”
0.5”
121
Appendix B :
Test Structures & Mask Design
1. Transistors Ring FETs:
Rectangular FETs:
⋅ Ring FETs are self isolated and do not need a mesa etch.
⋅ Gate to S/D spacing = 1, 1.5, 2, 4μm Label of spacing is = Z, SZ, S, L
⋅ S/D Doping has an 1, 1.5, 2um overlap with the gate
G
D
S
S
D G
B ⋅ Green layer = mesa etch Purple layer = active contact
⋅ S/D Doping has an 1, 1.5, 2um overlap with the gate
WidthLength
WidthLength
122
2. Contact Resistance
Kelvin Structure #1:
Kelvin Structure #2:
Transmission Line Method (TLM):
⋅ Current path is defined by implantation (pink layer)
⋅ Number indicates a width of 4 μm
⋅ “N” indicates a n‐contact
⋅ Current path is defined by mesa etch (green layer) with implantation everywhere (pink layer)
⋅ “N” indicates a n‐contact
⋅ Spacing between contacts are 5, 10, 15, 20, and 40 μm
⋅ Contact pads have widths of either 100 or 200 μm
123
Circular TLM (CTLM):
3. Resistivity
Van Der Pauw:
Four Point Probe:
⋅ Spacing between contacts are 5, 10, 15, 20, 25, 30, 40, and 60 μm
⋅ Active contact area = 4 x 4 μm
⋅ Length = 296 μm Width = 6 μm
⋅ Current path is defined by the mesa etch (green layer)
⋅ Active contact area = 4 x 4 μm
⋅ Current path is defined by the mesa etch (green layer)
124
4. Other Structures
MOSCAPs:
pn junction:
MOSFET with S/D Tied Together:
Charge Pumping FET:
⋅ Number indicates the area of the MOSCAP so 2.5K = 2500 μm2
⋅ Blue layer = metal gate grey layer = body contact
⋅ Number indicates the area of the MOSCAP so 2.5K = 2500 μm2
⋅ red layer = S/D contacts grey layer = body contact
⋅ Number indicates the area so 2.5K = 2500 μm2
⋅ red layer = S/D contacts blue layer = gate contact
⋅ For charge pumping measurements
⋅ FET length = 50, 75, 100 μm FET width = 200 μm
⋅ red layer = S/D tied together blue + purple layer = gate contact
ap + ALD Al2Oulation layeralignment mte (Mask #1)terning and rdened photvation by RTe Al2O3 by BO+ ALD regrot off patternetal lift off S/D + wet eiftoff (Maskg RTA 400oC
p‐
PR
Step #10
pStep # 11
Diffusion of implant
Ao~
loyed S/D C
O3 15nm at 3r marks and et) Si implantattoresist by OTA (700 oC foOE owth : 8nm Aning + Ni/Au
tch Al2O3 + ok #5,7) for 30 sec in
‐InGaAs
Al
‐InGaAs
Al2O3
overetch~15nm Mask
Alignm~1‐2u
Contacts
300oC for
tch into
tion (Mask#2O2 ashing or 10s in N2)
Al2O3 at 300o
evap (Mask
ohmic Au/Ge
n N2
PR
mentm
2)
oC k #3,8)
e/Ni
127
III‐V MOSFET with MIS S/D Contacts Copy steps # 1 – 9 from flow with alloyed S/D contacts up through gate formation. 10. Wet etch Al2O3 gate oxide 11. Sputter SiN + evaporate S/D metal all over 12. Pattern and etch S/D metal (Mask #5) 13. Quick dip in HF for thin SiN
Notes:
⋅ The simplified process flow illustration shown above does not include the isolation oxide deposition and body contact formation.
⋅ The isolation oxide layer is more for the contact resistance and resistivity measurements such as in the Kelvin and four point probe structures.
128
2. Process Details Process Step Processing Details Masking
2. Arsenic decap at 400oC for 6 min 3. ALD Al2O3 15nm at 300oC
2. Pattern Alignment Marks
1. YES oven for HMDS 2. Headway spin resist 5.5krpm for 30 sec for 1 um 3. Bake 90oC for 60sec 4. Expose KS for 1.0‐1.2 sec at Ch#1 (15mV/cm2) 5. Bake 115oC for 60 sec 6. Develop MF26A for 40 sec 7. Bake 110oC for 60 sec
Mask #1:Alignment Marks + Mesa Etch
3. Etch Alignment Marks into InGaAs
1. Wet etch Al2O3 in 20:1 BOE diluted 1:1 in DI for 1.5 min 2. Wet etch InGaAs in H2O2:H3PO4:H2O = 1:1:10 for 45 sec
4. Pattern S/D Implantation
1. Remove photoresist 2. YES oven for HMDS 3. Headway spin resist 5.5krpm for 30 sec for 1 um 4. Bake 90oC for 60sec 5. Expose KS for 1.0‐1.2 sec at Ch#1 (15mV/cm2) 6. Bake 115oC for 60 sec 7. Develop MF26A for 40 sec 8. Bake 110oC for 60 sec
Mask #2 :S/D Implant Mask
5. S/D Implant 1. Mount samples using resist on a 4” wafer 2. Si implant 20keV /1E14 cm‐2 3. Remove photoresist
6. Remove hardened resist Matrix O2 asher at 150W for 3 min
7. S/D Activation RTA (700 oC for 10s in N2) 8. ALD Gate Oxide 1. Wet etch Al2O3 in 20:1 BOE diluted 1:1 in DI for 1.5 min
2. NH4OH or (NH4)2S passivation 3. ALD Al2O3 8nm at 300oC
9. Pattern Gate Lift Off Resist Masking
1. LOL2000 spin 3krpm for 60 sec2. Bake 150oC for 4 min 3. Headway spin resist 5.5krpm for 30 sec for 1 um 4. Bake 90oC for 60sec 5. Expose KS for 1.0‐1.2 sec at Ch#1 (15mV/cm2) 6. Bake 115oC for 60 sec 7. Develop MF26A for 30 sec 8. Bake 110oC for 60 sec
Mask #8:Lift off Gate Mask
10. Deposit Gate Innotec 1000A Ni
129
11. Lift Off Gate Metal
1. Leave in 1165 for a few hours 2. Agitate samples in 1165 3. Rinse in acetone using a squeeze bottle. Squeeze hard
for a pressurized stream to remove any residual 4. Rinse in methanol and IPA 5. Blow dry in N2
12. Deposit Field Oxide
ALD 150oC 500cycles (use quick cycles recipe for a faster cycle since uniformity is not as critical for the isolation oxide)
13. Pattern Active Contact/Gate Same as for Mask #1 or Step #2
Mask #4:Active Contact
14. Wet Etch Field Oxide and Gate Oxide
Wet etch Al2O3 in 20:1 BOE
15. Deposit S/D Contact
1. NH4OH:DI = 1:1 for 3 min 2. AJA sputter thin SiN or other ultrathin dielectric 3. Innotec evaporate 1000A Al
16. Pattern S/D Contact Etch Mask Same as Mask #1 or Step #2
Mask # 5: S/D Contact Etch Mask
17. Wet Etch S/D Metal
1. Al Etchant2. Quick HF dip for SiN removal
18. Remove Resist 1. Heat PRX‐127 to 40oC and leave samples for 20 min 2. Rinse in running DI water for 5 min 3. Blow dry in N2. Ensure samples are completely dry 4. Heat PRS‐1000 to 40oC and leave samples for 10 min 5. Rinse in running DI water for 5 min 6. Blow dry in N2
19. Pattern Body Contact Lift Off Mask
Same as Mask #8 or Step #9 Mask #6:Lift Off Body Contact
1. Leave in 1165 for a few hours 2. Agitate samples in 1165 3. Rinse in acetone using a squeeze bottle. Squeeze hard
for a pressurized stream to remove any residual 4. Rinse in methanol and IPA 5. Blow dry in N2
130
3. Tips and Tricks
Wet Etching Recipes:
⋅ Wet etch rates can vary from day to day with if there are changes in the temperature or humidity and can also depend on the density and dimensions of the patterns. Dummy samples should always be used to calibrate the etch rate.
⋅ Dummy samples should be made with the real samples, for example during ALD oxide or metal deposition extra dummy samples should be added. If a metal layer is being patterned, these dummy samples should also be patterned with resist.
⋅ To calibrate the etch rate of an oxide, measure the initial oxide thickness with the ellipsometer. Etch a few samples with equal time spacings such as 20, 40, and 60 seconds, then measure the thickness and calculate the average etch rate.
Ion Implant Preparation:
⋅ To implant small pieces, secure the samples on a 4” Si wafer using SPR3612 resist as a sticking layer. Place small dots of resist and place the samples on then bake the wafer at 100oC for 5 to 10 min. Do not bake the wafer at too high of a temperature because it may cause the resist patterns to crack.
⋅ For extra precaution kapton tape dots can be used to secure the sample corners.
Resist Removal in JT Baker PRS-1000:
⋅ PRS-1000 can be used to remove even hardened photoresist.
⋅ SNF wet benches have the PRS-1000 heated to 40oC, however the manufacturer states the resist stripper should be used between 65-85oC. At these higher temperatures, the PRS-1000 strips most resists in 5-20 min without needing the help of PRX-127.
⋅ Caution: When heating the solution make sure to continuously monitor the temperature. Be sure not to exceed the flash point of 96oC.
131
Lift-Off Photoresist Patterning:
⋅ As illustrated above, the LOL2000 + SPR3612 photoresist dual layer works because the LOL material is not photosensitive, so it uses the developed PR as a mask. During the overdevelopment time an undercut pattern is created in the LOL layer. The undercut profile tends to create a small gap so not only is the metal deposition thinner, but the 1165 remover can also penetrate more easily.
⋅ When using LOL, make sure not to over develop the pattern because if there is too much undercut the resist may collapse making the pattern a single layer resist.
⋅ Develop several dummy samples with different development times and check these samples under the optical microscope before proceeding with the real samples. The idea undercut is about 1μm, so under a 50X magnification the pattern should look like two very close lines. If there is only one line then the LOL has not begun to develop the undercut. If there are two clear lines with a gap in between then the sample has been developed for too long.
Metal Lift-Off in Shipley 1165 Microposit Remover:
⋅ Typically for dual layer lift-off patterning (LOL2000 + resist) the metal will lift off after a few hours of soaking in 1165. If the pattern does not lift off, you can try:
1. Heating up the 1165 to roughly 60oC which will speed up the lift-off process significantly. Make sure you heat it up in the water bath at the solvent wet bench rather than using a hot plate for better temperature control. Make sure not to approach the flash point of 88oC.
2. Sonication of the sample in 1165 or acetone is another option. Turn the sonication power down to the lowest and sonicate in 30 sec intervals and check the patterns under a microscope. Caution: If the metal does not adhere well to the underlying layer the pattern may be roughened or in the extreme case the pattern can be completely lifted off. In this case an ultrathin Ti adhesion layer of 5A can help.
3. Certain metals lift off better than others. For example Pt and Ni lift-off more easily than Au or Al, so it may be helpful to try a different metal.
substrate
LOL2000
PR PRPR
substrate
PR PRPR
substrate
PR PRPR
132
Publications
Journal Publications
J. Hu and H.-S. Philip Wong, “Impact of Forming Gas Annealing on the
Electrical Characteristics of ALD Al2O3/ In0.53Ga0.47As MOSCAPS and
MOSFETs,” Journal of Appl. Phys., submitted.
J. Hu, K.C. Saraswat, and H.-S. P. Wong, “Impact of Fixed Charge on Metal-