Development Status for JAXA Critical Parts, 2010 Oct. 11th 2010 Electronic Devices and Materials Group Aerospace Research and Development Directorate, JAXA Satoshi KUBOYAMA [email protected] The 23rd Microelectronics Workshop
Development Status for JAXA Critical Parts, 2010
Oct. 11th 2010
Electronic Devices and Materials GroupAerospace Research and Development Directorate, JAXA
Satoshi [email protected]
The 23rd Microelectronics Workshop
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Background
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• Increased demands for high performance space systems
• Increased cost for LSI fab.• Decreased availability of cutting edge
devices for space applications.
Critical parts for space systems were selected to develop advanced space systems by Space Parts Engineering Committee.
Mismatch of demand and supply
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Overall status for devices already qualified
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High performance Microprocessor (64bit MPU)
Synchronous memory (Burst SRAM)QT was successfully completed in 2007.
100MHz operation, 180nm Bulk CMOS technology. QT was successfully completed in 2008.
200MHz operation, 180nm Bulk CMOS technology.Cache requires recovery by software for SEUs.
DC/DC converterNo magnet wire structure, 90% efficiency.QT was successfully completed in 2007.
Power MOSFET4 rated voltages, 3 die sizes are processes as a single wafer lot.QT was successfully completed in 2008 (n-ch, 100-500V).
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Devices Already Qualified
64 bit MPU, 200MHz36 Mbit Synchronous
SRAM, 100MHz
DC/DC converter N-channel power MOSFETs
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Flight demonstration (SDS-1)
SDS-1 : Small Demonstration Satellite #1
AMI : Advanced Micro processing In-orbit experiment equipment
1st phase critical parts
SDS-1 was successfully launched on Jan. 23rd, 2009.
Sun-synchronous orbit, 666km
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SDS-1 Results
Time [h]
SEU
rate
[SEU
s/h/
bit]
BSRAM
Cache
CREME96
Observed SEU rates were in agreement with the rate estimated by CREME96 for both cache and Burst SRAM.MBU (Multiple Bit Upset in a single word) were not observed as expected. All bits in a word were located physically isolated regions and control circuits were designed utilizing RHBD technique.
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SOI ASIC*Extremely high SEU immunity (>64 MeV-cm2/mg) by patented RHBD technique.QT will be completed by the beginning of Nov. 2010.
Same design with bulk version of 64 bit MPU, but no PLL and 50MHz operation. ½ power consumption.Already shipped for some science missions.
64bit MPU on SOI*
SOI FPGAChip design has just completed.QT will be completed in 2011.
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*Separated presentations will be made
Overall status for devices in development
SOI ASIC, RF analog extensionWafer level QT will be completed in 2011.The wafer will be shipped for MCM for GPS receiver.
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Overall status for devices in development
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POL (Point of load) type DC/DC converter*
P-ch Power MOSFET
Small size, no magnet wire structure.QT has just completed in Oct. 2010.
2 rated voltages, 3 die sizes are processes as a single wafer lot.QT will be completed in 2010 (100, 200V).
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450k,1M ASIC gates
SRAM based re-configurable FPGA.(Based on ATMEL architecture)
FPGA
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Target Specification for SOI FPGA
0.15μm commercial FD-SOI foundry withpatented SEU/SET free primitive circuits.(RHBD techniques used)1.5V for core and 3.3V for I/Os.SEU/SET free up to LET of 64MeV/(mg/cm2) TID: 1kGy(Si) (100krad(Si)) Common to FDSOI
TID: Total Ionizing Dose LET: Liner Energy TransferRHBD: Radiation Hardened By Design
Joint development with CNES / ATMEL
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Development schedule for SOI FPGA
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FY2009FY2007 FY2008 FY2010 FY2011
Qualification Test
FPGA total chip design
FPGA release(450k gate)
FPGA Element design and evaluation
SOI process tuning & Yield ramp-up
Process qualificationSPICE & PDK release
Qualification Test
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Analog element evaluation for analog ASIC
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Up to 20 GHzNormal VT transistorsSuper low VT transistorsMIM capacitorsOctagonal spiral InductorsPoly Si resistorsDiodesLateral bipolar transistors (for voltage reference)
Initial Target is front end circuit for GPS receiver
FY2009FY2007 FY2008 FY2010 FY2011
Design and EvaluationInitial PDK release
Initial Design and Evaluation
RefinementsWLR
User circuit design
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P-channel power MOSFETs
Die Size 1/1 1/2 1/4
Package SMD-2TO-254
SMD-1TO-257
SMD-0.5TO-39
VDS(V) -100RDS(on) (mΩ) 30 70 150
VDS(V) -200RDS(on) (mΩ) 70 150 350
SEE Non destructive up to LET = 64 MeV/(mg/cm2)
Characteristics
Package outlines
FY2009FY2007 FY2008 FY2010 FY2011
Design and EvaluationQT
Initial Design and Evaluation
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SEU/SET free PLL for high performance MPU clock generationFrequency Range is 30-300 MHzAdditional RHBD technique with SOINo errors was demonstrated with LET of 64 MeV-cm2/mg
High speed SRAM for MPU cache memory (>300MHz)New 10-Tr SRAM cellTapeout of test chip was completed
New DICE based latches/FFsNew 3 nodes DICE circuit was designed with 90nm bulk
technology.
New challenges
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Summary
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We would like to accelerate the discussion concerning the candidates for the next phase items including possible collaborations with ESA and CNES.
For most of the critical parts already developed were successfully qualified and their performance in orbit was demonstrated by SDS-1.
Developments of POL, p-ch MOSFET, SOI FPGA and RF analog extension are in progress.
New rad-hard circuit elements are in investigation for next generation devices.