Development of Development of SiC SiC Power Power MOSFETs with Low On MOSFETs with Low On - - resistance resistance National Institute of Advanced Industrial Science and Technology (AIST) Power Electronics Research Center(PERC) Device&Process Team 1 Leader Kenji Fukuda
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Development ofSiCPower MOSFETs with Low On- resistanceconference.kek.jp/RPIA2002/talks/fukuda.pdf · SiC device Projected SiC device Channel Electrode Resistance Ion Implantation
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Development ofDevelopment of SiCSiC Power Power MOSFETs with Low OnMOSFETs with Low On--resistanceresistance
National Institute of Advanced Industrial Science and Technology (AIST)Power Electronics Research Center(PERC)Device&Process Team 1 LeaderKenji Fukuda
Theo
ryfor
S iC
Theo
ryfor
S i
Breakdown Voltage
CurrentSiC device
ProjectedSiC device
ElectrodeChannelResistance
Ion Implantation
Material ScienceDevice Science
Crystal Growth Device Processing
Device Fabrication
Defects
On-
R es i
sta n
ce
oxides
Theor
y for
SiC
On-
Res
ista
nce
On-
Res
ista
nce
Theor
y for
Si
Ultra low loss Power Devices Ultra low loss Power Devices Technology Japanese National Technology Japanese National
project(1998project(1998--2002)2002)
OutlineOutline
1.1. BackgroundBackground2.2. Present state of Present state of SiC SiC devicesdevices3.3. Problem & Solution of Problem & Solution of SiC SiC MOSFETsMOSFETs4. Gate oxide reliability4. Gate oxide reliability5.5. SummarySummary
Physical properties of wide gap Physical properties of wide gap semiconductorssemiconductors
Semi-conductors
3C-SiC
4H-SiC
6H-SiC
Si
GaAs
Eg(eV)Mobility (cm2/Vs)
Saturation velocity(cm/s)
Dielectric Breakdown field(V/cm)
Thermal conductivity(W/cm・K)
2.23
3.26
2.93
1.11
1.43
1000
900
500
1350
8000
ー
3×106
3×106
3×105
4×105
4.5
4.5
4.5
1.5
0.5
2.7×107
2×107
2×107
1×107
2×107
Si-MOSFET
ND=4x1015cm-3ND=4x1013cm-3
330μm
30μm
n np p
n-Thickness
1/10
Carrier Concentration
100 times
On-State voltageabout 1/200
On-State voltage 250V@50A/cm2
On-State voltage 1.2V@50A/cm2
SiC-MOSFET
np n p
SiCSiC vs. Si (3300V MOSFET)vs. Si (3300V MOSFET)
High temperature operationHigh temperature operation
SiC
1. High thermal conductivity
2. Wide energy gap
1. High temperature operation is possible.
→ Powerful advantage
6H-SiC MOSFET at 300
J.W. Palmour et al.Physica B,185,461(1993)
Present state of Present state of SiC SiC devicesdevices
Rectifier
Inverter
DC
AC power supply
Motor(Load)
Diode・SBD (Schottky Barrier Diodes)・PiN Diode
Switching Devices・JFET(Junction FET)
・MOSFET
power electronics apparatuspower electronics apparatus
2.0
1.0
0
-1.0
-2.0
(100ns/div.)
Cur
rent
(A)
TimeReverse Recovery Characteristics
Si pn Diode
SiC-Schottky Barrier Diode
125 Ron :1 mΩcm2,Vbd=1kVSiCED(Siemens/Infineon)→ Sale($3/chip)
SiC-JFET CascodeArrengement with Si-MOSFET is necessary.
By P. Friedrich et al;”Static and Dynamic Characteristics of 4H-SiC JFETsDesigned for Different Blocking Categories”, Mate.Sci. Forum 338-342,2000,p.1243-1246.
Disadvantage of Disadvantage of SiC SiC JFETJFET
SiC JFET(SIT) is nomally-on device.
SiC MOSFET is ideal because it is normally-off type device.
Problem of Oxide reliabilityProblem of Oxide reliability1. Energy barrier height is small.
3. Working temperature of SiC is expected to be higher than that of Si.
2. Carbon reminds in SiO2 film.
φb SiO2(9eV)
SiElectron injection into SiCoxide is easier than that of Si.
Residual carbon causes large leak current.
Circumstance of SiC oxide is harsh.
φbSiO2(9eV)
SiC
Current VS. Gate voltageCurrent VS. Gate voltage
10-2310-22
10-2110-2010-19
10-1810-17
1 1.1 1.2 1.3 1.4 1.5
J/E2(A/V2 )
1/E(×10 -9,m/V)
Φeff=2.86eVm ox/m=0.42
10-1310-1110-910-710-510-310-1101
0 2 4 6 8 10 12 14
J(A/cm2 )
E(MV/cm)
9.5MV/cm(This is same as Si MOS)
R.T.
Long time reliability at high temperature is important. → Data is insufficient.
SummarySummary1. 1. SiCSiC JFETJFETRon=70mΩcm2、Vbd=2000VNormally-on、Cascode arrangement is necessary. → MOSFET is ideal device.2. 2. SiCSiC MOSFETMOSFET(1) Contact and Sheet Resistance is sufficient low.(1) Contact and Sheet Resistance is sufficient low.(2) MOS interface control technique(2) MOS interface control technique・μFE of 216cm2/Vs was achieved.・Lateral resurf MOSFETRon=51mΩcm2、Vbd=630VDynamics characteristics: rise time=20ns, fall time=15ns・DIMOSFETRon might decrease below 10mΩcm2, I am investigating now it.・ Oxide reliability at high temperature is left-behind. I am investigating now it,too.