Development of 3.3V Flash ZE~PROM Cell and kay b~ Jeewika Ranaweera A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Department of Electrical and Cornputer Engineering University of Toronto 1999 O Copyright by Jeewika Ranaweera 1999
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Development of 3.3V Flash ZE~PROM Cell and
k a y
b~ Jeewika Ranaweera
A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy
Department of Electrical and Cornputer Engineering University of Toronto
1999
O Copyright by Jeewika Ranaweera 1999
Acquisitions and Acqui%&ns et Bibliographie Senrices services Wbgraphiques
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Development of 3.3V Flash zE'PROM Ceii and Array
Doctor of Philosophy, 1998
Jeewika Ranaweera Department of Electrîcal and Computer Engineering
University of Toronto
Abstract
Most of the conventional flash E~PROM ceIls have major limitations for Iow voltage
applications and s&er from slow programming speeds. This thesis descn i s a Zener based
MOS flash memory c d (ZE~PROM), programmed by hot electrons generated by a heavily
doped reverse biased p+n+ junction attached to the drain. The Zener based programming
rnethod provides a practical solution to some of the limitations of conventional channel hot
electron programming method. This celi operates with a single supply of 3.3V and achieves
an order of magnitude reduction of programming time compared to conventional flash
memory ceils. The reduced Zener breakdown current also enables many bits to be
programmed simultaneously. The ceil can be irnplemented in a NOR type mernory array. It
uses an orthogonal write technique to achieve fast programming with low power dissipation
and reduced drain disturbance. The modeling of the charge transfer behavior of the
ZE*PROM cell is investigated using 2-D device simulations to specify the charging and
discharging of the floating gate during programming and erasing.
Experimental ZE~PROM arrays were implemented in a 0.8pm iithography CMOS
process fiow in which the n- LDD step was replaced with a one sided p+ boron implant with
a doping level of -10~~crn-~ . This minor change to a standard CMOS process, makes the
concept highly attractive for embedded memory applications. A programming time of
850ns at 3.3V supply was achieved on fabricated test devices.
1 would Like to express my sincere gratitude to Professor C.A.T. Saiama and to
Professor W.T. Ng for their insightful guidance and invaluable assistance throughout the
course of this work.
1 am ais0 indebted to Mehran Aliabad for the countless hours of valuable discussion
both technically and personally. Special thanks to Elvira Guiersen and Ivan Kaiastrisky for
many helpfd suggestions.
My sincere thanks to Alberto Dibu-Caiole for his assistance in developing the ON0
layers. My appreciation extends to ail the staff and students in the Mîcroe1ectronic
Research Laboratory including Jaro Pristupa, Dana Reem, Anthoula Kampouris, Dod
Chettiar, Li Zhang Hou, Hormoz Djahanshahi, Sbahla Honarkhah, Dusan Suvakovic,
Mehrdad Ramezani, Sameh KhaIil and Diana Gradinam for a l l their help.
A special word of thanks to my husband Senaka who has been a constant source of
support and encouragement. And to my son Mano, for king the best baby a mother could
have.
Financial support provided by the Naturd Sciences and Engineering Research
Councii of Canada, Nortel, Gennum, Mitel and Micronet are gratefuliy acknowLedged.
.............................. 1.3.1 NOR Type Array Architecture ................ ....,... 10
1 .3.2 NAND Type Array Architecture ............................................. 11
1.3.3 V i a 1 Ground Array Architecture .............. ..... .......................... 12 1.4 Reliability of flash E'PROM ............................................................... 13
1.4.1 Drain Disturb .................................. ..,, 14 1.4.2 DC Program ............................................................................... 15
1.4.3 DC Erase .................. .-.. ...................~......................................... 16
.................................................................................. 1.4.4 Read Disturb 16 2 .................................... 1 -5 Limitations of Conventional flash E PROM Cells 16
................................................................ 1.6 Objective and Outline of Thesis 17
CHAPTXR 2 2 .............................................. The 33V ZE PROM Ce1 and A m y ArcKhchire 0 0 0 0 ~ ~ 0 ~ ~ 2
3 .7.6 Endurance Characteristics ........................................................ 96 2 Integrating the ZE PROM array in a full process ........................... .. ..... 97
Scaling of the Ceil ................................................................................... 101
........................................................................ A . f Fabrication Rocess Flow 109
APPENDIX B The h Based Layout Design Rules . m ~ œ œ œ œ œ ~ œ œ œ œ œ œ ~ œ ~ m œ ~ ~ m m œ m œ c m m m œ m œ œ m m œ œ œ œ œ œ œ œ œ œ œ œ m m œ œ l2û
............................................................. B.1 Active are= (Mask#L. LOCOS) 120
.................................................... Erasing condition of a flash memory celi 8
Energy band diagram representing the F-N tunnelhg of electrons fiom the
floating gate to the source region ................................................... ... 9
...................... Schematic diagram of a NOR-type flash E~PROM array ... 10
...................... Sc hematic diagram of a NAND- type Bas h E~PROM array 11
............... Schematic diagram of a V i a 1 Ground flash E~PROM array ... 12
The disturb conditions experienced in a NOR type flash E~PROM array 15
2 The proposed ZE PROM ce11 structure ..................................................... 23 2 ........................... ...................... Programming of the ZE PROM ceil ,.. 24
Erasing of the ZE~PROM cell .................~....~~~~~..~.~~~.~~~~~.............~......~~..~~ 2 5
Reading of the Z~PROM ce ll ................................................................. 26
......................... The equivalent capacitance mode1 of the Z~PROM ceH 27
The surface vie* of the ZE~PROM cell ......................................... .. 29
The cross sections of (a) ZE~PROM ceii and (b) conventionai flash
memory cell, showing the dimensions used for numerical simulations .... 33
Floating gate voltage vs . programming t h e of cells A and B .................. 34
Floating gate voltage versus floating gate charge of cells A and B ........... 35
Figure 2.10
Figure 2.1 1
Figure 2.12
Figure 2.1 3
Figure 2.14
Figure 2.15
Figure 2-16
Figure 2.17
Figure 2.18
Figure 2.19
Figure 2.20
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3 -8
Figure 3.9
(a) Hot electron current and (b) floating gate charge during programming
of ceils A and B ........................................................ .......................... 36
Drain current during programming of cells A and B ................................ 37
Electron Injection efficiency during programming .................................... 38 2 Floating gate voltage during erasing of a ZE PROM ceL ........................ 39
Floating gate voltage versus Boating gate charge during erasing of a 2 ........................................................................................... ZE PROM ceU 39
F-N tumehg current during erasing of a E~PROM ce11 ..................... 40
FIoating gate charge during erasing of a ZE*PROM cell .......................... 40 2 Read current in a ZE PROM ceU ...................................... ................... 4 1
The ZE*PROM implemented in a NOR type array architecture ............... 42
Orthogonal prograrnming (cells P and R) of the Z~PROM array (h is
................................................. flowing in all the celis connected to B U ) 43
Drain disturb, by hot hole injection, in the unselected cells of the array
(cell Q). while ceiis P and R are king programmed ........................ .... ..44
Cross-sectional diagram of the proposed ZE'PROM ce11 ......................... 50
2 Cross-sectional diagrams of the ZE PROM process ................................ 56
Doping profile of the gate structure and the b u k region . The coordinate
............................. y=.0.58 mm corresponds to the top of the control gate 61
Doping pronles dong the nf drain of the Zener Junction . The coordinate
y4mm corresponds to the silicon surface ................................................ 62
Doping profiles dong the p+ region of the Zener junction . The coorduiate
y=0mm corresponds to the silicon surface ................................................ 62
Doping profile of the Zener Junction in lateral direction at 100A from the
silicon surface . The coordinate x = û p corresponds to the edge of the
channel at the source side .......................................................................... 63
Experirnental HF C-V characteristics for the 85A thin gate oxide ........... 66
Breakdown distribution obtained from 50 capacitors on a wafer .............. 68
The ON0 intcrpoly dielectric composition ..................................... .......... 70
Figure 3.10 The energy band structure of the ON0 dielectric .......................... ..........- 7 1
Figure 3.1 1 Leakage current vs. control gate voltage in ON0 and oxide test structure73
Figure 3.12
Figure 3.13
Figure 3.14
Figure 3.15
Figure 3.16
Figure 3.17
Figure 3.18
Figure 3.19
Figure 3.20
Figure 3.2 1
Figure 3.22
Figure 3.23
Figure 3.24
Figure 3.25
Figure 3.26
Figure 3.27
Figure 3.28
Figure 3 -29
Figure 3.30
Cntical breakdown voltage vs. the number of oxide and ON0 dielectric
capacitor samples .-......-.............*.... .-......., . . . . . . ................. 74 + + Experimental breakdown characteristics of the p n junction .................. 75
2 Layout design d e s for a 0 . 8 ~ ZE PROM cell .... .................................. 77
Test masks layout used in the fabrication process ...................*.........-.. 79
Micrograph of the test mask (area 6000pmx6100p) ........................ 8 1
2 Micrograph of a 2E PROM ceiI ...... .-..... ............................................ 82 2 Micrograph of a ZE PROM array ............................ ..... ....... ................82
SEM micrograph of ceii cross section across the width of the device ...... 83
Threshold voltage vs. progranunhg tune of a Z~PROM ceU ................. 86 2 Threshold voltage vs. erase time of a ZE PROM ceil .... ........................... 87
Programmed and virgin V, disaibution for a 8x8 Z~PROM array .......... 88
Read current vs. source voltage as a function of control gaie voltage ...... 89
Read current vs. source voltage as a function of the p+ diffusion width... 90
Drain and gate disturb conditions in the unselected celis (Q, S, T, U and 2 V) of a ZE PROM m y ...... ..............- . --...--................................. . . 9 1
ThreshoId voltage as a function of stress time to illustrate drain disturb
characterïstics, due to the p+nf junction, in unselected programmed and 2 erased ZE PROM ceils ..-- ...... . . . . .. . . . . . .+. .. . . .. .. -. - -.m.-. . . - . . . . . . . . . . . . . . . . 9 2
Threshold voltage as a function of stress time to demonstrate the gate
disturb (undesired programming and erasing) of the unselected erased and
programmed ZE*PROM ceils that share a common word line ................. 93
Safi wrïte time (time to cause a V, shift of 0.W) vs. the inverse of source
voltage applied during reading of a ZE~PROM cell at two different
Threshold voltage vs. writelerase cycles to v e m the endurance 2 c haracteristics of the ZE PROM cell ......-. .,..... ..... . ..... ...... .... . ... ..... ........... 97
Process flow of a modified CMOS process in which the additional 2 ZE PROM steps are identified (shaded) ........... . ..-- -.--.....-. -................ 98
Figure 3.3 1 Simulated and experimental programming time as a function of the gate
....................................... length for different flash ZE*PROM ceiis 102
Figure A- 1
Figure A.2
Figure A.3
Figure A.4
Figure AS
Figure A.6
Figure A.7
Figure A.8
Figure A.9
Figure A . 10
Cross-section after dry etching the nitride ......................................... 109
. Cross-section showing the Kooi effect after LOCOS formation ............ 1 10
................ Cross-section after gate oxidation and V, adjustment implant 111
.................. Cross-section a£ter patterning of the floating gate poly layer 112
Cross-section after etching of the gate structure ..................................... 114
......................................................... Cross-section after SWS formation 115
Cross-section after sourceidrain formation ............................................. 116
................................................ Cross-section after aiuminum sputtering 117
.................................................. Cross-section fiom the program section 118
Cross-section of the read section ......................................................... 118
2 TABLE 3.1 ZE PROM cell process summary .............................................................. 57
TABLE 3 2 Description of the rnasks in the ZE*PROM process ................................. 76 TABLE 3.3 Layout design d e s for the ZE~PROM cell ............................................. 78
................. TABLE 3.4 Summary of the ZE~PROM process and electncal parameters 84
Introduction
1.1 Flash E~PROM Development
In 1970, Frohman-Bentchkowsky [Il developed a programmable memory cell based
on a MOS field effect transistor, with the addition of a floating-gate buried in the insulator
between the substrate and the control-gate as shown in Fig. l.l(a), In this celi, electrons
are injected into the floating-gate via hot electron injection and removed fiom the float-
ing-gate by ultraviolet light. This ceil is known as the UV-EPROM (Ultra violet Electrï-
cally Programmable Read Only Memory). In the late 1970s, several attempts were made
to develop Elechicaily Erasable and Programmable Read Only Memory (EEPROM or
E~PROM) cells that use electron tunnelhg through a thin tunnel oxide for programming
and erasing operations [l] as shown in Fig. l.t(b). The E*PROM ce11 is a two transistor
ce11 that consists of a select transistor in senes with a programmable transistor. It exhiliits
limited endurance (the number of write/erase cycles that a memory can endure before faiI-
ure) due to thin tunnel oxide breakdown. It bas slow programming speeds (-lûms), and
has lower density as compared to a UV-EPROM cell. To overcome the tunnel oxide break-
down problem and the slow programming speed of the E~PROM c d , the FCAT (Floating
Si-gate Channel Corner Avalanche Transition) memory ce11 was proposed in 1978 and is
illustrated in Fig. l.l(c) [4]. It uses a reverse-biased junction in avalanche to inject hot
1
electrons and hot holes over a süicon dioxide b b r for proogramming and erasing respec-
tively. However, this method was thought to have deleterious effects on cell reiiability and
endurance due to the large junction breakdown current and operating voltages used, as
well as the injection of hot holes into the gate oxide- Tunnel oxide
floating-gate I
psubstrate
control-gate 1
p-substmte
p-substrate
(a) W-EPROM ceLi [2] (b) E*PROM transistor [3]
(c) FCAT ceil, surface view and cross sections at xx and yy [4]
Deeper source
\
I p-substrate I I p-substrate I (d) ETOX celi 121 (e) NAND ce11 CS]
Figure 1.1 Different non-volatile memory ceUs
2
In 1984, the combination of hot electron programming and tunnel erase
was used to develop a single transistor 'Yiash'' E'PROM cell [l]. The flash acronym
cornes from the fact that the cell cannot be erased one byte at a tirne but
erasure must occur for the entire chip or large blocks of the chip. The cell
occupies a smaLler area and offers better endurance reliability over the previously
described non-volatile memory cells. The flash E~PROM cells that are available
on the market today, use either hot electron injection or twiaeling for programming,
while all use tunneling for erasing. These cells attempt to optimize the trade-off
between cell size, process complexity and performance. Out of ail these flash
memory cells, the most commoniy used one is the E T O X ~ cell (EPROM Tunnel
Oxide) developed by Intel [2]. A cross-section of the ETOX cell is s h o w in
Fig. l.l(d). The cell uses a very thin nuinehg gaie oxide of -100A and has
a deeper source junction compared to the drain to facilitate the tunnel erase
procedure. The drawback of the ETOX cell is that it requires a dual power
supply for cell operation. The strongest competitor to the ETOX approach is the
NAND cell developed by Toshiba [SI and shown in Fig. l.l(e). It uses tumeling
for both programming and erasing mechanisms. Due to the low current requirements
of the tunneling mechanism, the voltages required for cell programming and erasing
can be generated on chip. This cell also has a smaller ce11 area compared to
that of the ETOX tell, The NAND memory array achieves its dense layout by
sharing a single bit line contact between a large number of memory cells arranged
in series in a single column. WhiIe the NAND type flash E~PROMS are very
useful for low-power and high density mass storage applications, the typical prograflltning
time is on the order of milliseconds.
There are many other approaches for flash ceil designs that seek to blend
the advantages of the ETOX and NAND cells. These approaches also address
one or more features of an ideai non volatiIe memory, which are: fast reading,
writing and erasing, high density, and high endurance.
In the foilowing section, the basic operathg pnnciple of a conventional
flash rnemory cell that uses channel hot electron injection for programming and
tunneling for erasing will be descriid.
1.2 Basic Operathg hinciple of a flash E~PROM ceiJ
The basic operating principle of the flash memory ceii, Uustrated in Fig.
1.2, involves the storage of charges in a floating polysilicon layer or gate that
is completely surrounded by a dielecaic, usually thermal oxide.
p-substrate
Figure 1.2 The storage of charge in the floating-gate of the ceU
By manipulating the charge in the fioating-gate (43, the threshold voltage,
(V,) of the transistor can be modified to switch between two distinct values.
These are conventionaily defined as the "0" (programmed state), and the "I"
(erased state) as illustrated in Fig. 1.3. The V, shift caused by the stored charge
Qfg on the floating-gate is given by:
where Cfg is the capaciiance between the floating-gate and the control-gate, VQ
and Vte correspond to the threshold voltage of the prografnmed and the erased
States respectively.
The information content of the device is detected by applyhg a voltage
to the control-gate between the two possible threshold voltages. In one state, the
transistor is conducting current, while in the other, the transistor is cutoff. To
provide a non-volatile device, the injected charge must remain stored in the floating-gate
when the power supply is rernoved-
661" cw' h without with
Vte
Figure 1.3 The influence of charge in the floating-gate on the threshold voltage of the ceil
At high drain biases, the electrons that are accelerated by the electric field
at the drain side of the channel gives rise to impact ionization at the drain, in
which both electrons and holes are generated. The highly energetic holes are
coUected at the substrate contact and form the so-cailed substrate current. The
electrons, on the other hand, are coiiected at the drain, Some of these electrons
gain enough energy to surmount the Si02 energy barrïer. If the oxide field favors
injection, these
floating-gate as
electrons overcome the oxide barrier and are injected into the
shown on the energy band diagram in Fig, 1.5 161,
Silicon Oxide Poly-Si Channel Gate floating-gate
Figure 1.5 Energy band representation of hot electron injection on to the floating-gate
The magnitude of the hot electron gate current is dependent on both the
applied control-gate and drain voltages. This means that the gate current is determined
by the number of hot electrons and their energy (which is Iargely dependent on
the Iateral elecûic field in the channel of the transistor). The gate current also
depends on the oxide field, which determines the fraction of hot electrms that
can actually reach the gate. Processing and geometrical parameters such as the
7
gate oxide thickness and the effective channel Iength aiso Wuence the amount
of injection current,
1.2.2 Basic Erasing Mechsnism
Erase in a conventional ceil is achieved by applying a positive voltage on
the source, and a negative voltage or ground to the control-gate as depicted in
Fig. 1.6. The high fields across the gate oxide results in electrons tunnelhg out
of the floating-gate to the source by Fowler-Nordheim (F-N) tunneling 17, The
field in the gate oxide depends on the floating-gate capacitive coupiing to the
source, the control-gate and the channel. Once the electrons are removed fiom
the Roating-gaie, the V, of the device is Iowered to the erased state.
= - or GND v'g r\
l p-su bs trate I
Figure 1 -6 Erasing condition of a 0ash memory cell
In F-N tunneling, when a large voltage is applied across the floating polysilicon
gate-SiO2-silicon structure, its energy band diagram will be as shown in Fig. 1.7.
Due to the high electric field, electrons in the polysilicon conduction band see
a triangular energy barrier with a width dependent on the applied field. At sufficiently
high fields, the width of the barrier becornes small enough that electrons can
tunnel through the oxide barrïer from the Boating-gate into the source region. A
significant tunnel current can be observed when the oxide thickness is reduced
Figure 1.7 Energy band diagram representing the F-N tunnelhg of electrons fkom the
floating-gate to the source region
The nuineling current density J through the oxide is exponentially related
to the applied electric field by the equation
(-B )/E J = Ae
where A and B are constants and E is the electric field [7]- To keep the erasing
voltages low, the hmnellîng oxide thickness needs to be small, consistent with
reliability and manufacturability requirements. High fields present during the tunneling
operation can result in severe degradation of the tunnelling oxide, which cm
cause Mure of the memory cell.
1.3 Array Architectures
The flash memory celis can be configured into different types of array
architectures. These include the NOR, NAND and Virtual Ground architectures.
9
1.3.1 NOR lPpe Army Architecture
The NOR-type array show in Fig. 1.8 is comouly used to implement
flash E~PROMS CS]. In the horizontal direction, the control-gates of the ceiis are
connected together by polysilicon to fom the word ihe (WL). In the vertical
direction, the drain and source contacts of the cells are comected to metal bit
lines (BL) and source b e s (SL) respectively. CeU address enables a specîfic word
and bit line and in combination they select one memory cell w i h h the array-
Al1 non-selected word and bit lines are connected to ground.
BL1 BL2 BL3 BL4
1
Word Line B k Bit Line SL = Source Line
2
I SL 1 SL2 SL3 SL4
Figure 1 -8 Schematic diagram of a NOR-type flash E~PROM array
In this array, read and write operations are done in a sunilar manner
except for the clifferences in the applied voltages. The advantage of this architecture
is the larger read current which leads to a fast access tirne for the memory cell.
Intei's ETOX cells are configured in a NOR-type array architecture [8].
10
1.3.2 NAND TPpe Array Architecture
NAND flash memory is a relatively recent architecture pioneend by Toshiba
[SI. Fig. 1.9 shows the interconnection of transistors in a NAND array- The high
density in this array is obtained by reducing the number of bit line contacts
required within the array. The memory ceiis are isolated at each end of the
column by select gates.
BLO BLI I
WL= Word Line B k Bit Line
Metal a+ - -
1 1 i f Polysilicon
I I W L O
I I
I I I I
I i
1 1 1 I -15
I I SLO SLl
Figure 1.9 Schematic diagram of a NAND-type flash E'PROM array
In this architecture, the intemal program and erase operations are done by
using F-N tunneling. NAND flash memory applies voltages to the substrate and
to the control-gate. nie required voltages can be generated on chip due to the
low currents in the tunneling mechmism. This makes the NAND ceil ideai for
low voltage portable applications.
The F-N tunneling mechanism is a relatively slow process when compared
to hot-electron injection. Typical programming times are on the order of milliseconds.
The access time is dso slow because of the s m d read currents that result fiom
the ceIls that are connected in series in the array. To overcome these limitations,
reading and Wnting of the array are done in paraUe1.
1.3.3 Voirtual Ground Array Architecture
Another array architecture that does not have bit line contact openings to
achieve minimum device area is called the virtual ground architecture 191. This
architecture uses diffbsed bit lines instead of metal bit lines and is illustrated in Fig, 1.10.
Diffused bit Iines I I -1
I - I 1 - 1 - I I I I I I D
I I I I l I I I
- I I - I - 1
I I I L I I t I I
BLL BL2 BL3 B U BL5
I I l I
m2 I WL= Word Line
1 - f BL= Bit Line
I - 1 f I t
Figure 1.10 Schematic diagram of a V i a I Ground flash E*PROM array
I - 1 - 1 1 -
t 1 I I I
I i
I I I
I I
I I
I I
While the virtud ground architecture leads to reduced m a , it exhibits many
disadvantages. When a certain word h e (WL) and a bit line (BL) are selected,
two ceils are addressed dong the same word line row. For example, when WL1
and BL3 are addressed, both ceiis A and B are selected. Therefore, ceU B too
would be erroneously programmed or read. To avoid this, all the bit Lines to the
right of BL3 have to be raised to the same voltage as BL3. This causes the
drains and the source regions of the cells to the right of cell A to have the
same potential thus complicating the addressing of the memory.
The high resistance in the dBbsed bit lines is another undesirable feature
of this array. To compensate for the potential drop dong the bit Line, a large
drain voltage is required. The read current also degrades due to the high resistance
in the bit lines.
1.4 Reliability of flash E~PROM
Degradation due to progrderase cycling is the most important reliability
issue for flash memory devices. The limiting factor on the number of program
and erase cycles obtahable is usudy due to the degradation of the gate oxide
[Il]. Holes generated during erase at the source side get injected into the gaie
oxide resulting in V, degradation. Electron trapping in the oxide also occurs after
several programming cycles. Trapped electrons decrease the rate of programming
as the electrons that flow through the oxide now encounter locally repulsive fields.
Therefore, as the number of cycles increases, the trapped charges begin to slow
down the movement of electrons back and forth to and from the fioatuig-gate.
This leads to an increase in program and erase tirnes, which is of significant
concern for the system designer. This condition c m be minimized by proper growth
of the gate oxide to reduce the density of electron ûaps.
Another cntical concem in the fiash E~PROM cells using thin oxide based
processes is the storage of charge (10 years) under normal chip operating conditions.
Leakage through the tunnel dielectrïc or interpoly dielectric is the basic charge
loss mechanism- The two worst case conditions for charge loss, are control-gate
high and drain low, and control-gate low and drain high. These two conditions
lead to leakage through the interpoly dielectric and leakage through the tunnel
dielectric thus producing erroneous data k i n g stored in a cell. The disturb mechanisms
that affect data integrity are drain disturb, DC program, DC erase and read disturb ClO].
1.4.1 Drain Disturb
Drain disturb occurs when programmed cells are sharing the same bit line
with a ce11 that is king programmed. This situation is Uustrated in Fig. 1.1 1
where an aiready programmed ceil A is experiencing drain disturb while ce11 B
is being programmed. Under this condition, the word line of ceU A is grounded
and the bit line is pulled to Vdd. Th" creates a high field between the drain
and gate for cells sharing the bit Line with the ceil that is king programmed.
If these cells are in the programmed state, this may cause some electrons to
tunnel from floating-gate to the drain leading to a lower threshold voltage thereby
erroneously erasing the ceils. For these cells to be immune to this leakage, no
change in the stored charge on the floating-gate must be observed for the total
time that it would take to program al1 the cells dong a bit line.
Figure 1.1 1 The distub conditions experienced in a NOR type flash E~PROM array
Erased cells which share a common word Line with a ce11 that is king
programmed, suffer from DC program. When a high voltage is placed on the
gate of the ce11 that is bekg programmed, the erased ceiIs sharing the cornmon
word h e are exposed to this voltage as weli- The high electric field across the
gate oxide of these erased cells may cause some electrons from the substrate to
tunnel across and accumulate on the floating-gate, thereby raising the threshold
voltage. This condition is shown in Fig. 1.1 1 where ce11 C is experiencing the
gate disturb condition while ce11 B is being programmed. For the celi to be
immune to this leakage, no change in the stored charge on the floating-gate must
be observed for the total time that it would take to program ail cells dong that word line.
1.4.3 DC Erase
DC erase occurs to programmed celIs sharing a common word line with
a celi that is king programmed In this case, the high electric field causes some
of these programmed cells to loose electrons by conduction through the interpoly
dielectric. Fig. 1.1 1 shows ceil D leaking charge whiie ceil B is being programmed.
This cm leave cell D in an erased state.
1.4.4 Read Disturb
During prograrn and read operations of the Bash memory ceils, the voltages
applied to the control-gaie and to the drain are both positive and curent flows
through the device. The only ciifference between the read and the prograrn condition
is the magnitude of the voltages applied at the drain and gate of the cell. Therefore,
even a smail drain voltage can result in electron injection resulting in erroneous
programming of the ceU.
1.5 Limitations of Conventional flash E~PROM CeUs
One of the major limitations of flash E~PROM devices which rely on conventional
channel hot electron injection for programming, is the need for an external higbvoltage
power suppiy (>SV) to program within a reasonable time. In this programming method,
when the channel length is reduced to the sub-half micron regirne, the drain voltage must
also be reduced to avoid punchthrough breakdown. This limits the electric field at the
drain thus reducing the hot electron generation efficiency. Therefore, this p r o g r d g
method lirnits the possibility of using flash E*PROM for low voltage (Q.3V) applications.
The channel hot electron p r o g r h g method also generates very high source-to-dfain
currents (in the range of milliamperes). This limits the number of cells that cm be pro-
grammed at one tirne.
The corner avalanche injection method used in the FCAT cell does not result in fast
programming since the avalanche injectors are not located directly below the Boating-gate.
It also suffers fiom ceU reliability problems due to the large voltages used for program-
ming and the hot hole injection method used for erasing.
In the ETOX ceil erase operation, the high voltage (+12V) applied to the
source terminal generates hot holes that get trapped in the gate oxide. These
trapped holes result in V, degradation as the number of program and erase cycles
increases.
The slow programming speed (-10p) is another major drawback of existing
flash cells. This limitation, prevents their application as replacement for RAMs
and electronic hard disks.
Charge leakage through the interpoly dielectric and gate oxide is aiso of
critical concern in terms of reliability The disturb conditions such as drain disturb,
DC program, DC erase and read disturb affect data integrity of the flash memory ceIl.
1.6 Objective and Outline of Thesis
A flash E~PROM MOSFET ce11 using Zener breakdown at a heavily doped p+n+ junc-
tion was previously proposed by the author as part of her M.A.Sc thesis[l6]. The structure
involved two nfpf injectors one each at the source and drain sides of the charme1 and was
implemented in a 3pm process. The celL was proven operational at Sv
Given the increasing demand for portable applications, device dimensions as weil as
supply voltages must be scaled down to achieve higher packing deasity, higher speed and
Iower power dissipation. The objective of this thesis is to propose, implement and charac-
terize a modified 3.3V Zener-based MOS memory ceIl (&PROM) [12] programmed by
+ + hot electrons generated using a single, heavily doped reverse-biased p n Zener injector
attached to the drain. The ceil is implemented in a submicron (0.8p.m) CMOS compatible
process and achieves higher density., better programmr'ng speed reduced disturb condi-
tions and enhanced endurance characteristics, as compared to the previously proposed cell
[16]. The use of a 3.3V supply makes the present Z~PROM ceil suitable for a variety of
portable applications. In addition, the cell provides a practical soIution to some of the Lm-
itations of conventionai flash memory cells that use the channel hot electron programming
method.
A novel orthogonal write architecture, suitable for a ZE~PROM array is also pro-
posed. This write architecture minimizes drain disturb time and power dissipation while
maintainhg a programming speed of the order of several hundreds of nanoseconds in the
ZE~PROM ceils.
In Chapter 2, the 3.3V ZE~PROM cell and array architecture are presented.
The ceil operation is discussed by means of an analytical device mode1 and two
dimensional device simulations.
Chapter 3 discusses the fabrication process and the characterization of the
ZE~PROM cell and array. The fabrication of the test rnemory cells are carried
out in a 0.8pm, double polysilicon, CMOS process. Two-dimensional process simulations
are performed to define the process parameters. The characterization of the thin
+ + gate oxide, oxide-nitride-oxide (ONO) interpoly dielectric and the p n Zener junction
18
are investigated on fabricated test structures. The experimental ceil characteristics
such as programming, erasing, reading, endurance and reliability obtaiwd on fabricated
devices and arrays are also discussed in detail-
FinaMy, in Chapter 4 concIusions are drawn regarding the implications of
this ceii design and topics for future research are presented.
References
C. Hu, 'Wonvolatile Semiconductor Memories Technologies, Design and
Application", pp- 1-2, IEEE Press, New York, 1991.
B. Dipert and L. Hebert, 'Flash Memory goes mainstream", IEEE Spectnun, Vol.
30, pp 48-52, October 1993
A. KoIodny, S.T.K. Nieh, B. Eitan and J. Shappir, "Analysis and modehg of
floating-gate EEPROM ceiis", IEEE Transaction on EIectron Devices, Vol. 33, pp.
835-844, 1986-
M. Honuchi and H. Katto, "FCAT - A Iow voltage high speed alterable n-channel
nonvolatile memory device", TEEE Transaction on EIectron Devices, Vol. 26, pp.
914-918, 1979.
M. Momodomi, R. Kirisawa, R Nakayarna, S. Aritome, T.Endoh, Y Itoh, Y Iwata,
H. Oodaria, T. Tanaka, M. Chiba, R- Shirota and F. Masuoka, "New device
technologies for SV-ody 4Mb EEPROM with NAND structure ceil", IEDM
Technical Digest, pp. 412-415, 1988.
B. Eitan and D. Frohman-Bentchkowsky, "Hot eIectron injection into the oxide in
n-cbannel MOS-devices," LEEE Transaction on Electron Devices, Vol 28, p. 328,
198 1.
M. Lenzlinger and E.H Snow, 'Fowler-Nordheim tumeling in themaiiy grown
Si02," Journal of Applied Physics, Vo1.40, pp.278-283, 1969.
B. Dipert and M. Levy, 'Designhg with flash Memory", pp. 25-32, Annabooks,
San Diego, 1994.
W. Kammer, B. Sani, P. Kauk, R. Kazerounian and B- Eitan, "A new virtual ground
array architecture for very high speed, high density EPROMs," International
Symposium on VLSI Circuits, Proceedings, pp. 83-84, 199 1-
A. Ahmed, ''Flash Memory Reliability", EDN, p. 32, June 1994.
[ I l ] S. Haddad, C. Chang, B. Swamùiathan, J. Lien, ''Degradation due to hole trapping
in flash memory cells,? IEEE Electron Device Letter, Vol. IO, pp. 1 17-1 19, 1989.
[12] J. Ranaweera Kalastirsky, E. Gulersen, W.T- Ng, and C-A.T. Salama, "A Method
of Fabricating a Fast Programming flash E'PROM ceIl," U.S. patent application,
June 1996.
1131 J. Ranaweera, 1. Kalastirsky, E. GuIersen, W.T. Ng and C.A.T. Salama, "A novel
programming method for high speed, low voltage flash E'PROM cells", Solid State
Electronics, Vol, 39, pp- 98 1-989, 1996.
1141 J. Ranaweera, 1. Kalastirsb, A. Dibu-Caiole, W-TT Ng, and CAT- Salama,
6Terformance Limitations of a flash E~PROM cell, programmed with Zener induced
hot electrons", IEEE Non Volatile Memory Workshop. Paper #Z2, 1997.
[LS] J. Ranaweera, W-TT Ng and C.A.T. Salama, "Simulation, Fabrication and
Characterization of a 3.3V flash ZE~PROM array implemented in a 0.8pm
process", Solid State Electronics, accepted for publication.
[la J. Ranaweera, "Developrnent of a Hash EEPROM celi suitable for 5-V operation,"
M.A.Sc. Thesis, University of Toronto, April 1995.
CHAPTER 2
The 3.3V ZE~PROM Cell and Array Architecture
2.1 Introduction
Conventionai channel hot electron programming relies on biasing the device
at a large drain voltage to achieve a high channel electric field for hot electron
generation. A high positive gate voltage is used to obtain a high gate-to-drain
field to assist electron injection into the Roating-gate. Due to the high drain
voltage required for cell prograrnming, fiash E*PROM celis that employ the conventional
channel hot electron method are not readily suitable for low voltage applications.
Therefore, it is necessary to find alternative methods of injecting electrons to
program the ceil at lower voltages.
In this chapter, a flash E~PROM cell structure that incorporates Zener junction
breakdom to achieve very fast programming at low voltages is presented. This
ce11 uses hot electrons injected from the drain side to charge the floating-gate.
The ce11 exhibits excellent programmability at a supply voltage of 3.3V and has
considerable potentiai for applications in which hirther reduction in power supply
voltage are necessary
This chapter is organized as follows. First, the Zener based ZE*PROM cell
structure is presented and the methods of programming, erasing and reading are
22
discussed. The analytical mode1 of the ZE~PROM ceil based on a simple capacitor
model is developed. The device performance is then analyzed using two-dimensional
numerical simulations. This is followed by a discussion of the array architecture
used in implementation of the orthogonal programming technique that is needed
to reduce drain disturb and power dissipation,
2.2 Cell Structure and Operations
The optimized version of the ZE~PROM cell Cl-41, illustrated in Fig. 2.1, has a pç
pocket implant extending part-way across a portion of the width of the drain region to gen-
erate hot electrons for programmhg.
floating-gate
Figure 2.1 The propsed ZE~PROM ceil structure.
The heavily doped pfn+ junction in the reverse-biased condition is capable of gen-
erating the hot electrons required for programming at relatively low voltages. These hot
electrons result from Zener breakdown [a. If the doping densities of both the p and n sides
23
are greater than 10'~cm-~, the depletion layer at the junction is very thin and the eIectnc
field necessary for Zener breakdown is reached at voltages less than SV [a. Since the d o p
ing concentration of the n+drain region of the cell is on the order of 102°cm'3, the drain
breakdown voltage depends principaily on the ciophg of the pf region.
22.1 Programming
To program the Z~PROM ceII show in Fig. 2.2, the p*nf junction is reverse
biased to create an elecnic field of -106 Vkm and generate energetic hot electrons inde-
pendently of the channel length. At these fields, the electrons gain sufticient energy to sur-
mount the energy barrier between the silicon substrate and the SiOz gaie insulator. By
increasing the doping concentration of the p+ region, the depletion region can be narrowed
and the magnitude of the electric field peak c m be increased 151. Also associated with this
increase in the p+ region doping is a decrease in breakdown voltage. Therefore, the applied
drain voltage can be lowered
1 p - substrate V
ron populai ion.
Figure 2.2 Programming of the Z~PROM ceii
2.2.2 Erasuig
As depicted in Fig. 2.3, erasing is performed by Fowlec-Nordheim tunnelhg of
electrons fiom the floating-gate to the source. In this erasing method a negative voltage is
applied to the control-gate while the source is connected to the supply voltage.
vcg-
Figure 2.3 Erasing of the ZE'PROM ceii
2.2.3 Reading
Since the pC region adjacent to the drain region exhibits a low breakdom voltage,
which contributes to soft programming, the source region must be used in the read opera-
tion as illustrated in Fig. 2.4. In this ce11 design, the reduced channel width available for
reading also yields lower read current compared to the conventional Rash memory cells.
This can be compensated by using a larger device width, or if programming speed is not
critical, reducing the width of the pf dinusion.
1 p - substrate v I r
Figure 2.4 Reading of the ZE~PROM cell
2.3 Analytical Model of the ZE~PROM Cell
Similar to other flash memory cells, the presence of a floating, but conductive gate
inside the gate dielectric has important consequences from the device modeling point of
view. In this section, the floating-gate potential due to capacitive coupling during pro-
gramming, erasing and reading operations, and an analytical model for 1-V characteristics
are derived. This aoalytical model is a useful tool in predicting the behavior of the fabri-
cated ZE~PROM ceiis.
2.3.1 The Capacitor Model
To gain insight into the basic charge-transfer characteristics of the ZE~PROM
structure, a capacitive equivalent circuit was developed as shown in Fig. 2.5. The voltage
on the floating-gate is contrded through capacitive-coupling with the extemal nodes of
the device. Cfg is the capacitance between the controi-gaie and the fioating-gate, 5, s, Cd and Cs are the couphg capacitances between the floating-gate and the substrate, the p+
region, the drain and the source respectively.
Figure 2.5 The equivalent capacitance mode1 of the ZE~PROM ceil
When the device is operating in the program mode, the current through the thin
tunnel oxide is integrated and appears as a charge Qfg on the fioating-gate. The accumula-
tion of the charge on the floating-gate is reflected as a change in the threshold voltage V, of
the device. The relationship between Vt and Qfg is given by
where V~ corresponds to the initial Vt when Qfg = O. The threshold shift is proportional to
D.W. Hess and BE. Deal, 'Effect of Nitrogen and OxygenMitrogen mixtures on
oxide charges in MOS structures,*' J. Electrochem. Soc., Vol. 122, pp.1123-1127,
1975.
K. Iniewski, "High Frequency CV measurements", MRL Data Sheets.
R.M. Anderson and D.R. Kerr, "Evidence for surface asperity mechanism of
conductivity in oxide grown on polycrystalline silicon," J. Appl. Phys., Vol. 48,
pp.4834-4836, 1977.
A. Dibu-Caiole, J. Ranaweera, W.T. Ng and C-A.T. Salama, "ON0 inter-poly
dielectrics for novel flash E~PROM celIs", Canadian Semiconductor Technology
Conference, p.42, 1997.
S. Mori, N-Yasuhisa, T-Yanase, M- Sato, K. Yoshikawa and H.Nozawa,
"Reliability aspects of l0OA inter-poly dielectncs for high density VLSI's", VLSI
Symposium, Digest of Technicd papers, p.7 1-72, 1986.
S. Mori, N. Matsukawa, Y. Kaneko, N. Ami, T. Shhagawa, Y. Suiza, N. Hosokawa
and K. Yoshikawa, "EDM Digest of Technical Papers", pp-556-559, 1987.
[12] S. Mori, Y. Kawko, N.Arai, Y-Ohshuna, H-Araki, IGNarita, E,Sakagami and
K.Yoshikawa, "Reliability study of thin inter-poly dielectncs for non volatile
memory application", International Reliability Physics Symposium, pp. 132-144,
1990-
[13] S-Mori, M-Sato, YMikata, T-Yanase and K. Yoshikawa, "Poly-oxide/nitride/oxide
structures for highiy reiiable EPROM ceils", VLSI Symposium, Digest of
Technicd papes, pAI-4 1, 1984-
[14] B. Dipert and M. Levy, 'Designhg with flash Memory", pp. 25-32, Annabook,
San Diego, 1994.
[15] M. Lenzlinger and E.H Snow, "Fowler-Nordheim tunneling in thermaliy grown
Si02," Journal of Applied Physics, Vo1.40, pp.278-283, 1969.
[l6] S.T. Wang, "On the 1-V characteristics of tloating-gate MOS transistor", IEEE
h s . Electron Devices, Vol. 26, pp. 1292-1294, 1979.
[17] G. Verma and N. Mielke, ''Reliability performance of ETOX based flash
mernories", International Reliability Physics Symposium, pp, 158- 166, 1988.
[18] J. Ranaweera, W.T. Ng and C.A.T. Salama, "Simulation, Fabrication and
Characterization of a 3.3V flash E~PROM array implernented in a 0 . 8 ~
process", Solid State Electronics, Accepted for publication.
Cl91 N. Ajika, M- Ohi, H- Arima, T. Matsukawa and N. Tsubouchi, "A 5V only 16Mbit
flash EEPROM cell with a simple stacked gare structure^', IEDM Digest of
Technical Papers, pp. 1 15- 1 1 8, 1990.
[20] S M Sze, "Physics of Semiconductor Devices", Second Edition, Wiley, New York,
1981.
[2 11 1. Kalastirsky, "Design and fabrication of fast programming flash EEPROM ceIls",
M.A.Sc. Thesis, University of Toronto, A p d 1996.
100
Conclusions
In this thesis, a flash E~PROM ceiI and array that incorporate Zener injector
to achieve a programming speed of the order of severai hundreds of nanoseconds
was presented. This Zener based cell (ZE~PROM), uses hot electrons injected
fiom the drain side to charge its floating-gate and program the cell in 85011s.
Zener induced hot electrons for progranunhg yields very low drain currents by
comparison to the channel hot electron programming method used in conventional
flash E~PROM cells. Therefore, it is possible to program many bits simultaneously.
A method of programming a i l the required celIs in a bit-line (orthogonal programming),
that reduces drain disturb and power dissipation was aiso introduced. The erasure
is performed within 5ûms. To avoid soft programming during reading, the source
region is used instead of the low breakdown Zener junction attached to the drain-
Program and erasure can be done with a 3-3V supply and a charge pump to
generate the I12V to the control-gate to implement all cell operations.
With high speed programming and simple driving circu3s, the 3.3V Bash
Z~PROM design presented in this thesis would be useful in many portable applications.
It also offers potential to replace RAMs and electronic hard drives. The cell
dimensions can be easily scaied to further enhance its performance.
the development of a Zener based ceU that cm be operated from a single
supply voltage (33V), the ceii exhibits an order of magnitude reduction in programming
tirne compared to conventional flash E*PROM cells.
the design and fabrication of a CMOS compatible, double polysilicoo, 3.3V
ZE~PROM array,
the development of an orthogonal programming technique to reduce drain disturbance
and power consumption in Z~PROM arrays, and
the demonstration of a method to prevent soft-write in ZE'PROM c d s by using
the source region for reading.
Further research is necessary to elucidate the following issues that have
not been considered in this thesis, These include:
developing flash Z*PROM ceil that operates at voltages below 3.3V, and
çtudying the possibility of using the ZE~PROM cell for multilevel storage
APPENDIX A
Flash ZE~PROM Fabrication Process Description
A detailed description of the ZE~PROM fabrication process is given below.
This description is intended to serve as a reference for future work on the ZE~PROM
ceils. The wafers used in the fabrication process are p-type with resistivity IR-cm,
<LOO> orientation and 4" diametet Steps such as cleaning, photolithography and
photoresist removal are standard proceuing steps. Ail the steps described are optimized
to achieve the appropriate specifications for the Z~PROM cells and arrays.
The wafer cleaning process uses the 3-step cleaning method described in
UTICL Data Sheets. The following solutions in which the ratio is given by volume
are used. To remove heavy organic contaminants - H2S04:H& = l:l, to rernove
light organic contaminants - DI water:Hfi:NHQOH = 5A:l and to remove inorganic
contaminants - DL water:H202:HCl = 6:l:l are used. The thin oxide grown after
each cleaning step is removed by dipping the wafers in 5%HF for 5 seconds.
The photolithography process step to form 0.8pm line width uses Shipley
positive photoresist 1813. The rest of the photolithography process steps described
in the process flow use photoresist type MICROPOSIT 13501. The developer is
of type MICROPOSIT MF-312. Spinning of the photoresist is done at 6000rpm
-7000rpm for 40 seconds. The pre-bake and pst-bake are done at 90°C for 30
108
minutes. Photoresist development is done in 45 seconds in a solution containing
equai parts of DI water and developer. Acetone is usually used to remove the
photoresist M e r a high dosehigh energy ion implantation, the photoresist asher
machine is used to remove the photoresist-
A.1 Fabrication Process How
Clean the wafers using the standard 3-step cleaning process-
Grow a ~ O O A rhick stress relief dry oxide in the furnace at 950°C for 62 minutes.
Deposit a 1200A thick nitride layer in the LPCVD at 800°C.
Patterning of the device active areas using mask #1 (LOCOS).
Dry etching (RIE) of nitride is done to define regions for LOCOS field oxidation.
The cross section after this process step is shown in Fig. A.1.
Photoresist -+,
p-substrate
Figure A.1 Cross-section after dry etchùig the nitride
Cleaning of the wafers.
The LOCOS field oxidation at llOo°C for 85 minutes in steam. Target oxide
thickness is 7500A. The oxidation of nitride in stearn also produces amnonia
which can d i s e through the oxide to the Si-SiO2 interface and form a nitride
layer. This is known as the White Ribbon or the Kooi effect Cl] and is s h o w
in Fig. A.2. During gate oxidation, these nitride layers significantly reduces the
thickness of the gate oxide preventing the formation of the highest quality gate
oxide. The technique used to eliminate the Kooi effect is to add a step to
grow a sacrificial steam oxide (-1000A) which wouid oxidize the nitride interfafe.
This oxide layer is stripped and the gate oxidation is performed on the nitride
fiee silicon d a c e .
white Ribbon regions
p-substrate
Figure A.2 Cross-section showing the Kooi effect after LOCOS formation.
Cleaning of the wafers.
The growth of -85A thin gate oxide by using a dry oxidation method with
diluted oxygen. A gas combination of go%&, 8%02 and 2%HC1 is used at
I 1 0 0 ~ ~ for 5 minutes. The addition of % during the oxidation contributes to
a slower growth rate of the oxide thus making it possible to increase the
oxidation temperature to llOO°C at 1 atm. HCI is intentionally introduced into
the oxîdation ambient to improve both the oxide and the underlying silîcon
properties. Oxide improvements included a reduction in ion contamination, an
increased dielectric breakdown strength and a reduced interface trap densityi
110
Immediately a€ter the gate oxide is grown, the gas flow is changed back to
N2 to anneal the wafers for 30 minutes at llOO°C to reduce the amount of
fixed oxide charge Q, [2]-
A blanket threshold voltage adjustment implant consisting of boron, dose of
4 ~ 1 0 ~ ~ c m ' ~ at an energy of 30KeV is done after the growth of the gaie oxide.
The cross section after this step is shown in Fig. A.3.
V, adjustment implant
Gate Oxide
p-su bstrate
Figure A.3 Cross-section after gate oxidation and V, adjustment implant
In order to retain the thin gate oxide, a 3-step deanhg without dipping the
wafers in 5% HF is done pnor to the deposition of amorphous silicon.
First poly layer consisting of a 3600A thick amorphous silicon layer is deposited
by pyrolyzing 40% Silane at a pressure of 03Torr h a LPCVD reactor at
560°C. The reason for initial deposition of amorphous silicon is that the surface
is smooth which is important for the interface with the interpoly dielectric.
Improved surface smoothness, ailows a thin oude to be grown on the heavily
doped polysilicon without sacriking the quality of the oxide.
The amorphous sîiicon layer is subsequently implant doped with a phosphorus
dose of 8xl0'~crn-~ at an energy level of 30KeV to d u c e the sheet resistivity.
CIeaning of the wafers.
A RTO (Rapid Thermal Oxidation) at 1 10°C for 30 seconds is done to redistribute
phosphorus in the polysilicon to achieve a constant etch rate, for crystalhation
of the amorphous silicon layer and to grow a thin oxide on the wafers. This
oxide layer is necessary for better adherence of photoresist into polysüicon.
Patterning of the fioating-gate using mask #2 (FGPOLY)
At this stage of the fabrication, a photolithography is done to pattern the polysiiïcon
layer to cover the entire active device area. The undesired areas of polysilicon
above the LOCOS are wet etched after removing the thin pad oxide. Next,
the photoresist and the pad oxide on top of the polysilicon layer are removed.
The cross section after the etching is shown in Fig. A.4.
nC Polysilicon
r LOCOS
p-substrate - Gate Oxide
- - - - - - -- -- - -
Figure AA Cross-section a.€ter patterning of the fioating-gate poly layer.
Cleanin~ of the wafers.
The interpoly dielectnc consisting of an oxide-nitride-oxide (ONO) sandwich
with 200A of equivaient electrïc thickness is then fabrïcated [3]. This optîmized
ON0 thicknss is used to obtain good retention characteristics compared to
polyoxide. The 80A thin bottom oxide is fabncated in diluted oxygen at 9 5 0 ~ ~
for 8 minutes. The gas combination used in this step is 86%N2, 1 2 1 4 and
296HCl. Then a nitride layer of -190A is deposited in the LPCVD at 750°C
for 10 minutes. A wet oxidation of the silicon nitride layer is done at 950°C
for 40 minutes to obtain a 40A thin top oxide.
A second layer of arnorphous silicon is then deposited, doped and annealeci
to form the control-gate. This layer is proçessed with similar conditions as the
first polysilicon layer.
Cleaning of the wafers,
A layer of 4000A LPCVD oxide is deposited to serve as the mask in Reactive
Ion Etching (RIE) of the polysilicon and ON0 Iayers. At this point, ail the
layers that were grown and deposited in the back of the wafers are wet etched.
This is necessary to have a better control of the temperature during the Rapid
Thermal Anneal (RIA) step-
Cleaning of the wafers.
RTA is done next at 1 l00OC for 30 seconds to provide a uniform distribution
of implanted phosphorus and to dense the LPCVD oxide.
Patterning of the gate structure using masW3 (CGPOLY). This photolithography
step patterns the LPCVD oxide. To achieve a minimum of 0 . 8 ~ line width
for the gate structure, Shipley positive photoresist type 1813 is coated and
spun at 6000 RPM for 40 seconds. Mer p s t bakiag the wafers for 30 minutes
at 90°C, the mask is aïigned and exposed for 13 seconds using the Karl Suss
MA4 mask aligner,
The gate structure is then defined by dry etching. First the LPCVD oxide
Iayer is etched using the photoresist as the mask. Then the resist is stripped
and the thick oxide is used as the mask to etch the gate structure. The polysilicoa
Iayers are etched with CI2 gas, and the oxide and nitride Iayers are etched
with Freon gases- Duruig the etching of the floating-gate poly layer, care must
be taken to avoid etching the silicon of the source and drain regions.
Cleaning of the wafers.
A layer of ~ O O A LPCVD oxide is then deposited to serve as the screen oxide
for the next ion implantation- The cross section after this process step is shown
in Fig. AS. , /-- ScreeOing Oxide
p-substrate - Gate Oxide
Figure A S Cross-section after etching of the gate structure
Patterning the p+ Zener region using mask #4 (PZENER). This photoiithography
step patterns the p' region of the Zener junction and of the substrate contacts.
The alignment of the Mask #4 is the most cnticai one in this process.
A boron implant of 8 x l 0 ' ~ m - ~ dose and 25KeV of energy is used next to
form the p+ regions. This boron implant replaces the conventional n-LDD implant
in the CMOS process,
Cleaning of the wafers,
A side waü spacer (SWS) is fonned next by depositing ~SOOA of LPCVD
oxide, denswing the oxide, and dry etching. Tbe funiace cycle used to deus@
the oxide also drives-in the boron implant* The cross section at this process
step is shown in Fig, A.6.
sws --\
I p-substrate
Figure A.6 Cross-section d e r SWS formation
Cleaning of the wafers,
A 500A thick LPCVD oxide is deposited to serve as the screen oxide for
the next ion implantation.
Patternhg of the source and drain regions using mask #5 (NDEV). This
photolithography step patterns windows through which n+ source and drain regions
are implanted Arsenic with a dose of 5~10'~crn-~ and an energy of 120KeV
is used for this implantation. The SWS is used to form the self aügned n+
source and drain regions and also to avoid counter-doping of the p+ pocket-
Since this is a high energy implantation, the photoresist after the implant must
be removed by the asher.
CIeaning of the wafers.
Another LPCVD oxide layer of 8OOA is deposited to use as the isolation
Iayer between the devices and the metal Iayer. The wafers are annealed in dry
oxygen at 1000°C for 12 minutes. This annealing step densifies the thick oxide
and dso drives-in the implanted phosphoms ions to form the source and drain
regions. This drive-in step is very important to detennine the exact location
of the Zener junction, and its junction depai. The cross section after this process
step is shown in Fig. A.7.
r LPCVD oxide -80OChk
p-subs trate
- --
Figure A.7 Cross-section after source/drain formation
116
Patterning of the contact windows using mask #6 (CON). Wet oxide etch is
used to open these contact windows for difision and polysiiicon regions. Then
tfie photoresist is removed and the wafers are cleaned for medlkation~
A 0 . 8 ~ thick A1+2%Si is sputtered on the wafers. The cross section after
this step is shown in Fig. A.8.
1 p-substrate 1
Figure A.8 Cross-section after aiuminum sputtering
Patteming of the metal Lines using mask #?. The Alurninurn layer is pattemed
with photolithography and the undesired areas of Aluminum is wet etched in
a solution heated to 4S°C. The photoresist is removed and sintering is carried
out at 4 5 0 ~ ~ for 20 minutes in fomiing gas to make the contacts. The final
cross sections (program and read) of the device are shown in Fig. A.9 and
Fig. A. 10 respectively.
Figure A 9 Cross-section fiom the program section
p-subs trate
Figure A. IO Cross-section of the read section
[Il 0s. Trapp, L.J. Lopp and R-A. Blanchard, bcSemiconductor Technology
Handbook", Chap- 3, Technology Associates, CA, 1993.
[2] D.W. Hess and BE. Deal, ''Effect of Nitrogen and OxygenINitrogen mixtures on
oxide charges in MOS structures," J. Electrochem. Soc. Vol-122, pp.1123-1127,
1975.
[3] A. Dibu-CaioIe, J. Ranaweera, W.T. Ng and C.A.T. Salama, "ON0 inter-poly
dielecûics for novel flash E*PROM tells", Eighth Canadian Semiconductor
Technology Conference, p.42, 1997.
The h Based Layout Design Rules
The layout d e s for the ZE'PROM array are based on a minimum alignment
tolerance and a minimum line width of 2k, where h~~ These d e s are
listed below.
B.l Active area: (Mask #1, LOCOS)
'i-
0 LLOCOS FGPOLY -----
1- - - - J CGPOLY
1-1 Minimum width=14Â,
1.2 Minimum spacing= 30h
1.3 Minimum overlap of n+ diffusion -
1 -4 Minimum overlap of floating-gate poly=SX T 1 -5 Minhum overlap of control-gate poty=6h 1.6 Minimum width of pt Zenedli 1.7 Minimum overlap of p+ a n e r difhision=5Â.
0 LOCOS FGPOLY
2.1 Minimum width=2k
2.2 Minimum spacing=i6h
B.3 control-gate poly: (Mask#3, CGPLOY)
3.1 Minimum width=2h
3 -2 Minimum spacingr16h
3 -3 Minimum control-gate extension =6x
3 -4 Minimum active area extension of 15k
3.5 Minimum field poly to activm9k
B.4 P+ Zener region and mbstrate contacts: (Mask #4, PZENER)