T. Hatsui, RIKEN Development and Deployment Status of X-ray 2D Detector for SACLA SPring-8 Angstrom Compact free-electron LAser 1 PIXEL2012, Sep.4th, 2012 Takaki Hatsui on Behalf of SACLA Team & SOPHIAS collaboration RIKEN SPring-8 Center
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T. Hatsui, RIKEN
Development and Deployment Status of X-ray 2D Detector for SACLA
SPring-8 Angstrom Compact free-electron LAser
1 PIXEL2012, Sep.4th, 2012
Takaki Hatsui on Behalf of SACLA Team & SOPHIAS collaboration
RIKEN SPring-8 Center
T. Hatsui, RIKEN
Collaborators RIKEN, JASRI
All members of SACLA members, especially,
Togo Kudo, Takashi Kameshima, Yoichi Kirihara, Shun Ono, Tomohiko Tatsumi, Kazuo Kobayashi, Motohiko Omodani, Kyosuke Ozaki
Yasumasa Joti, Atsushi Tokuhisa
Mitsuhiro Yamaga, Arnaud Amselem, Akio Kiyomichi
Takashi Sugimoto, Toru Ohata, Toko Hirono, Masahiko Kodera, Ryotaro Tanaka, Tetsuya Ishikawa
Univ. of Hyogo
Takeo Watanabe, Tetsuo Harada, Hiroo Kinoshita
KEK Yasuo Arai, and SOIPIX collaboration
Academia Sinica Minglee Chu, Chih Hsun Lin , Shih-chang Lee
Private Sector Lapis Semiconductor, Rohm, T-Micro, A-R-Tec Corp., e2v plc, XCam Ltd, Meisei Electric,
Kyocera, Clear Pulse Co. Ltd, Hamamatsu Photonics K.K., RIGAKU Corp.
Yokogawa Digital Computing, sgi
Advisory Committee Members Peter Denes (LBNL), Yasuo Arai (KEK), Andrew Holland (The Open Univ.), and
Grzegorz Deptuch (Fermilab)
PIXEL2012, Sep.4th, 2012 2
T. Hatsui, RIKEN
Outline
PIXEL2012, Sep.4th, 2012 3
Multiport CCD under deployment at SACLA
SOI Sensor Technology
SOPHIAS for SACLA
After SOPHIAS
T. Hatsui, RIKEN PIXEL2012, Sep.4th, 2012 4
injector
Experimental Hall
SACLA (8 GeV, Compact XFEL)
SPring-8 (8 GeV SR)
• 2nd X-ray Free-Electron Laser Facility after LCLS
• Shortest wavelength lasing achieved
• Compact XFEL facility
T. Ishikawa et.al., Nature Photonics(2012)
T. Hatsui, RIKEN
Laser Stability
PIXEL2012, Sep.4th, 2012 5
Laser availability was 92~95% from March to mid. April
3 Days 3 Days
T. Hatsui, RIKEN
Sensor Development
with e2v, XCam
Readout Electronics Development
with Meisei Electronics Co. Ltd
6 PIXEL2012, Sep.4th, 2012
T. Hatsui, RIKEN
Multiport-CCD (MPCCD) Sensor Realization by Design Optimization
60 frame/sec achieved by 8 ports/sensor
Peak signal of 4.4 Me- achieved by optimized pixel design
Dead area of 300 um by optimized drive tracks
Noise < 300 e- rms is achieved by dedicated CDS readout electronics.
Device life > 30 Mrad demonstrated
50 um pixel
512 x 1024 pixels/sensor
PIXEL2012, Sep.4th, 2012 7
PSF 9 um (std.) for femtosecond 0.5 Me- injection demonstrated
Sensitive Layer: 50 um epi
Development of 300 um deep CCD is started
T. Hatsui, RIKEN
Multiport CCD Detector with 8 sensor array
8
Pixel: 50 μm□
2048 x 2048 pixels
60 frame/sec
(currently running at 30fps
PIXEL2012, Sep.4th, 2012
User Operation
2012A proposal (March-July)
25 proposals selected
More than half will use MPCCD detector
T. Hatsui, RIKEN
Deployment Example
9 PIXEL2012, Sep.4th, 2012
T. Hatsui, RIKEN 10
壽壱号
(Kotobuki)
K-B Mirror
Vacuum Path
Cryo-imaging chamber developed by Prof. Nakasako’s Gr. (Keio Univ.)
MPCCD
Octal Single/Double sample
PIXEL2012, Sep.4th, 2012
T. Hatsui, RIKEN
with Lapis Semiconductor, A-R-Tec, KEK
12 PIXEL2012, Sep.4th, 2012
See Poster #25 for details: Omodani et.al.
T. Hatsui, RIKEN
What do We need for XFEL and future (hard) X-ray SR applications?
PIXEL2012, Sep.4th, 2012 13
Observables
• Intensity
• Photon Energy
• Position
• Arrival Time
• Phase
Silicon Sensor
• Single Photon Detection
• ΔE < 120 eV
• < 1 um
• ～ psec
Pixelation Technologies • High integration >10 Mpixel
• High Speed Processing In-pixel: ～ GHz/event/pixel
I/O: Tbps/sensor
Our Choice
SOI Sensor technology
T. Hatsui, RIKEN
SOI Pixel Detector Monolithic Si Pixel Sensor with VLSI
Collaboration of KEK, and Lapis Semiconductor, and other institutions
PIXEL2012, Sep.4th, 2012 14
Advantages Summarized by KEK
• Bonded wafer → Thick High Resistivity Sensor + CMOS
• Monolithic Detector → High Density, Low material
• Standard CMOS → Complex functions in a pixel
• No mechanical bump bonding
→ High yield, Low cost
• Small input capacitance
→ ~10fF, High conversion gain, Low noise
• Based on Industrial standard technology
→ Cost benefit and Scalability
• No Latch Up, Low SEE
• Low Power
• Operate in wide temperature
(4-570K) range.
RIKEN joined SOIPIX collaboration
from the end of 2007
Control of charge collection
SOPHIAS
T. Hatsui, RIKEN
2007 when RIKEN joined SOIPIX collaboration
Back-gate effect
Handle wafer resistivity was low after CMOS process.
• ～400 ohm/cm
Small sensor chip size compared to other technology
• 20 mm x 20 mm
Devices were for digital, not for analog circuitry.
X-ray Radiation hardness was not evaluated.
SOI Pixel Technology Process/Device/Simulation
PIXEL2012, Sep.4th, 2012 15
Current Status
Buried P-well proposed by KEK, and now extensively used.
T. Hatsui, RIKEN
Critical Achievements in Process Technologies for XFEL applications 8 Inch FZ SOI wafer for full depletion of 500 um
PIXEL2012, Sep.4th, 2012 16
Courtesy of Lapis Semiconductor
T. Hatsui, RIKEN
Critical Achievements in Process Technologies for XFEL applications Backside processing
PIXEL2012, Sep.4th, 2012 17
0.3 um
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
Char
ge
Depth from back side (um)
Device Simulation Results
Backside Processing
• CMP
• Wet etching
• Implant
• Laser annealing
• Al deposition
ー w/o Al
ー with Al
Inverse current
T. Hatsui, RIKEN 18
◆Stitching Process: Intermediate Observation
10um
Buffer
10um
Shot A Shot A
Shot A Shot B
◆Stitching Layers: guard rings, M1
◆ Pixel Gap by Stitching is designed to match to the pixel size of 30 um
◆Stitching error in X/Y directions < 0.025 um Courtesy of Lapis Semiconductor
PIXEL2012, Sep.4th, 2012
T. Hatsui, RIKEN
Device/Process Introduction Critical for SOPHAS
PIXEL2012, Sep.4th, 2012 19
Courtesy of A-R-Tec
Introduced for SOPHIAS
MIM Cap.
onto 3M
Diode Cell for temp. sensor/circuitry
Introduction of I/O Tr
for Vdd=2.5 V Operation
5M for minimizing
IR drop
T. Hatsui, RIKEN
1/f & 1/f2 Noise Suppression
PIXEL2012, Sep.4th, 2012 20
Fully Depleted SOI Transistor (FD-SOI Tr): Body Floating Tr
Large 1/f noise due to body floating
Source Tie/Body Tie Tr Pcell has been introduced. 1/f & 1/f2 noise simulation environment has been
successfully introduced.
Courtesy of A-R-Tec
T. Hatsui, RIKEN
1/f Noise: Simulation and Measurement by Test Chip
PIXEL2012, Sep.4th, 2012 21
15.4
mm
7.5mm
SOPHIAS Test Chip
MIVAPIX2
30m
m
64.8mm
X
T. Hatsui, RIKEN
2007 when RIKEN joined SOIPIX collaboration
Back-gate effect
Handle wafer resistivity was low after CMOS process.
• ～400 ohm/cm
Small sensor chip size compared to other technology
• 20 mm x 20 mm
Devices were for digital, not for analog circuitry.
X-ray Radiation hardness was not evaluated.
Current Status
Buried P-well proposed by KEK, and now extensively used.
FZ with > 3 kohm/cm
Stitching 66 mm x 30 mm achieved 130 mm x 130 mm is possible
4M to 5M, MIM Cap onto 3M
1/f noise suppression by Source-tie and body-tie Tr.
Simulation environment improvement.
Currently upto 150 krad for Tr. → SOPHIAS is for < 7 keV with back-illumination
Systematic study of the radiation damage has been started Design Optimization by
radiation damaged device models
New devices
SOI Pixel Technology Process/Device/Simulation
PIXEL2012, Sep.4th, 2012 22
T. Hatsui, RIKEN
78 Me-
17.6 Me-
～ 6Me-
SOPHIAS Silicon-On-Insulator Photon-Imaging Array Sensor
by using SOI Sensor Technology
PIXEL2012, Sep.4th, 2012 23
with A-R-Tec, ARKUS, and Tokyo Electron Devices, Kyocera
See Poster #25 for details: Omodani et.al.
Peak Signal/100 um□ • Peak Signal 7 Me-
• Noise 100 e-
(Effective 16.1 bit)
• Dual gain pixel
• 30 um□ pixel
• 1.9 M pixel/chip
• 60 frame/sec
T. Hatsui, RIKEN PIXEL2012, Sep.4th, 2012 24
Pixel
Via
SOPHIAS Pixel Layout
by Multi-Via Concept
Low Gain Via : 4
High Gain Via : 24 High gain
Low gain Via
+ + + +
- - - -
X-ray
SiO2
Sensor
n-
p+
30 um□pixel
T. Hatsui, RIKEN
SOPHIAS In-pixel Schematics
PIXEL2012, Sep.4th, 2012 25
Gain Csens [fF] Via # Gain [uV/e]
High 16 24 7.2
Low 240 4 0.15
Output
Col Amp. & Aout Amp. Csens
240 fF
Output
Col Amp. & Aout Amp. Csens
16 fF
………
High gain
Low gain
24
4
x48
T. Hatsui, RIKEN
SOIPHIAS Sensor
PIXEL2012, Sep.4th, 2012 26
64 mm
30 m
m
All the Periphery Circuit incl. row registers
Guard Ring
3-side buttable
4-side buttable with stepped geometry
T. Hatsui, RIKEN PIXEL2012, Sep.4th, 2012 27
25 msec Exposure Ag 20 kV 0.2 mA
64 mm
26.7
mm
Raw Data
T. Hatsui, RIKEN
X-ray Image
PIXEL2012, Sep.4th, 2012 28
800 700 600 500 400 300 200 100 0
1500
2 mm
T. Hatsui, RIKEN
1st Submission of Full Sensor Chip Offset Variation
PIXEL2012, Sep.4th, 2012 29
Data taken by Test Camera
• Dead pixel: 0
• Readout port: 6
• Readout Speed: 25 MHz/pixel
equivalent to
60 frame/sec with off-chip Digital CDS
120 frame/sec without off-chip digital CDS
100
101
102
103
104
-400 -200 0 200 400
Dead Pixel: None
Defect Pixel defined as offset > 200 meV
ratio 2.7 x 10^-5
53 pixels /1.9 Mpixel
T. Hatsui, RIKEN
Deployment Schedule of SOPHIAS
PIXEL2012, Sep.4th, 2012 30
• Deploy to user operation in 2014
• Sensor capable of 60 frame/sec, but limited to 30 frame/sec due to Cameralink Interface bandwidth
• 3.8 Mpixel
Dual-Sensor Detector
• Release target TBD
• 60 frame/sec
• max 80 Mpixel
• with E/O, calibration FPGA, and CLHS
Multi-Sensor Detector
T. Hatsui, RIKEN
Future Applications
PIXEL2012, Sep.4th, 2012 31
SPring-8 II Coherent flux of source
x 1000 in 10 keV region More flux increase at sample position
A Target Candidate X-ray Photon Correlation Spectroscopy (XPCS) in nanosecond regime
Provisional Demands for Detectors Data frame acquisition at 23.6 nsec interval, (or 1.966 nsec interval at best) in burst mode
Medical Applications In collab. with Lapis Semiconductor and Rohm group.
Coherent Flux
x 1000
T. Hatsui, RIKEN
SOI Pixel Detector Monolithic Si Pixel Sensor with VLSI
Collaboration of KEK, and Lapis Semiconductor, and other institutions
PIXEL2012, Sep.4th, 2012 32
Advantages Summarized by KEK
• Bonded wafer → Thick High Resistivity Sensor + CMOS
• Monolithic Detector → High Density, Low material
• Standard CMOS → Complex functions in a pixel
• No mechanical bump bonding
→ High yield, Low cost
• Small input capacitance
→ ~10fF, High conversion gain, Low noise
• Based on Industrial standard technology
→ Cost benefit and Scalability
• No Latch Up, Low SEE
• Low Power
• Operate in wide temperature
(4-570K) range.
RIKEN joined SOIPIX collaboration
from the end of 2007
Sample Hold Electronics
With 20 ENC at close to GHz rate
Control of charge collection
SOPHIAS
Charge transimpedance amplifier is not needed.
Speed and noise is not in trade-off relationship
in conventional way.
T. Hatsui, RIKEN
Preliminary Functional Blocks
33
Control logic
Analog Memory
256 p
ixel (=
30.7
2m
m)
540 pixel (=64.8 mm)
Glo
bal T
imin
g Track
Colu
mn Sign
al Track
s
Global Timing Track from upper and lower pads → timing delay < 1nsc
Design optimization should be carried out.
ADC
Assumed Parameter: 120 um□ pixel, 10 bit ADC, Analog: noise 50 e- Peak 100 ke-
PIXEL2012, Sep.4th, 2012
Technology for 1 nsec framing will be in our hand.
Readout remain in 10-100 kframe/sec.
Exposure/readout ratio is low.
• Optimized operation
• Off-pixel processing
• Integrate new technology, such as 3D integration
for higher readout rate
T. Hatsui, RIKEN
Summary
PIXEL2012, Sep.4th, 2012 34
MPCCD under deployment
• Large Peak Signal of 4.4 Me- achieved.
• Upgrade with Deep 300 um CCD process has started
SOI Sensor Technology
• Ramping up to real (hard) X-ray applications.
• For SR &XFEL, limited up to 7 keV due to rad. hardness
SOPHIAS
• Peak Signal 7 Me-, Noise 100 e-, Dual gain pixel, 30 um□ pixel, 1.9 M pixel/chip
• To be deployed in 2014 with 3.8 M pixels
• Major tasks
• Pixel-by-pixel Calibration
After SOPHIAS
• Low input capacitance
• Fast shutter in the nanosecond regime
See Poster #25 for details: Omodani et.al.
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