Detector Array Controller Based on Detector Array Controller Based on First Light First Light PICNIC Array Mux PICNIC Array Mux Image of ESO Messenger Image of ESO Messenger Front Page Front Page M.Meyer M.Meyer June 05 June 05 NGC NGC High Speed Serial Link Technology High Speed Serial Link Technology [ IRDT and ODT ] [ IRDT and ODT ]
NGC. Detector Array Controller Based on. High Speed Serial Link Technology. First Light PICNIC Array Mux Image of ESO Messenger Front Page. [ IRDT and ODT ]. M.Meyer June 05. Conventional Approach : Acquisition System (IRACE). PCI Interface. Communication and Data Transfer. - PowerPoint PPT Presentation
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Detector Array Controller Based onDetector Array Controller Based on
First LightFirst Light
PICNIC Array MuxPICNIC Array Mux
Image of ESO Image of ESO Messenger Front Messenger Front
PagePageM.MeyerM.Meyer
June 05June 05
NGC NGC
High Speed Serial Link TechnologyHigh Speed Serial Link Technology
[ IRDT and ODT ][ IRDT and ODT ]
Conventional Approach :Conventional Approach :Acquisition System (IRACE)Acquisition System (IRACE)
CommunicationCommunication and Data Transferand Data Transfer
SequencerSequencer Clock and BiasClock and BiasAcquisitiAcquisitionon
Module(Module(s)s)
PCI PCI InterfaceInterface
NGC Prototype - Minimum SystemNGC Prototype - Minimum System
Back-End and Front-End ( Four ChannelsBack-End and Front-End ( Four Channels ) ) NGC is a modular system for IR detector NGC is a modular system for IR detector
and CCD readout with a Back-end, a and CCD readout with a Back-end, a basic Front-end unit containing a basic Front-end unit containing a complete four channel system on one complete four channel system on one card and additional boards like multi card and additional boards like multi channel ADC units and more...channel ADC units and more...
There is no processor, no parallel inter-There is no processor, no parallel inter-module data bus on the front-end side. module data bus on the front-end side. Advanced FPGA link technology is used Advanced FPGA link technology is used to replace conventional logic to replace conventional logic
Connection between Back and Front-end with high speed fiber links at 2.5GBit/s
Connection between Front-end modules with high speed copper links at 2.5GBit/s.
Power Consumption on this Front-end is less than 10 Watts
( Excluding power supply )
This Front-End system does not require big cooling boxes
System Noise on PrototypeSystem Noise on Prototype
11 22
3344
Back-EndBack-EndVirtexII ProVirtexII Pro
Contains :Contains :
PCI 64 IF (IP)PCI 64 IF (IP)
CommunicatioCommunicationn
DMA Data DMA Data TransferTransfer
Fiber opticsFiber optics
Back-End
PCI BUS Interface
XILINX IP
TX COM #10
RX COM #10
Header #02
STATUS REG # 14
COMMAND REG #1C
VIDEO FIFO Header #01
PCI REGISTERS SLAVE IF
MASTER IF
Rx
Tx
DOWNSTREAM LINK
Back-EndBack-End
Function is based on the XILINX Virtex Function is based on the XILINX Virtex Pro FPGA XC2VP7 FF 672 Pro FPGA XC2VP7 FF 672
Back-End PCI is a 64 Bit PCI boardBack-End PCI is a 64 Bit PCI board FPGA contains PCI interface toFPGA contains PCI interface to Communication functionsCommunication functions DMA data channelDMA data channel Status and CommandStatus and Command Direct interface from FPGA to PCI Direct interface from FPGA to PCI
without glue logicwithout glue logic
PCI master and PCI slave are PCI master and PCI slave are independentindependent
Communication and data transfers all Communication and data transfers all on serial link with RocketIO on serial link with RocketIO transceiverstransceivers
Handshake communication to Front-Handshake communication to Front-EndEnd
Data rate on one channel between Data rate on one channel between front and back-end ~ 200MByte/sfront and back-end ~ 200MByte/s
Front-EndFront-End
CLOCK and BIASCLOCK and BIASVirtexII ProVirtexII Pro
Contains :Contains :
CommunicatioCommunicationn
Data transferData transfer
SequencerSequencer
TelemetryTelemetry
Glue logicGlue logic
AcquisitionAcquisition
4 Channels4 Channels
16/18 Bit16/18 Bit
MonitoringMonitoring
TelemetryTelemetry
16 Bit16 Bit
Front-EndFront-End
COM IF
Rx NEXT LINK IF
STATUS REG
Tx
Tx
Rx
SEQUENCER
AQ MANAGER
AQ FIFO 1
AQ FIFO
CLOCK and BIAS
TX COM
DOWNSTREAM RX LINK
On Board ADCs
DOWNSTREAM TX LINK
CONFIG REGISTER
SYSTEM RESET
MONITOR
TELEMETRY
LINK CONFIG
UPSTREAM RX LINK
UPSTREAM TX LINK
Front-EndFront-End Function is based on the XILINX Virtex Pro Function is based on the XILINX Virtex Pro
FPGA XC2VP7 FF 672 FPGA XC2VP7 FF 672 FPGA contains link interface for FPGA contains link interface for
communication and data transfer with communication and data transfer with RocketIO transceivers, sequencer, system RocketIO transceivers, sequencer, system administration, interface to acquisition, administration, interface to acquisition, clock and bias, telemetry and monitoringclock and bias, telemetry and monitoring
Four ADC channels ( 16 or 18Bit)Four ADC channels ( 16 or 18Bit)
16 clocks, 20 biases16 clocks, 20 biases
TelemetryTelemetry
MonitoringMonitoring
Data rate on one channel between front-Data rate on one channel between front-end modules and front to back-end ~ end modules and front to back-end ~ 200MByte200MByte
Handshake for communication to back-endHandshake for communication to back-end
Galvanic isolated trigger input and control Galvanic isolated trigger input and control outputs outputs
Connection to detector ASIC’s - all Connection to detector ASIC’s - all communication and data transfer to the communication and data transfer to the back-end can be handled with the same back-end can be handled with the same firmware already contained in the FPGA firmware already contained in the FPGA
Number of Slices: 2508 out of 4928Number of Slices: 2508 out of 4928 50% 50% Number of Slice Flip Flops: 3043 out of 9856Number of Slice Flip Flops: 3043 out of 9856 30% 30% Number of 4 input LUTs: 4190 out of 9856Number of 4 input LUTs: 4190 out of 9856 42% 42% Number of bonded IOBs: 124 out of 396 31% Number of bonded IOBs: 124 out of 396 31% Number of TBUFs: 160 out of 2720Number of TBUFs: 160 out of 2720 5% 5% Number of BRAMs: 25 out of 44Number of BRAMs: 25 out of 44 56% 56% Number of GCLKs: 3 out of 16Number of GCLKs: 3 out of 16 18% 18% Number of GTs: 4 out of 8Number of GTs: 4 out of 8 50% 50% Number of DCMs: 1 out of 4Number of DCMs: 1 out of 4 25% 25%
Signals to route : Signals to route : 22530 22530
Used language : VHDLUsed language : VHDL
RX COM
HEADER #2
FUNCTION # ADDR
Rx NEXT LINK
HEADER #5
RX COM
HEADER #2
FUNCTION # ADDR
Rx NEXT LINK
HEADER #5
Board 1
Board 2
PACKET STRUCTURE
… | DATA | DATA | WRITE | ADDR | … | HEADER2 | HEADER1
WRITE DATA TO ADDRESS
READ n WORDS | ADDR | … | HEADER2 | HEADER1 READ n WORDS FROM ADDRESS
OPTIONAL
OPTIONAL
Tx Tx
Data Packet from Back-End
LINK COMMUNICATION PRINCIPLE
Communication and Data TransferCommunication and Data Transfer
Communication and data transfer is handled with the Virtex Pro FPGA’s Gigabit transceivers
The communication between all system modules is based on packet transmission over serial links
A packet structure is
defined to address a function ( e.g. a register or memory in a front-end module) for read or write
From the Back-End ( PCI board ) the packets can be routed to and through each board in the Front-End
Data are routed with the
same structure from the acquisition modules to the Back-End